IT1303282B1 - Cella di memoria di tipo eeprom con soglia regolata mediante impiantoe procedimeento per la sua fabbricazione. - Google Patents

Cella di memoria di tipo eeprom con soglia regolata mediante impiantoe procedimeento per la sua fabbricazione.

Info

Publication number
IT1303282B1
IT1303282B1 IT1998MI002334A ITMI982334A IT1303282B1 IT 1303282 B1 IT1303282 B1 IT 1303282B1 IT 1998MI002334 A IT1998MI002334 A IT 1998MI002334A IT MI982334 A ITMI982334 A IT MI982334A IT 1303282 B1 IT1303282 B1 IT 1303282B1
Authority
IT
Italy
Prior art keywords
implant
procedure
manufacture
memory cell
type memory
Prior art date
Application number
IT1998MI002334A
Other languages
English (en)
Inventor
Carlo Cremonesi
Bruno Vajana
Roberta Bottini
Libera Giovanna Dalla
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT1998MI002334A priority Critical patent/IT1303282B1/it
Priority to US09/431,301 priority patent/US6329254B1/en
Publication of ITMI982334A1 publication Critical patent/ITMI982334A1/it
Application granted granted Critical
Publication of IT1303282B1 publication Critical patent/IT1303282B1/it
Priority to US09/976,484 priority patent/US20020020872A1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
IT1998MI002334A 1998-10-30 1998-10-30 Cella di memoria di tipo eeprom con soglia regolata mediante impiantoe procedimeento per la sua fabbricazione. IT1303282B1 (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT1998MI002334A IT1303282B1 (it) 1998-10-30 1998-10-30 Cella di memoria di tipo eeprom con soglia regolata mediante impiantoe procedimeento per la sua fabbricazione.
US09/431,301 US6329254B1 (en) 1998-10-30 1999-10-29 Memory cell of the EEPROM type having its threshold adjusted by implantation, and fabrication method
US09/976,484 US20020020872A1 (en) 1998-10-30 2001-10-12 Memory cell of the EEPROM type having its threshold adjusted by implantation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT1998MI002334A IT1303282B1 (it) 1998-10-30 1998-10-30 Cella di memoria di tipo eeprom con soglia regolata mediante impiantoe procedimeento per la sua fabbricazione.

Publications (2)

Publication Number Publication Date
ITMI982334A1 ITMI982334A1 (it) 2000-04-30
IT1303282B1 true IT1303282B1 (it) 2000-11-06

Family

ID=11380973

Family Applications (1)

Application Number Title Priority Date Filing Date
IT1998MI002334A IT1303282B1 (it) 1998-10-30 1998-10-30 Cella di memoria di tipo eeprom con soglia regolata mediante impiantoe procedimeento per la sua fabbricazione.

Country Status (2)

Country Link
US (2) US6329254B1 (it)
IT (1) IT1303282B1 (it)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010102269A (ko) * 1999-12-21 2001-11-15 롤페스 요하네스 게라투스 알베르투스 하나의 기판 상에 적어도 하나의 메모리 셀과 적어도하나의 로직 트랜지스터를 제조하는 방법 및 하나의 기판상에 적어도 하나의 메모리 셀과 적어도 하나의 고전압트랜지스터를 제조하는 방법 및 반도체 장치
US6958271B1 (en) * 2003-08-04 2005-10-25 Advanced Micro Devices, Inc. Method of fabricating a dual-level stacked flash memory cell with a MOSFET storage transistor
TWI228800B (en) * 2003-11-06 2005-03-01 Ememory Technology Inc Non-volatile memory cell and related method
US7190623B2 (en) * 2003-11-06 2007-03-13 Ememory Technologies Inc. Non-volatile memory cell and method of operating the same
US7262457B2 (en) * 2004-01-05 2007-08-28 Ememory Technology Inc. Non-volatile memory cell
CN102760737A (zh) * 2011-04-28 2012-10-31 上海华虹Nec电子有限公司 浮栅型eeprom器件及其制造方法
TWI701770B (zh) * 2018-07-24 2020-08-11 華邦電子股份有限公司 非揮發性記憶體裝置及其製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5486487A (en) * 1990-03-30 1996-01-23 Sgs-Thomson Microelectronics S.R.L. Method for adjusting the threshold of a read-only memory to achieve low capacitance and high breakdown voltage
US5908311A (en) * 1996-07-25 1999-06-01 National Semiconductor Corporation Method for forming a mixed-signal CMOS circuit that includes non-volatile memory cells

Also Published As

Publication number Publication date
ITMI982334A1 (it) 2000-04-30
US6329254B1 (en) 2001-12-11
US20020020872A1 (en) 2002-02-21

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Legal Events

Date Code Title Description
0001 Granted