IT1270180B - Method and device for locking on frame synchronisation in a digital information system - Google Patents

Method and device for locking on frame synchronisation in a digital information system

Info

Publication number
IT1270180B
IT1270180B ITMI941188A ITMI941188A IT1270180B IT 1270180 B IT1270180 B IT 1270180B IT MI941188 A ITMI941188 A IT MI941188A IT MI941188 A ITMI941188 A IT MI941188A IT 1270180 B IT1270180 B IT 1270180B
Authority
IT
Italy
Prior art keywords
bits
locking
groups
frame synchronisation
information system
Prior art date
Application number
ITMI941188A
Other languages
Italian (it)
Inventor
Sante Andreoli
Giovanni Castagna
Original Assignee
Italtel Cerm L Aquila S C P A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Italtel Cerm L Aquila S C P A filed Critical Italtel Cerm L Aquila S C P A
Priority to ITMI941188A priority Critical patent/IT1270180B/en
Publication of ITMI941188A0 publication Critical patent/ITMI941188A0/en
Publication of ITMI941188A1 publication Critical patent/ITMI941188A1/en
Application granted granted Critical
Publication of IT1270180B publication Critical patent/IT1270180B/en

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Landscapes

  • Detection And Prevention Of Errors In Transmission (AREA)
  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

Method and circuit for locking on frame synchronisation in telecommunications systems, based on digital techniques, especially SDH telecommunications systems. It enables the programming of parameters which optimise the alignment strategy, while maintaining a simple circuit implementation. The proposed system employs aggregation of the bits of the sequence received in groups of bits which are compared with the corresponding bits of the synchronisation word, allowing predetermined error levels xr, xv, in the individual groups of bits. The system further provides for checking when predetermined thresholds Sr, Sv are exceeded in the number of groups of received bits. <IMAGE>
ITMI941188A 1994-06-08 1994-06-08 Method and device for locking on frame synchronisation in a digital information system IT1270180B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
ITMI941188A IT1270180B (en) 1994-06-08 1994-06-08 Method and device for locking on frame synchronisation in a digital information system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITMI941188A IT1270180B (en) 1994-06-08 1994-06-08 Method and device for locking on frame synchronisation in a digital information system

Publications (3)

Publication Number Publication Date
ITMI941188A0 ITMI941188A0 (en) 1994-06-08
ITMI941188A1 ITMI941188A1 (en) 1995-12-08
IT1270180B true IT1270180B (en) 1997-04-29

Family

ID=11369070

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI941188A IT1270180B (en) 1994-06-08 1994-06-08 Method and device for locking on frame synchronisation in a digital information system

Country Status (1)

Country Link
IT (1) IT1270180B (en)

Also Published As

Publication number Publication date
ITMI941188A1 (en) 1995-12-08
ITMI941188A0 (en) 1994-06-08

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Legal Events

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970613