IT1241662B - MEMORY TO REDUNDANCY USING LINE OF WORD FROM MEMORY - Google Patents

MEMORY TO REDUNDANCY USING LINE OF WORD FROM MEMORY

Info

Publication number
IT1241662B
IT1241662B IT19590A IT1959090A IT1241662B IT 1241662 B IT1241662 B IT 1241662B IT 19590 A IT19590 A IT 19590A IT 1959090 A IT1959090 A IT 1959090A IT 1241662 B IT1241662 B IT 1241662B
Authority
IT
Italy
Prior art keywords
memory
redundancy
word
line
Prior art date
Application number
IT19590A
Other languages
Italian (it)
Other versions
IT9019590A1 (en
IT9019590A0 (en
Inventor
Sherif Sweha
Mark Bauer
Phil Kliza
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of IT9019590A0 publication Critical patent/IT9019590A0/en
Publication of IT9019590A1 publication Critical patent/IT9019590A1/en
Application granted granted Critical
Publication of IT1241662B publication Critical patent/IT1241662B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/781—Masking faults in memories by using spares or by reconfiguring using programmable devices combined in a redundant decoder
IT19590A 1989-03-10 1990-03-07 MEMORY TO REDUNDANCY USING LINE OF WORD FROM MEMORY IT1241662B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US32190489A 1989-03-10 1989-03-10

Publications (3)

Publication Number Publication Date
IT9019590A0 IT9019590A0 (en) 1990-03-07
IT9019590A1 IT9019590A1 (en) 1991-09-07
IT1241662B true IT1241662B (en) 1994-01-26

Family

ID=23252548

Family Applications (1)

Application Number Title Priority Date Filing Date
IT19590A IT1241662B (en) 1989-03-10 1990-03-07 MEMORY TO REDUNDANCY USING LINE OF WORD FROM MEMORY

Country Status (4)

Country Link
JP (1) JPH02278600A (en)
GB (1) GB2229021B (en)
HK (1) HK1000974A1 (en)
IT (1) IT1241662B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9305801D0 (en) * 1993-03-19 1993-05-05 Deans Alexander R Semiconductor memory system
FR2716732B1 (en) * 1994-02-28 1996-04-19 Sgs Thomson Microelectronics Redundancy memory addressing system.
DE69412234T2 (en) * 1994-03-29 1999-06-17 Sgs-Thomson Microelectronics S.R.L., Agrate Brianza, Mailand/Milano Redundancy circuit for a semiconductor memory device
US6259309B1 (en) * 1999-05-05 2001-07-10 International Business Machines Corporation Method and apparatus for the replacement of non-operational metal lines in DRAMS

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57130298A (en) * 1981-02-06 1982-08-12 Hitachi Ltd Semiconductor integrated circuit memory and relieving method for its fault

Also Published As

Publication number Publication date
GB9000359D0 (en) 1990-03-07
IT9019590A1 (en) 1991-09-07
GB2229021A (en) 1990-09-12
IT9019590A0 (en) 1990-03-07
HK1000974A1 (en) 1998-05-15
GB2229021B (en) 1993-03-31
JPH02278600A (en) 1990-11-14

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19980327