IT1199342B - ELECTRICALLY ERASABLE PROGRAMMABLE MEMORY LATCH EQUIPPED WITH REDUNDANCY, COMBINED WITH MAJORITY CIRCUIT AND WITH REDUNDANCY LOSS DETECTOR CIRCUIT - Google Patents

ELECTRICALLY ERASABLE PROGRAMMABLE MEMORY LATCH EQUIPPED WITH REDUNDANCY, COMBINED WITH MAJORITY CIRCUIT AND WITH REDUNDANCY LOSS DETECTOR CIRCUIT

Info

Publication number
IT1199342B
IT1199342B IT48784/86A IT4878486A IT1199342B IT 1199342 B IT1199342 B IT 1199342B IT 48784/86 A IT48784/86 A IT 48784/86A IT 4878486 A IT4878486 A IT 4878486A IT 1199342 B IT1199342 B IT 1199342B
Authority
IT
Italy
Prior art keywords
redundancy
circuit
combined
erasable programmable
electrically erasable
Prior art date
Application number
IT48784/86A
Other languages
Italian (it)
Other versions
IT8648784A0 (en
Inventor
Giuseppe Savarese
Sossio Vergara
Original Assignee
Texas Instruments Italia Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Italia Spa filed Critical Texas Instruments Italia Spa
Priority to IT48784/86A priority Critical patent/IT1199342B/en
Publication of IT8648784A0 publication Critical patent/IT8648784A0/en
Application granted granted Critical
Publication of IT1199342B publication Critical patent/IT1199342B/en

Links

IT48784/86A 1986-12-23 1986-12-23 ELECTRICALLY ERASABLE PROGRAMMABLE MEMORY LATCH EQUIPPED WITH REDUNDANCY, COMBINED WITH MAJORITY CIRCUIT AND WITH REDUNDANCY LOSS DETECTOR CIRCUIT IT1199342B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
IT48784/86A IT1199342B (en) 1986-12-23 1986-12-23 ELECTRICALLY ERASABLE PROGRAMMABLE MEMORY LATCH EQUIPPED WITH REDUNDANCY, COMBINED WITH MAJORITY CIRCUIT AND WITH REDUNDANCY LOSS DETECTOR CIRCUIT

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT48784/86A IT1199342B (en) 1986-12-23 1986-12-23 ELECTRICALLY ERASABLE PROGRAMMABLE MEMORY LATCH EQUIPPED WITH REDUNDANCY, COMBINED WITH MAJORITY CIRCUIT AND WITH REDUNDANCY LOSS DETECTOR CIRCUIT

Publications (2)

Publication Number Publication Date
IT8648784A0 IT8648784A0 (en) 1986-12-23
IT1199342B true IT1199342B (en) 1988-12-30

Family

ID=11268540

Family Applications (1)

Application Number Title Priority Date Filing Date
IT48784/86A IT1199342B (en) 1986-12-23 1986-12-23 ELECTRICALLY ERASABLE PROGRAMMABLE MEMORY LATCH EQUIPPED WITH REDUNDANCY, COMBINED WITH MAJORITY CIRCUIT AND WITH REDUNDANCY LOSS DETECTOR CIRCUIT

Country Status (1)

Country Link
IT (1) IT1199342B (en)

Also Published As

Publication number Publication date
IT8648784A0 (en) 1986-12-23

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19941006