IT1114185B - Addizionatore perfezionato - Google Patents

Addizionatore perfezionato

Info

Publication number
IT1114185B
IT1114185B IT31120/77A IT3112077A IT1114185B IT 1114185 B IT1114185 B IT 1114185B IT 31120/77 A IT31120/77 A IT 31120/77A IT 3112077 A IT3112077 A IT 3112077A IT 1114185 B IT1114185 B IT 1114185B
Authority
IT
Italy
Prior art keywords
perfected
adjuster
perfected adjuster
Prior art date
Application number
IT31120/77A
Other languages
English (en)
Italian (it)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT1114185B publication Critical patent/IT1114185B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3832—Less usual number representations
    • G06F2207/3844—Hexadecimal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4921—Single digit adding or subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
IT31120/77A 1977-01-10 1977-12-22 Addizionatore perfezionato IT1114185B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/758,378 US4118786A (en) 1977-01-10 1977-01-10 Integrated binary-BCD look-ahead adder

Publications (1)

Publication Number Publication Date
IT1114185B true IT1114185B (it) 1986-01-27

Family

ID=25051516

Family Applications (1)

Application Number Title Priority Date Filing Date
IT31120/77A IT1114185B (it) 1977-01-10 1977-12-22 Addizionatore perfezionato

Country Status (6)

Country Link
US (1) US4118786A (US06566495-20030520-M00011.png)
JP (1) JPS5387638A (US06566495-20030520-M00011.png)
DE (1) DE2800598A1 (US06566495-20030520-M00011.png)
FR (1) FR2377063A1 (US06566495-20030520-M00011.png)
GB (1) GB1593336A (US06566495-20030520-M00011.png)
IT (1) IT1114185B (US06566495-20030520-M00011.png)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL59907A0 (en) * 1980-04-23 1980-06-30 Nathan Grundland Arithmetic logic unit
US4866656A (en) * 1986-12-05 1989-09-12 American Telephone And Telegraph Company, At&T Bell Laboratories High-speed binary and decimal arithmetic logic unit
JPH01115341A (ja) * 1987-10-29 1989-05-08 Nagashima Ika Kikai Kk 総合視運動検査装置におけるプロジェクタ
JPH01115340A (ja) * 1987-10-29 1989-05-08 Nagashima Ika Kikai Kk 総合視運動検査装置
US7325025B2 (en) * 2001-12-18 2008-01-29 Intel Corporation Look-ahead carry adder circuit
US7299254B2 (en) * 2003-11-24 2007-11-20 International Business Machines Corporation Binary coded decimal addition
US7546328B2 (en) * 2004-08-31 2009-06-09 Wisconsin Alumni Research Foundation Decimal floating-point adder
US7743084B2 (en) * 2004-09-23 2010-06-22 Wisconsin Alumni Research Foundation Processing unit having multioperand decimal addition

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3596074A (en) * 1969-06-12 1971-07-27 Ibm Serial by character multifunctional modular unit
US3629565A (en) * 1970-02-13 1971-12-21 Ibm Improved decimal adder for directly implementing bcd addition utilizing logic circuitry
US3711693A (en) * 1971-06-30 1973-01-16 Honeywell Inf Systems Modular bcd and binary arithmetic and logical system
US3752394A (en) * 1972-07-31 1973-08-14 Ibm Modular arithmetic and logic unit
US3958112A (en) * 1975-05-09 1976-05-18 Honeywell Information Systems, Inc. Current mode binary/bcd arithmetic array
JPS5384647A (en) * 1976-12-30 1978-07-26 Fujitsu Ltd High-speed adder for binary and decimal

Also Published As

Publication number Publication date
FR2377063B1 (US06566495-20030520-M00011.png) 1980-01-04
FR2377063A1 (fr) 1978-08-04
GB1593336A (en) 1981-07-15
JPS5387638A (en) 1978-08-02
US4118786A (en) 1978-10-03
JPS5628303B2 (US06566495-20030520-M00011.png) 1981-07-01
DE2800598A1 (de) 1978-07-13

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