IT1072410B - Procedimento di decodificazione di un codice a doppia frequenza e dispositivo per la sua messa in opera - Google Patents
Procedimento di decodificazione di un codice a doppia frequenza e dispositivo per la sua messa in operaInfo
- Publication number
- IT1072410B IT1072410B IT2753476A IT2753476A IT1072410B IT 1072410 B IT1072410 B IT 1072410B IT 2753476 A IT2753476 A IT 2753476A IT 2753476 A IT2753476 A IT 2753476A IT 1072410 B IT1072410 B IT 1072410B
- Authority
- IT
- Italy
- Prior art keywords
- double frequency
- frequency code
- decoding procedure
- decoding
- procedure
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
- G06K7/01—Details
- G06K7/016—Synchronisation of sensing process
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
- G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Artificial Intelligence (AREA)
- Computer Vision & Pattern Recognition (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR7529259A FR2326082A1 (fr) | 1975-09-24 | 1975-09-24 | Procede de decodage d'un code double frequence et dispositif pour la mise en oeuvre du procede |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| IT1072410B true IT1072410B (it) | 1985-04-10 |
Family
ID=9160385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT2753476A IT1072410B (it) | 1975-09-24 | 1976-09-23 | Procedimento di decodificazione di un codice a doppia frequenza e dispositivo per la sua messa in opera |
Country Status (7)
| Country | Link |
|---|---|
| BE (1) | BE845971A (enExample) |
| DE (1) | DE2642422A1 (enExample) |
| DK (1) | DK429276A (enExample) |
| FR (1) | FR2326082A1 (enExample) |
| IT (1) | IT1072410B (enExample) |
| LU (1) | LU75819A1 (enExample) |
| NL (1) | NL7610590A (enExample) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2506543B1 (fr) * | 1981-05-22 | 1986-12-05 | Thomson Csf | Dispositif de decodage d'un signal code sur une seule voie et notamment d'informations lues a vitesse variable et/ou inscrites a densite variable |
-
1975
- 1975-09-24 FR FR7529259A patent/FR2326082A1/fr active Granted
-
1976
- 1976-09-09 BE BE1007613A patent/BE845971A/xx unknown
- 1976-09-17 LU LU75819A patent/LU75819A1/xx unknown
- 1976-09-21 DE DE19762642422 patent/DE2642422A1/de active Pending
- 1976-09-23 IT IT2753476A patent/IT1072410B/it active
- 1976-09-23 DK DK429276A patent/DK429276A/da unknown
- 1976-09-23 NL NL7610590A patent/NL7610590A/xx not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| FR2326082B1 (enExample) | 1978-03-17 |
| BE845971A (fr) | 1977-03-09 |
| DE2642422A1 (de) | 1977-03-31 |
| LU75819A1 (enExample) | 1977-05-13 |
| DK429276A (da) | 1977-03-25 |
| FR2326082A1 (fr) | 1977-04-22 |
| NL7610590A (nl) | 1977-03-28 |
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