IN2015DN03134A - - Google Patents

Info

Publication number
IN2015DN03134A
IN2015DN03134A IN3134DEN2015A IN2015DN03134A IN 2015DN03134 A IN2015DN03134 A IN 2015DN03134A IN 3134DEN2015 A IN3134DEN2015 A IN 3134DEN2015A IN 2015DN03134 A IN2015DN03134 A IN 2015DN03134A
Authority
IN
India
Prior art keywords
processing unit
level
cache
processor
hierarchy
Prior art date
Application number
Other languages
English (en)
Inventor
Paul Edward Kitchin
William L Walker
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of IN2015DN03134A publication Critical patent/IN2015DN03134A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4418—Suspend and resume; Hibernate and awake

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
IN3134DEN2015 2012-10-17 2013-10-16 IN2015DN03134A (enrdf_load_stackoverflow)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/653,744 US20140108734A1 (en) 2012-10-17 2012-10-17 Method and apparatus for saving processor architectural state in cache hierarchy
PCT/US2013/065178 WO2014062764A1 (en) 2012-10-17 2013-10-16 Method and apparatus for saving processor architectural state in cache hierarchy

Publications (1)

Publication Number Publication Date
IN2015DN03134A true IN2015DN03134A (enrdf_load_stackoverflow) 2015-10-02

Family

ID=49517688

Family Applications (1)

Application Number Title Priority Date Filing Date
IN3134DEN2015 IN2015DN03134A (enrdf_load_stackoverflow) 2012-10-17 2013-10-16

Country Status (7)

Country Link
US (1) US20140108734A1 (enrdf_load_stackoverflow)
EP (1) EP2909714A1 (enrdf_load_stackoverflow)
JP (1) JP2015536494A (enrdf_load_stackoverflow)
KR (1) KR20150070179A (enrdf_load_stackoverflow)
CN (1) CN104756071A (enrdf_load_stackoverflow)
IN (1) IN2015DN03134A (enrdf_load_stackoverflow)
WO (1) WO2014062764A1 (enrdf_load_stackoverflow)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9158693B2 (en) 2011-10-31 2015-10-13 Intel Corporation Dynamically controlling cache size to maximize energy efficiency
DE112012007119T5 (de) * 2012-12-26 2015-07-30 Intel Corporation Threadmigration-Unterstützung für Kerne unterschiedlicher Architektur
US9367114B2 (en) 2013-03-11 2016-06-14 Intel Corporation Controlling operating voltage of a processor
US9262322B2 (en) * 2013-09-17 2016-02-16 Advanced Micro Devices, Inc. Method and apparatus for storing a processor architectural state in cache memory
US9891695B2 (en) * 2015-06-26 2018-02-13 Intel Corporation Flushing and restoring core memory content to external memory
US9946646B2 (en) * 2016-09-06 2018-04-17 Advanced Micro Devices, Inc. Systems and method for delayed cache utilization
US10387298B2 (en) * 2017-04-04 2019-08-20 Hailo Technologies Ltd Artificial neural network incorporating emphasis and focus techniques
US10373285B2 (en) * 2017-04-09 2019-08-06 Intel Corporation Coarse grain coherency
US10325341B2 (en) 2017-04-21 2019-06-18 Intel Corporation Handling pipeline submissions across many compute units
US10970080B2 (en) 2018-02-08 2021-04-06 Marvell Asia Pte, Ltd. Systems and methods for programmable hardware architecture for machine learning
US10929760B1 (en) 2018-05-22 2021-02-23 Marvell Asia Pte, Ltd. Architecture for table-based mathematical operations for inference acceleration in machine learning
US11016801B1 (en) 2018-05-22 2021-05-25 Marvell Asia Pte, Ltd. Architecture to support color scheme-based synchronization for machine learning
US10929778B1 (en) 2018-05-22 2021-02-23 Marvell Asia Pte, Ltd. Address interleaving for machine learning
US10997510B1 (en) 2018-05-22 2021-05-04 Marvell Asia Pte, Ltd. Architecture to support tanh and sigmoid operations for inference acceleration in machine learning
US10929779B1 (en) * 2018-05-22 2021-02-23 Marvell Asia Pte, Ltd. Architecture to support synchronization between core and inference engine for machine learning
US10891136B1 (en) 2018-05-22 2021-01-12 Marvell Asia Pte, Ltd. Data transmission between memory and on chip memory of inference engine for machine learning via a single data gathering instruction

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5860106A (en) * 1995-07-13 1999-01-12 Intel Corporation Method and apparatus for dynamically adjusting power/performance characteristics of a memory subsystem
US7412565B2 (en) * 2003-08-18 2008-08-12 Intel Corporation Memory optimization for a computer system having a hibernation mode
US7139909B2 (en) * 2003-10-16 2006-11-21 International Business Machines Corporation Technique for system initial program load or boot-up of electronic devices and systems
US7539819B1 (en) * 2005-10-31 2009-05-26 Sun Microsystems, Inc. Cache operations with hierarchy control
US7958312B2 (en) * 2005-11-15 2011-06-07 Oracle America, Inc. Small and power-efficient cache that can provide data for background DMA devices while the processor is in a low-power state
US7606976B2 (en) * 2006-10-27 2009-10-20 Advanced Micro Devices, Inc. Dynamically scalable cache architecture
US20100274972A1 (en) * 2008-11-24 2010-10-28 Boris Babayan Systems, methods, and apparatuses for parallel computing
US8117498B1 (en) * 2010-07-27 2012-02-14 Advanced Micro Devices, Inc. Mechanism for maintaining cache soft repairs across power state transitions
US8751745B2 (en) * 2010-08-11 2014-06-10 Advanced Micro Devices, Inc. Method for concurrent flush of L1 and L2 caches
US20130262780A1 (en) * 2012-03-30 2013-10-03 Srilatha Manne Apparatus and Method for Fast Cache Shutdown

Also Published As

Publication number Publication date
WO2014062764A1 (en) 2014-04-24
CN104756071A (zh) 2015-07-01
US20140108734A1 (en) 2014-04-17
KR20150070179A (ko) 2015-06-24
JP2015536494A (ja) 2015-12-21
EP2909714A1 (en) 2015-08-26

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