IN2015CH01503A - - Google Patents

Info

Publication number
IN2015CH01503A
IN2015CH01503A IN1503CH2015A IN2015CH01503A IN 2015CH01503 A IN2015CH01503 A IN 2015CH01503A IN 1503CH2015 A IN1503CH2015 A IN 1503CH2015A IN 2015CH01503 A IN2015CH01503 A IN 2015CH01503A
Authority
IN
India
Application number
Other languages
English (en)
Inventor
Kumar Kodavalla Vijay
Original Assignee
Wipro Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wipro Ltd filed Critical Wipro Ltd
Priority to IN1503CH2015 priority Critical patent/IN2015CH01503A/en
Publication of IN2015CH01503A publication Critical patent/IN2015CH01503A/en
Priority to US14/754,475 priority patent/US9720485B2/en
Priority to EP15196622.3A priority patent/EP3073349B1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B15/00—Suppression or limitation of noise or interference
    • H04B15/02—Reducing interference from electric apparatus by means located at or near the interfering apparatus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2215/00—Reducing interference at the transmission system level
    • H04B2215/064—Reduction of clock or synthesizer reference frequency harmonics
    • H04B2215/065—Reduction of clock or synthesizer reference frequency harmonics by changing the frequency of clock or reference frequency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
IN1503CH2015 2015-03-24 2015-03-24 IN2015CH01503A (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IN1503CH2015 IN2015CH01503A (fr) 2015-03-24 2015-03-24
US14/754,475 US9720485B2 (en) 2015-03-24 2015-06-29 System and method for dynamically adjusting host low power clock frequency without depending on peripheral low power clock frequency
EP15196622.3A EP3073349B1 (fr) 2015-03-24 2015-11-26 Système et procédé destinés à régler dynamiquement la fréquence d'horloge hôte à faible puissance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IN1503CH2015 IN2015CH01503A (fr) 2015-03-24 2015-03-24

Publications (1)

Publication Number Publication Date
IN2015CH01503A true IN2015CH01503A (fr) 2015-04-10

Family

ID=54394683

Family Applications (1)

Application Number Title Priority Date Filing Date
IN1503CH2015 IN2015CH01503A (fr) 2015-03-24 2015-03-24

Country Status (2)

Country Link
US (1) US9720485B2 (fr)
IN (1) IN2015CH01503A (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190029657A (ko) * 2016-07-22 2019-03-20 후아웨이 테크놀러지 컴퍼니 리미티드 메모리 요청 정보에 기반하여 캐시 메모리의 클럭 속도/전압을 설정하는 장치 및 방법

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105357033B (zh) * 2015-10-16 2019-04-05 华为技术有限公司 一种减小移动产业处理器接口对通信质量干扰的方法和装置
US10698522B2 (en) * 2016-04-27 2020-06-30 Qualcomm Incorporated Variable rate display interfaces
US10742390B2 (en) * 2016-07-13 2020-08-11 Novatek Microelectronics Corp. Method of improving clock recovery and related device
US11633673B2 (en) * 2018-05-17 2023-04-25 Universal City Studios Llc Modular amusement park systems and methods
US11768701B2 (en) * 2019-09-17 2023-09-26 Western Digital Technologies, Inc. Exception analysis for data storage devices
US11895588B2 (en) * 2020-08-05 2024-02-06 Analog Devices, Inc. Timing precision maintenance with reduced power during system sleep
CN114153303B (zh) * 2021-10-31 2024-06-14 山东云海国创云计算装备产业创新中心有限公司 一种功耗控制系统和功耗控制方法、装置、介质
US20230400900A1 (en) * 2022-06-14 2023-12-14 Dell Products, L.P. Managing thermal and acoustic characteristics of an information handling system (ihs) based on the use of external peripheral devices

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6292903B1 (en) * 1997-07-09 2001-09-18 International Business Machines Corporation Smart memory interface
JP5341503B2 (ja) 2008-12-26 2013-11-13 株式会社東芝 メモリデバイス、ホストデバイスおよびサンプリングクロックの調整方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190029657A (ko) * 2016-07-22 2019-03-20 후아웨이 테크놀러지 컴퍼니 리미티드 메모리 요청 정보에 기반하여 캐시 메모리의 클럭 속도/전압을 설정하는 장치 및 방법

Also Published As

Publication number Publication date
US20160282921A1 (en) 2016-09-29
US9720485B2 (en) 2017-08-01

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