IN2014DN10633A - - Google Patents

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Publication number
IN2014DN10633A
IN2014DN10633A IN10633DEN2014A IN2014DN10633A IN 2014DN10633 A IN2014DN10633 A IN 2014DN10633A IN 10633DEN2014 A IN10633DEN2014 A IN 10633DEN2014A IN 2014DN10633 A IN2014DN10633 A IN 2014DN10633A
Authority
IN
India
Prior art keywords
inverting terminal
differential
differential transmitter
biasing circuit
transmitter
Prior art date
Application number
Inventor
Daniel J Rohr
Richard Earl Jenkins
Original Assignee
Schneider Electric It Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Schneider Electric It Corp filed Critical Schneider Electric It Corp
Publication of IN2014DN10633A publication Critical patent/IN2014DN10633A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0292—Arrangements specific to the receiver end
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Dc Digital Transmission (AREA)

Abstract

A bi-directional differential bus interface that includes a differential transmitter having a non inverting terminal and an inverting terminal a differential receiver having a non inverting terminal and an inverting terminal and a biasing circuit that is electrically coupled to the non inverting terminal of the differential transmitter and the inverting terminal of the differential transmitter. The biasing circuit is configured to generate a voltage between the non inverting terminal of the differential transmitter and the inverting terminal of the differential transmitter that is approximately 200 mV or more in response to assertion of a control signal received on a control input of the biasing circuit.
IN10633DEN2014 2012-05-21 2012-05-21 IN2014DN10633A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2012/038800 WO2013176649A1 (en) 2012-05-21 2012-05-21 Systems and methods for biasing a bus

Publications (1)

Publication Number Publication Date
IN2014DN10633A true IN2014DN10633A (en) 2015-09-11

Family

ID=49624182

Family Applications (1)

Application Number Title Priority Date Filing Date
IN10633DEN2014 IN2014DN10633A (en) 2012-05-21 2012-05-21

Country Status (7)

Country Link
US (1) US9984033B2 (en)
EP (1) EP2853028B1 (en)
CN (1) CN104471859B (en)
AU (1) AU2012381055B2 (en)
DK (1) DK2853028T3 (en)
IN (1) IN2014DN10633A (en)
WO (1) WO2013176649A1 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10073806B2 (en) * 2015-05-13 2018-09-11 Qualcomm Incorporated Apparatus and methods for providing a reconfigurable bidirectional front-end interface
DE102018205217A1 (en) * 2018-04-06 2019-10-10 Robert Bosch Gmbh Circuit for a bus system and method for operating a circuit
US10536301B2 (en) 2018-06-14 2020-01-14 Semiconductor Components Industries, Llc Methods and apparatus for an interface
CN109343387B (en) * 2018-09-29 2021-03-16 珠海格力电器股份有限公司 Data communication method, device, equipment and air conditioner
CN109274615B (en) * 2018-11-09 2020-01-31 珠海格力电器股份有限公司 Bus signal reflection suppression method, device and system and control circuit
CN109560967A (en) * 2018-12-18 2019-04-02 珠海格力电器股份有限公司 Master-slave machine switching circuit and circuit control method
DE102019220022A1 (en) * 2019-12-18 2021-06-24 Robert Bosch Gesellschaft mit beschränkter Haftung Transmitting / receiving device for a bus system and method for reducing oscillations of a bus differential voltage in the event of interference
US11405068B2 (en) * 2020-08-03 2022-08-02 Apple Inc. Bi-directional single-ended transmission systems

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6188271B1 (en) 1998-07-13 2001-02-13 Minhui Wang Fail safe bias system for a tri-state bus
US6542946B1 (en) * 2000-01-28 2003-04-01 Compaq Information Technologies Group, L.P. Dual mode differential transceiver for a universal serial bus
EP1304842B1 (en) * 2001-10-19 2008-05-14 Texas Instruments Incorporated Serial differential data link with automatic power down
US6864704B1 (en) 2003-09-24 2005-03-08 Altera Corporation Adjustable differential input and output drivers
JP3778291B2 (en) 2004-05-24 2006-05-24 セイコーエプソン株式会社 Transmission circuit, data transfer control device, and electronic device
US7245154B1 (en) 2005-03-03 2007-07-17 Lattice Semiconductor Corporation Differential input receiver with programmable failsafe
US7386410B2 (en) 2005-09-27 2008-06-10 Ati Technologies Inc. Closed loop controlled reference voltage calibration circuit and method
JP2007116278A (en) 2005-10-18 2007-05-10 Nec Lcd Technologies Ltd Method for treating idle terminal and interface unit
CN2872753Y (en) 2005-12-30 2007-02-21 成都同和资讯有限责任公司 Network failure protection connecting structure
US7656226B2 (en) * 2006-03-31 2010-02-02 Intel Corporation Switched capacitor equalizer with offset voltage cancelling
JP2009544191A (en) 2006-07-10 2009-12-10 アステリオン・インコーポレイテッド Apparatus and method for generating a time reference
WO2008035582A1 (en) 2006-09-19 2008-03-27 Panasonic Corporation Signal transmitting apparatus
ATE546783T1 (en) * 2007-03-02 2012-03-15 Rambus Inc BIDIRECTIONAL INTERFACE CIRCUIT WITH A SWITCHABLE POWER SOURCE BIAS
CN201826830U (en) 2010-10-11 2011-05-11 天津市泰华科技有限公司 Logging device based on RS485 system data bus

Also Published As

Publication number Publication date
WO2013176649A1 (en) 2013-11-28
CN104471859B (en) 2018-10-19
AU2012381055A1 (en) 2015-01-15
EP2853028A1 (en) 2015-04-01
US9984033B2 (en) 2018-05-29
US20150149671A1 (en) 2015-05-28
CN104471859A (en) 2015-03-25
EP2853028B1 (en) 2019-07-10
AU2012381055B2 (en) 2017-05-25
EP2853028A4 (en) 2016-01-13
DK2853028T3 (en) 2019-10-07

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