IN2014DN03087A - - Google Patents

Info

Publication number
IN2014DN03087A
IN2014DN03087A IN3087DEN2014A IN2014DN03087A IN 2014DN03087 A IN2014DN03087 A IN 2014DN03087A IN 3087DEN2014 A IN3087DEN2014 A IN 3087DEN2014A IN 2014DN03087 A IN2014DN03087 A IN 2014DN03087A
Authority
IN
India
Prior art keywords
value
circuitry
floating point
frint
mask
Prior art date
Application number
Inventor
David Raymond Lutz
Neil Burgess
Sabrina Marie Romero
Original Assignee
Advanced Risc Mach Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Risc Mach Ltd filed Critical Advanced Risc Mach Ltd
Publication of IN2014DN03087A publication Critical patent/IN2014DN03087A/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942Significance control
    • G06F7/49947Rounding
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942Significance control
    • G06F7/49947Rounding
    • G06F7/49957Implementation of IEEE-754 Standard
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001Arithmetic instructions
    • G06F9/30014Arithmetic instructions with variable precision
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30025Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Software Systems (AREA)
  • Complex Calculations (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

Processing circuitry is provided to perform an operation FRINT for rounding a floating point value to an integral floating point value. Control circuitry controls the processing circuitry to perform the FRINT operation in response to an FRINT instruction. The processing circuitry includes shifting circuitry for generating a rounding value by shifting a base value adding circuitry for adding the rounding value to the significand of the floating point value to generate a sum value mask generating circuitry for generating a mask for clearing fractional valued bits of the sum value and masking circuitry for applying the mask to the sum value to generate the integral floating point value.
IN3087DEN2014 2011-12-07 2012-11-29 IN2014DN03087A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/313,062 US9104479B2 (en) 2011-12-07 2011-12-07 Apparatus and method for rounding a floating-point value to an integral floating-point value
PCT/GB2012/052938 WO2013083957A1 (en) 2011-12-07 2012-11-29 Apparatus and method for rounding a floating-point value to an integral floating-point value

Publications (1)

Publication Number Publication Date
IN2014DN03087A true IN2014DN03087A (en) 2015-05-15

Family

ID=47436105

Family Applications (1)

Application Number Title Priority Date Filing Date
IN3087DEN2014 IN2014DN03087A (en) 2011-12-07 2012-11-29

Country Status (9)

Country Link
US (1) US9104479B2 (en)
EP (1) EP2788862B1 (en)
JP (1) JP6006803B2 (en)
KR (1) KR101913094B1 (en)
CN (1) CN103988170B (en)
IL (1) IL232631A (en)
IN (1) IN2014DN03087A (en)
MY (1) MY168709A (en)
WO (1) WO2013083957A1 (en)

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US9916130B2 (en) * 2014-11-03 2018-03-13 Arm Limited Apparatus and method for vector processing
CN105677967B (en) * 2016-01-06 2018-11-20 浪潮集团有限公司 A method of promoting ASIC arithmetic accuracy
US10310809B2 (en) * 2016-04-08 2019-06-04 Arm Limited Apparatus and method for supporting a conversion instruction
US10606557B2 (en) * 2016-12-06 2020-03-31 Arm Limited Leading zero anticipation
US20180173527A1 (en) * 2016-12-15 2018-06-21 Optimum Semiconductor Technologies, Inc. Floating point instruction format with embedded rounding rule
CN110163355B (en) * 2018-02-13 2020-10-09 上海寒武纪信息科技有限公司 Computing device and method
US10684824B2 (en) 2018-06-06 2020-06-16 Nvidia Corporation Stochastic rounding of numerical values
US11327923B2 (en) 2019-09-04 2022-05-10 SambaNova Systems, Inc. Sigmoid function in hardware and a reconfigurable data processor including same
US11327713B2 (en) 2019-10-01 2022-05-10 SambaNova Systems, Inc. Computation units for functions based on lookup tables
US11328038B2 (en) 2019-11-25 2022-05-10 SambaNova Systems, Inc. Computational units for batch normalization
US11150872B2 (en) * 2019-12-17 2021-10-19 SambaNova Systems, Inc. Computational units for element approximation
US11836629B2 (en) 2020-01-15 2023-12-05 SambaNova Systems, Inc. Computationally efficient softmax loss gradient backpropagation
US11809908B2 (en) 2020-07-07 2023-11-07 SambaNova Systems, Inc. Runtime virtualization of reconfigurable data flow resources
US11782729B2 (en) 2020-08-18 2023-10-10 SambaNova Systems, Inc. Runtime patching of configuration files

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US5696709A (en) 1995-03-31 1997-12-09 International Business Machines Corporation Program controlled rounding modes
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US6148316A (en) 1998-05-05 2000-11-14 Mentor Graphics Corporation Floating point unit equipped also to perform integer addition as well as floating point to integer conversion
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JP2000347832A (en) * 1999-06-09 2000-12-15 Mitsubishi Electric Corp System and unit for floating-point arithmetic and semiconductor integrated circuit device equipped with same
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US6965906B1 (en) 1999-08-19 2005-11-15 National Semiconductor Corporation Converting negative floating point numbers to integer notation without two's complement hardware
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Also Published As

Publication number Publication date
US9104479B2 (en) 2015-08-11
MY168709A (en) 2018-11-29
CN103988170B (en) 2016-12-07
EP2788862B1 (en) 2015-10-07
KR20140099508A (en) 2014-08-12
WO2013083957A1 (en) 2013-06-13
JP2015506022A (en) 2015-02-26
IL232631A0 (en) 2014-06-30
CN103988170A (en) 2014-08-13
JP6006803B2 (en) 2016-10-12
US20130151576A1 (en) 2013-06-13
EP2788862A1 (en) 2014-10-15
IL232631A (en) 2017-05-29
KR101913094B1 (en) 2018-12-28

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