IN2014CN03229A - - Google Patents

Info

Publication number
IN2014CN03229A
IN2014CN03229A IN3229CHN2014A IN2014CN03229A IN 2014CN03229 A IN2014CN03229 A IN 2014CN03229A IN 3229CHN2014 A IN3229CHN2014 A IN 3229CHN2014A IN 2014CN03229 A IN2014CN03229 A IN 2014CN03229A
Authority
IN
India
Application number
Inventor
Minjiao Ye
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of IN2014CN03229A publication Critical patent/IN2014CN03229A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/426—Internal components of the client ; Characteristics thereof
    • H04N21/42653—Internal components of the client ; Characteristics thereof for processing graphics
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/12—Synchronisation between the display unit and other units, e.g. other display units, video-disc players
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/06—Use of more than one graphics processor to process data before displaying to one or more screens
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/127—Updating a frame memory using a transfer of data from a source area to a destination area
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Computer Hardware Design (AREA)
  • Computer Graphics (AREA)
  • Signal Processing (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
IN3229CHN2014 2011-12-26 2014-04-29 IN2014CN03229A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2011/084634 WO2013097071A1 (en) 2011-12-26 2011-12-26 Direct link synchronization communication between co-processors

Publications (1)

Publication Number Publication Date
IN2014CN03229A true IN2014CN03229A (en) 2015-07-03

Family

ID=48696167

Family Applications (1)

Application Number Title Priority Date Filing Date
IN3229CHN2014 IN2014CN03229A (en) 2011-12-26 2014-04-29

Country Status (6)

Country Link
US (1) US9443279B2 (en)
EP (1) EP2798804A4 (en)
CN (1) CN104012059B (en)
IN (1) IN2014CN03229A (en)
TW (1) TWI585713B (en)
WO (1) WO2013097071A1 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9443279B2 (en) 2011-12-26 2016-09-13 Intel Corporation Direct link synchronization communication between co-processors
US20130318268A1 (en) 2012-05-22 2013-11-28 Xockets IP, LLC Offloading of computation for rack level servers and corresponding methods and systems
WO2013177313A2 (en) * 2012-05-22 2013-11-28 Xockets IP, LLC Processing structured and unstructured data using offload processors
EP2946296A4 (en) * 2013-01-17 2016-11-16 Xockets Ip Llc Offload processor modules for connection to system memory
CN103902498B (en) * 2013-12-18 2016-12-07 曲阜师范大学 A kind of software definition server system towards Heterogeneous Computing and method
US11132203B2 (en) * 2014-08-14 2021-09-28 Texas Instruments Incorporated System and method for synchronizing instruction execution between a central processor and a coprocessor
GB2540382B (en) * 2015-07-15 2020-03-04 Advanced Risc Mach Ltd Data processing systems
US10296393B2 (en) * 2016-09-19 2019-05-21 Texas Instruments Incorporated Method for scheduling a processing device
KR102223032B1 (en) * 2017-03-27 2021-03-04 삼성전자주식회사 Display controller and display driving apparatus including the same
CN115955733A (en) * 2022-12-30 2023-04-11 中国科学院计算技术研究所 Communication baseband processor

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6480200B1 (en) * 2000-06-09 2002-11-12 Hewlett-Packard Company Method and apparatus for deferred texture validation on a multi-tasking computer
FI114882B (en) 2003-04-30 2005-01-14 Nokia Corp Photo Frame Update Sync
US20060082580A1 (en) * 2004-10-05 2006-04-20 Raymond Chow Method and apparatus for triggering frame updates
US7522167B1 (en) * 2004-12-16 2009-04-21 Nvidia Corporation Coherence of displayed images for split-frame rendering in multi-processor graphics system
US7586492B2 (en) * 2004-12-20 2009-09-08 Nvidia Corporation Real-time display post-processing using programmable hardware
US8112513B2 (en) * 2005-11-30 2012-02-07 Microsoft Corporation Multi-user display proxy server
US20080055322A1 (en) * 2006-08-31 2008-03-06 Ryan Thomas E Method and apparatus for optimizing data flow in a graphics co-processor
US9747105B2 (en) * 2009-12-17 2017-08-29 Intel Corporation Method and apparatus for performing a shift and exclusive or operation in a single instruction
US8279213B2 (en) * 2009-12-23 2012-10-02 Intel Corporation Synchronized media processing
US9443279B2 (en) 2011-12-26 2016-09-13 Intel Corporation Direct link synchronization communication between co-processors

Also Published As

Publication number Publication date
TW201333876A (en) 2013-08-16
CN104012059B (en) 2017-09-01
WO2013097071A1 (en) 2013-07-04
TWI585713B (en) 2017-06-01
US9443279B2 (en) 2016-09-13
EP2798804A1 (en) 2014-11-05
US20140204099A1 (en) 2014-07-24
CN104012059A (en) 2014-08-27
EP2798804A4 (en) 2015-09-23

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