IN2014CN02111A - - Google Patents
Info
- Publication number
- IN2014CN02111A IN2014CN02111A IN2111CHN2014A IN2014CN02111A IN 2014CN02111 A IN2014CN02111 A IN 2014CN02111A IN 2111CHN2014 A IN2111CHN2014 A IN 2111CHN2014A IN 2014CN02111 A IN2014CN02111 A IN 2014CN02111A
- Authority
- IN
- India
- Prior art keywords
- single instruction
- instruction multiple
- multiple data
- register file
- operands
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/602—Providing cryptographic facilities or services
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30029—Logical and Boolean instructions, e.g. XOR, NOT
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09C—CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
- G09C1/00—Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0643—Hash functions, e.g. MD5, SHA, HMAC or f9 MAC
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
- H04L9/3236—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using cryptographic hash functions
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
- H04L9/3236—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using cryptographic hash functions
- H04L9/3239—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using cryptographic hash functions involving non-keyed hash functions, e.g. modification detection codes [MDCs], MD5, SHA or RIPEMD
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
- H04L2209/125—Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Bioethics (AREA)
- General Health & Medical Sciences (AREA)
- Health & Medical Sciences (AREA)
- Computing Systems (AREA)
- Executing Machine-Instructions (AREA)
- Storage Device Security (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1119834.8A GB2497070B (en) | 2011-11-17 | 2011-11-17 | Cryptographic support instructions |
PCT/GB2012/052315 WO2013072657A1 (fr) | 2011-11-17 | 2012-09-20 | Instructions simd permettant de prendre en charge la génération de valeurs de hachage dans des algorithmes cryptographiques |
Publications (1)
Publication Number | Publication Date |
---|---|
IN2014CN02111A true IN2014CN02111A (fr) | 2015-05-29 |
Family
ID=45444264
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IN2111CHN2014 IN2014CN02111A (fr) | 2011-11-17 | 2012-09-20 |
Country Status (11)
Country | Link |
---|---|
US (3) | US8966282B2 (fr) |
EP (1) | EP2742421B1 (fr) |
JP (1) | JP6068493B2 (fr) |
KR (1) | KR101962104B1 (fr) |
CN (1) | CN103930869B (fr) |
GB (1) | GB2497070B (fr) |
IL (1) | IL231467B (fr) |
IN (1) | IN2014CN02111A (fr) |
MY (1) | MY168503A (fr) |
TW (1) | TWI522832B (fr) |
WO (1) | WO2013072657A1 (fr) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2497070B (en) | 2011-11-17 | 2015-11-25 | Advanced Risc Mach Ltd | Cryptographic support instructions |
US8874933B2 (en) * | 2012-09-28 | 2014-10-28 | Intel Corporation | Instruction set for SHA1 round processing on 128-bit data paths |
US8953785B2 (en) * | 2012-09-28 | 2015-02-10 | Intel Corporation | Instruction set for SKEIN256 SHA3 algorithm on a 128-bit processor |
US9128698B2 (en) * | 2012-09-28 | 2015-09-08 | Intel Corporation | Systems, apparatuses, and methods for performing rotate and XOR in response to a single instruction |
US8838997B2 (en) * | 2012-09-28 | 2014-09-16 | Intel Corporation | Instruction set for message scheduling of SHA256 algorithm |
GB2508343A (en) | 2012-11-28 | 2014-06-04 | Ibm | Replacing a hash function if a second hash function is more effective |
US9251377B2 (en) | 2012-12-28 | 2016-02-02 | Intel Corporation | Instructions processors, methods, and systems to process secure hash algorithms |
US8924741B2 (en) * | 2012-12-29 | 2014-12-30 | Intel Corporation | Instruction and logic to provide SIMD secure hashing round slice functionality |
US10038550B2 (en) | 2013-08-08 | 2018-07-31 | Intel Corporation | Instruction and logic to provide a secure cipher hash round functionality |
US9425953B2 (en) | 2013-10-09 | 2016-08-23 | Intel Corporation | Generating multiple secure hashes from a single data buffer |
US10503510B2 (en) | 2013-12-27 | 2019-12-10 | Intel Corporation | SM3 hash function message expansion processors, methods, systems, and instructions |
US9912481B2 (en) * | 2014-03-27 | 2018-03-06 | Intel Corporation | Method and apparatus for efficiently executing hash operations |
US9513913B2 (en) | 2014-07-22 | 2016-12-06 | Intel Corporation | SM4 acceleration processors, methods, systems, and instructions |
US9317719B2 (en) | 2014-09-04 | 2016-04-19 | Intel Corporation | SM3 hash algorithm acceleration processors, methods, systems, and instructions |
US9467279B2 (en) | 2014-09-26 | 2016-10-11 | Intel Corporation | Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality |
US9658854B2 (en) | 2014-09-26 | 2017-05-23 | Intel Corporation | Instructions and logic to provide SIMD SM3 cryptographic hashing functionality |
US10110566B2 (en) * | 2015-07-21 | 2018-10-23 | Baffle, Inc. | Systems and processes for executing private programs on untrusted computers |
KR102307105B1 (ko) * | 2015-08-19 | 2021-09-29 | 인텔 코포레이션 | Simd sm3 암호화 해싱 기능을 제공하기 위한 명령어 및 로직 |
US10348506B2 (en) | 2016-09-30 | 2019-07-09 | International Business Machines Corporation | Determination of state of padding operation |
US10326596B2 (en) * | 2016-10-01 | 2019-06-18 | Intel Corporation | Techniques for secure authentication |
US9680653B1 (en) * | 2016-10-13 | 2017-06-13 | International Business Machines Corporation | Cipher message with authentication instruction |
US10833847B2 (en) * | 2017-02-28 | 2020-11-10 | Google Llc | Cryptographic hash generated using data parallel instructions |
US10491377B2 (en) * | 2017-02-28 | 2019-11-26 | Google Llc | Hashing using data parallel instructions |
DE102021100538A1 (de) * | 2021-01-13 | 2022-07-14 | Infineon Technologies Ag | Schaltung und verfahren zur rotationsinvarianten ausführung einer oder mehrerer operationen mit mindestens einem operanden |
US20220416999A1 (en) * | 2021-06-25 | 2022-12-29 | Intel Corporation | Fused instruction to accelerate performance of secure hash algorithm 2 (sha-2) workloads in a graphics environment |
CN113794552B (zh) * | 2021-09-14 | 2023-07-07 | 山东省计算中心(国家超级计算济南中心) | 一种基于simd的sm3并行数据加密运算方法及系统 |
CN114095149B (zh) * | 2021-11-12 | 2023-05-30 | 龙芯中科技术股份有限公司 | 信息加密方法、装置、设备及存储介质 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5918062A (en) * | 1997-10-23 | 1999-06-29 | Advanced Micro Devices, Inc. | Microprocessor including an efficient implemention of an accumulate instruction |
US6377970B1 (en) * | 1998-03-31 | 2002-04-23 | Intel Corporation | Method and apparatus for computing a sum of packed data elements using SIMD multiply circuitry |
DE10061998A1 (de) | 2000-12-13 | 2002-07-18 | Infineon Technologies Ag | Kryptographieprozessor |
GB2389678A (en) * | 2002-06-14 | 2003-12-17 | Univ Sheffield | Finite field processor reconfigurable for varying sizes of field. |
US7599489B1 (en) * | 2004-02-09 | 2009-10-06 | Sun Microsystems Inc. | Accelerating cryptographic hash computations |
US20060190700A1 (en) * | 2005-02-22 | 2006-08-24 | International Business Machines Corporation | Handling permanent and transient errors using a SIMD unit |
US7933405B2 (en) * | 2005-04-08 | 2011-04-26 | Icera Inc. | Data access and permute unit |
US7536532B2 (en) * | 2006-09-27 | 2009-05-19 | International Business Machines Corporation | Merge operations of data arrays based on SIMD instructions |
TWI335528B (en) | 2007-05-15 | 2011-01-01 | Htc Corp | A device with multiple functions, and a method for switching the functions and related electronic devices thereof |
US20090106526A1 (en) | 2007-10-22 | 2009-04-23 | David Arnold Luick | Scalar Float Register Overlay on Vector Register File for Efficient Register Allocation and Scalar Float and Vector Register Sharing |
GB2456775B (en) * | 2008-01-22 | 2012-10-31 | Advanced Risc Mach Ltd | Apparatus and method for performing permutation operations on data |
US7877582B2 (en) * | 2008-01-31 | 2011-01-25 | International Business Machines Corporation | Multi-addressable register file |
US8879725B2 (en) * | 2008-02-29 | 2014-11-04 | Intel Corporation | Combining instructions including an instruction that performs a sequence of transformations to isolate one transformation |
GB2464292A (en) * | 2008-10-08 | 2010-04-14 | Advanced Risc Mach Ltd | SIMD processor circuit for performing iterative SIMD multiply-accumulate operations |
US20100115232A1 (en) * | 2008-10-31 | 2010-05-06 | Johnson Timothy J | Large integer support in vector operations |
US8595467B2 (en) * | 2009-12-29 | 2013-11-26 | International Business Machines Corporation | Floating point collect and operate |
GB2497070B (en) | 2011-11-17 | 2015-11-25 | Advanced Risc Mach Ltd | Cryptographic support instructions |
US9251377B2 (en) * | 2012-12-28 | 2016-02-02 | Intel Corporation | Instructions processors, methods, and systems to process secure hash algorithms |
US9912481B2 (en) * | 2014-03-27 | 2018-03-06 | Intel Corporation | Method and apparatus for efficiently executing hash operations |
-
2011
- 2011-11-17 GB GB1119834.8A patent/GB2497070B/en active Active
-
2012
- 2012-09-20 WO PCT/GB2012/052315 patent/WO2013072657A1/fr active Application Filing
- 2012-09-20 JP JP2014541744A patent/JP6068493B2/ja active Active
- 2012-09-20 IN IN2111CHN2014 patent/IN2014CN02111A/en unknown
- 2012-09-20 MY MYPI2014700645A patent/MY168503A/en unknown
- 2012-09-20 EP EP12772372.4A patent/EP2742421B1/fr active Active
- 2012-09-20 KR KR1020147014337A patent/KR101962104B1/ko active IP Right Grant
- 2012-09-20 CN CN201280055673.6A patent/CN103930869B/zh active Active
- 2012-09-24 TW TW101134968A patent/TWI522832B/zh active
- 2012-09-26 US US13/627,209 patent/US8966282B2/en active Active
-
2014
- 2014-03-12 IL IL231467A patent/IL231467B/en active IP Right Grant
- 2014-12-30 US US14/585,900 patent/US9104400B2/en active Active
-
2015
- 2015-07-07 US US14/792,796 patent/US9703966B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
CN103930869A (zh) | 2014-07-16 |
EP2742421A1 (fr) | 2014-06-18 |
GB201119834D0 (en) | 2011-12-28 |
MY168503A (en) | 2018-11-12 |
TWI522832B (zh) | 2016-02-21 |
EP2742421B1 (fr) | 2020-07-01 |
GB2497070A8 (en) | 2013-07-10 |
US9104400B2 (en) | 2015-08-11 |
KR101962104B1 (ko) | 2019-03-26 |
GB2497070B (en) | 2015-11-25 |
JP6068493B2 (ja) | 2017-01-25 |
JP2015501946A (ja) | 2015-01-19 |
IL231467B (en) | 2020-03-31 |
US20160026806A1 (en) | 2016-01-28 |
GB2497070A (en) | 2013-06-05 |
CN103930869B (zh) | 2017-10-10 |
TW201322041A (zh) | 2013-06-01 |
US20150121036A1 (en) | 2015-04-30 |
US9703966B2 (en) | 2017-07-11 |
IL231467A0 (en) | 2014-04-30 |
US8966282B2 (en) | 2015-02-24 |
WO2013072657A1 (fr) | 2013-05-23 |
KR20140093695A (ko) | 2014-07-28 |
US20130132737A1 (en) | 2013-05-23 |
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