IN2014CN01325A - - Google Patents

Info

Publication number
IN2014CN01325A
IN2014CN01325A IN1325CHN2014A IN2014CN01325A IN 2014CN01325 A IN2014CN01325 A IN 2014CN01325A IN 1325CHN2014 A IN1325CHN2014 A IN 1325CHN2014A IN 2014CN01325 A IN2014CN01325 A IN 2014CN01325A
Authority
IN
India
Prior art keywords
tas
shared memory
lock
data
transactional middleware
Prior art date
Application number
Inventor
Xugang Shen
Xiangdong Li
Original Assignee
Oracle Int Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oracle Int Corp filed Critical Oracle Int Corp
Publication of IN2014CN01325A publication Critical patent/IN2014CN01325A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/526—Mutual exclusion algorithms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
    • G06F12/1466—Key-lock mechanism

Abstract

A lock mechanism can be supported in a transactional middleware system to protect transaction data in a shared memory when there are concurrent transactions. The transactional middleware machine environment comprises a semaphore provided by an operating system running on a plurality of processors. The plurality of processors operates to access data in the shared memory. The transactional middleware machine environment also comprises a test and set (TAS) assembly component that is associated with one or more processes. Each said process operates to use the TAS assembly component to perform one or more TAS operations in order to obtain a lock for data in the shared memory. Additionally a process operates to be blocked on the semaphore and waits for a release of a lock on data in the shared memory after the TAS component has performed a number of TAS operations and failed to obtain the lock.
IN1325CHN2014 2011-09-29 2012-09-18 IN2014CN01325A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201161541051P 2011-09-29 2011-09-29
US13/414,593 US8782352B2 (en) 2011-09-29 2012-03-07 System and method for supporting a self-tuning locking mechanism in a transactional middleware machine environment
PCT/US2012/055942 WO2013048826A1 (en) 2011-09-29 2012-09-18 System and method for supporting a self-tuning locking mechanism in a transactional middleware machine environment

Publications (1)

Publication Number Publication Date
IN2014CN01325A true IN2014CN01325A (en) 2015-04-24

Family

ID=47993775

Family Applications (1)

Application Number Title Priority Date Filing Date
IN1325CHN2014 IN2014CN01325A (en) 2011-09-29 2012-09-18

Country Status (6)

Country Link
US (2) US8782352B2 (en)
JP (1) JP6088527B2 (en)
KR (1) KR101964392B1 (en)
CN (1) CN103842986B (en)
IN (1) IN2014CN01325A (en)
WO (1) WO2013048826A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015165073A1 (en) * 2014-04-30 2015-11-05 Oracle International Corporation System and method for supporting adaptive self-tuning locking mechanism in transactional middleware machine environment
GB2523804B (en) * 2014-03-06 2021-03-31 Advanced Risc Mach Ltd Transactional memory support
EP3304297A1 (en) * 2015-06-04 2018-04-11 Siemens Aktiengesellschaft Method and system for clustering engineering data in a multidisciplinary engineering system
US10459909B2 (en) * 2016-01-13 2019-10-29 Walmart Apollo, Llc System for providing a time-limited mutual exclusivity lock and method therefor
WO2017131624A1 (en) * 2016-01-26 2017-08-03 Hewlett Packard Enterprise Development Lp A unified lock

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5050072A (en) 1988-06-17 1991-09-17 Modular Computer Systems, Inc. Semaphore memory to reduce common bus contention to global memory with localized semaphores in a multiprocessor system
JP2853608B2 (en) * 1995-05-30 1999-02-03 日本電気株式会社 File access control method of parallel processing system
JPH10269027A (en) * 1997-03-26 1998-10-09 Toshiba Corp Disk device and buffer management control method in the same
CA2302784A1 (en) * 1997-09-17 1999-03-25 Frank C. Luyster Improved block cipher method
US6549961B1 (en) 1999-10-27 2003-04-15 Infineon Technologies North America Corporation Semaphore access in a multiprocessor system
KR20010045288A (en) * 1999-11-04 2001-06-05 이계철 Method for managing schema using shared memory in multiple data management middleware system
JP2001229678A (en) * 1999-12-07 2001-08-24 Toshiba Corp Semiconductor memory
US20010033654A1 (en) * 2000-01-13 2001-10-25 Gabor Wieser W-EC1 encryption and decryption method and system
US7430627B2 (en) 2000-12-19 2008-09-30 International Business Machines Corporation Adaptive reader-writer lock
NZ532773A (en) * 2001-11-01 2005-11-25 Verisign Inc Transactional memory manager
CA2374290A1 (en) * 2002-03-01 2003-09-01 Ibm Canada Limited-Ibm Canada Limitee Updating spin counters for spin latches
US7697690B2 (en) * 2003-07-21 2010-04-13 Hewlett-Packard Development Company, L.P. Windowed backward key rotation
US7594234B1 (en) 2004-06-04 2009-09-22 Sun Microsystems, Inc. Adaptive spin-then-block mutual exclusion in multi-threaded processing
KR100596394B1 (en) * 2004-12-13 2006-07-04 한국전자통신연구원 Method and apparatus for controlling access shared memory in a UNIX system
US7984248B2 (en) 2004-12-29 2011-07-19 Intel Corporation Transaction based shared data operations in a multiprocessor environment
US20060143511A1 (en) 2004-12-29 2006-06-29 Huemiller Louis D Jr Memory mapped spin lock controller
US8028133B2 (en) 2006-02-22 2011-09-27 Oracle America, Inc. Globally incremented variable or clock based methods and apparatus to implement parallel transactions
CN101546275B (en) * 2008-03-26 2012-08-22 中国科学院微电子研究所 Method for realizing multiprocessor system with hardware semaphore module

Also Published As

Publication number Publication date
JP2014528609A (en) 2014-10-27
US20130086333A1 (en) 2013-04-04
US20140344529A1 (en) 2014-11-20
KR20140068909A (en) 2014-06-09
JP6088527B2 (en) 2017-03-01
CN103842986A (en) 2014-06-04
WO2013048826A1 (en) 2013-04-04
KR101964392B1 (en) 2019-04-01
US8914588B2 (en) 2014-12-16
CN103842986B (en) 2017-07-04
US8782352B2 (en) 2014-07-15

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