IN2014CH00988A - - Google Patents

Info

Publication number
IN2014CH00988A
IN2014CH00988A IN988CH2014A IN2014CH00988A IN 2014CH00988 A IN2014CH00988 A IN 2014CH00988A IN 988CH2014 A IN988CH2014 A IN 988CH2014A IN 2014CH00988 A IN2014CH00988 A IN 2014CH00988A
Authority
IN
India
Prior art keywords
mixed
signal circuit
netlist
property
disclosed
Prior art date
Application number
Other languages
English (en)
Inventor
Deng Yunbin
K Gopalakrishnan Venkat
L Thompson Rick
Original Assignee
Bae Sys Inf & Elect Sys Integ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bae Sys Inf & Elect Sys Integ filed Critical Bae Sys Inf & Elect Sys Integ
Publication of IN2014CH00988A publication Critical patent/IN2014CH00988A/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31704—Design for test; Design verification
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/3167—Testing of combined analog and digital circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3323—Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
IN988CH2014 2013-03-14 2014-02-27 IN2014CH00988A (https=)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US201361852361P 2013-03-14 2013-03-14

Publications (1)

Publication Number Publication Date
IN2014CH00988A true IN2014CH00988A (https=) 2015-05-08

Family

ID=54141891

Family Applications (1)

Application Number Title Priority Date Filing Date
IN988CH2014 IN2014CH00988A (https=) 2013-03-14 2014-02-27

Country Status (2)

Country Link
US (1) US20150268300A1 (https=)
IN (1) IN2014CH00988A (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7756590B2 (ja) * 2022-03-31 2025-10-20 三菱電機エンジニアリング株式会社 機能推定方法および機能推定プログラム

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040153982A1 (en) * 2003-01-27 2004-08-05 Pengfei Zhang Signal flow driven circuit analysis and partition technique
US8418098B2 (en) * 2007-12-28 2013-04-09 Taiwan Semiconductor Manufacturing Company, Ltd. Advisory system for verifying sensitive circuits in chip-design

Also Published As

Publication number Publication date
US20150268300A1 (en) 2015-09-24

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