IN2014CH00519A - - Google Patents

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Publication number
IN2014CH00519A
IN2014CH00519A IN519CH2014A IN2014CH00519A IN 2014CH00519 A IN2014CH00519 A IN 2014CH00519A IN 519CH2014 A IN519CH2014 A IN 519CH2014A IN 2014CH00519 A IN2014CH00519 A IN 2014CH00519A
Authority
IN
India
Prior art keywords
volatile memory
controller
memory
storage device
data storage
Prior art date
Application number
Other languages
English (en)
Inventor
Edward TUERS Daniel
Manohar Abhijeet
Murin Mark
Shlick Mark
Lasser Menahem
Original Assignee
Sandisk Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sandisk Technologies Inc filed Critical Sandisk Technologies Inc
Priority to IN519CH2014 priority Critical patent/IN2014CH00519A/en
Priority to US14/264,160 priority patent/US9400747B2/en
Publication of IN2014CH00519A publication Critical patent/IN2014CH00519A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7205—Cleaning, compaction, garbage collection, erase control
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
IN519CH2014 2013-12-02 2014-02-04 IN2014CH00519A (es)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IN519CH2014 IN2014CH00519A (es) 2013-12-02 2014-02-04
US14/264,160 US9400747B2 (en) 2013-12-02 2014-04-29 Batch command techniques for a data storage device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201361910857P 2013-12-02 2013-12-02
IN519CH2014 IN2014CH00519A (es) 2013-12-02 2014-02-04

Publications (1)

Publication Number Publication Date
IN2014CH00519A true IN2014CH00519A (es) 2015-06-12

Family

ID=54393930

Family Applications (1)

Application Number Title Priority Date Filing Date
IN519CH2014 IN2014CH00519A (es) 2013-12-02 2014-02-04

Country Status (2)

Country Link
US (1) US9400747B2 (es)
IN (1) IN2014CH00519A (es)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9824004B2 (en) 2013-10-04 2017-11-21 Micron Technology, Inc. Methods and apparatuses for requesting ready status information from a memory
US10108372B2 (en) 2014-01-27 2018-10-23 Micron Technology, Inc. Methods and apparatuses for executing a plurality of queued tasks in a memory
US10257192B2 (en) * 2014-05-29 2019-04-09 Samsung Electronics Co., Ltd. Storage system and method for performing secure write protect thereof
US9858009B2 (en) * 2015-10-26 2018-01-02 Sandisk Technologies Llc Data folding in 3D nonvolatile memory
US10613772B2 (en) * 2017-03-16 2020-04-07 Qualcomm Incorporated Methods and apparatuses for copying a data page in an unmanaged flash memory device
US11294824B2 (en) * 2020-01-03 2022-04-05 Western Digital Technologies, Inc. System and method for reduced latency of read-modify-write operations
US11934675B2 (en) * 2020-09-12 2024-03-19 Western Digital Technologies, Inc. Mixed mode block cycling for intermediate data

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4414624A (en) * 1980-11-19 1983-11-08 The United States Of America As Represented By The Secretary Of The Navy Multiple-microcomputer processing
US7196931B2 (en) 2002-09-24 2007-03-27 Sandisk Corporation Non-volatile memory and method with reduced source line bias errors
ITMI20031893A1 (it) 2003-10-03 2005-04-04 St Microelectronics Srl Dispositivo integrato di memoria con comandi di lettura e scrittura multipli.
US6999366B2 (en) * 2003-12-03 2006-02-14 Hewlett-Packard Development Company, Lp. Magnetic memory including a sense result category between logic states
US20050285248A1 (en) 2004-06-29 2005-12-29 Sun-Teck See Method and system for expanding flash storage device capacity
US7401184B2 (en) * 2004-11-19 2008-07-15 Intel Corporation Matching memory transactions to cache line boundaries
US8581349B1 (en) * 2011-05-02 2013-11-12 Monolithic 3D Inc. 3D memory semiconductor device and structure
CN103794620B (zh) * 2010-12-14 2016-08-24 桑迪士克科技有限责任公司 具有三个用于行选择的器件驱动器的三维非易失性存储器
US9116781B2 (en) * 2011-10-17 2015-08-25 Rambus Inc. Memory controller and memory device command protocol
WO2013147797A1 (en) * 2012-03-29 2013-10-03 Intel Corporation Method and apparatus for treatment of state confidence data retrieved from a non-volatile memory array
US8902650B2 (en) * 2012-08-30 2014-12-02 Micron Technology, Inc. Memory devices and operating methods for a memory device

Also Published As

Publication number Publication date
US9400747B2 (en) 2016-07-26
US20150154112A1 (en) 2015-06-04

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