IN2014CH00440A - - Google Patents

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Publication number
IN2014CH00440A
IN2014CH00440A IN440CH2014A IN2014CH00440A IN 2014CH00440 A IN2014CH00440 A IN 2014CH00440A IN 440CH2014 A IN440CH2014 A IN 440CH2014A IN 2014CH00440 A IN2014CH00440 A IN 2014CH00440A
Authority
IN
India
Prior art keywords
validation system
electronic device
mechanisms
tools
signals associated
Prior art date
Application number
Other languages
English (en)
Inventor
Sehgal Rajeev
Mandavilli Srinivas
Mathews Pradish
Singh Ajit
Potts Henry
Original Assignee
Mentor Graphics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mentor Graphics Corp filed Critical Mentor Graphics Corp
Priority to IN440CH2014 priority Critical patent/IN2014CH00440A/en
Priority to US14/473,914 priority patent/US9703916B2/en
Publication of IN2014CH00440A publication Critical patent/IN2014CH00440A/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
IN440CH2014 2014-01-31 2014-01-31 IN2014CH00440A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IN440CH2014 IN2014CH00440A (ja) 2014-01-31 2014-01-31
US14/473,914 US9703916B2 (en) 2014-01-31 2014-08-29 Streaming, at-speed debug and validation architecture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IN440CH2014 IN2014CH00440A (ja) 2014-01-31 2014-01-31

Publications (1)

Publication Number Publication Date
IN2014CH00440A true IN2014CH00440A (ja) 2015-08-07

Family

ID=53755052

Family Applications (1)

Application Number Title Priority Date Filing Date
IN440CH2014 IN2014CH00440A (ja) 2014-01-31 2014-01-31

Country Status (2)

Country Link
US (1) US9703916B2 (ja)
IN (1) IN2014CH00440A (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11475191B2 (en) * 2019-05-15 2022-10-18 International Business Machines Corporation Generating and adding additional control information to logic under test to facilitate debugging and comprehension of a simulation

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6823497B2 (en) * 1999-11-30 2004-11-23 Synplicity, Inc. Method and user interface for debugging an electronic system
US7379861B2 (en) * 2004-05-28 2008-05-27 Quickturn Design Systems, Inc. Dynamic programming of trigger conditions in hardware emulation systems

Also Published As

Publication number Publication date
US9703916B2 (en) 2017-07-11
US20150220677A1 (en) 2015-08-06

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