IN2014CH00438A - - Google Patents
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- Publication number
- IN2014CH00438A IN2014CH00438A IN438CH2014A IN2014CH00438A IN 2014CH00438 A IN2014CH00438 A IN 2014CH00438A IN 438CH2014 A IN438CH2014 A IN 438CH2014A IN 2014CH00438 A IN2014CH00438 A IN 2014CH00438A
- Authority
- IN
- India
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/06—Power analysis or power optimisation
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IN438CH2014 IN2014CH00438A (ru) | 2014-01-31 | 2014-01-31 | |
| US14/608,567 US9679097B2 (en) | 2014-01-31 | 2015-01-29 | Selective power state table composition |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IN438CH2014 IN2014CH00438A (ru) | 2014-01-31 | 2014-01-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| IN2014CH00438A true IN2014CH00438A (ru) | 2015-08-07 |
Family
ID=53755053
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IN438CH2014 IN2014CH00438A (ru) | 2014-01-31 | 2014-01-31 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US9679097B2 (ru) |
| IN (1) | IN2014CH00438A (ru) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9507406B2 (en) | 2012-09-21 | 2016-11-29 | Atmel Corporation | Configuring power domains of a microcontroller system |
| US9323312B2 (en) | 2012-09-21 | 2016-04-26 | Atmel Corporation | System and methods for delaying interrupts in a microcontroller system |
| US9383807B2 (en) | 2013-10-01 | 2016-07-05 | Atmel Corporation | Configuring power domains of a microcontroller system |
| US9684367B2 (en) * | 2014-06-26 | 2017-06-20 | Atmel Corporation | Power trace port for tracing states of power domains |
| CN107431664B (zh) | 2015-01-23 | 2021-03-12 | 电子湾有限公司 | 消息传递系统和方法 |
| WO2016115735A1 (en) | 2015-01-23 | 2016-07-28 | Murthy Sharad R | Processing high volume network data |
| US10311192B2 (en) * | 2015-03-30 | 2019-06-04 | Synopsys, Inc. | System and method for power verification using efficient merging of power state tables |
| US10706192B1 (en) * | 2017-05-01 | 2020-07-07 | Synopsys, Inc. | Voltage reconciliation in multi-level power managed systems |
| US10346581B2 (en) | 2017-06-15 | 2019-07-09 | Toshiba Memory Corporation | Method for system level static power validation |
| US10915683B2 (en) | 2018-03-08 | 2021-02-09 | Synopsys, Inc. | Methodology to create constraints and leverage formal coverage analyzer to achieve faster code coverage closure for an electronic structure |
| US10769329B1 (en) | 2019-04-03 | 2020-09-08 | Synopsys, Inc. | Retention model with RTL-compatible default operating mode |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103838892B (zh) * | 2012-11-26 | 2018-06-15 | 恩智浦美国有限公司 | 多电压域电路设计验证方法 |
| US8683419B1 (en) * | 2012-11-30 | 2014-03-25 | Cadence Design Systems, Inc. | Power domain crossing interface analysis |
| EP2869224A1 (en) * | 2013-10-31 | 2015-05-06 | Synopsys, Inc. | Method and system for functional verification of a circuit description |
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2014
- 2014-01-31 IN IN438CH2014 patent/IN2014CH00438A/en unknown
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2015
- 2015-01-29 US US14/608,567 patent/US9679097B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US9679097B2 (en) | 2017-06-13 |
| US20150220678A1 (en) | 2015-08-06 |