IN2013CN00694A - - Google Patents

Info

Publication number
IN2013CN00694A
IN2013CN00694A IN694CHN2013A IN2013CN00694A IN 2013CN00694 A IN2013CN00694 A IN 2013CN00694A IN 694CHN2013 A IN694CHN2013 A IN 694CHN2013A IN 2013CN00694 A IN2013CN00694 A IN 2013CN00694A
Authority
IN
India
Prior art keywords
branch
register
transaction
indicate whether
indicator
Prior art date
Application number
Inventor
Ravi Rajwar
Laura A Knauth
Peter Lachner
Konrad K Lai
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of IN2013CN00694A publication Critical patent/IN2013CN00694A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/526—Mutual exclusion algorithms
    • G06F9/528—Mutual exclusion algorithms by using speculative mechanisms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/3476—Data logging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
    • G06F11/1407—Checkpointing the instruction stream
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3636—Software debugging by tracing the execution of the program
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3812—Instruction prefetching with instruction modification, e.g. store into instruction stream
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/466—Transaction processing
    • G06F9/467—Transactional memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Debugging And Monitoring (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

In one embodiment a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.
IN694CHN2013 2010-07-28 2011-07-28 IN2013CN00694A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/845,554 US8479053B2 (en) 2010-07-28 2010-07-28 Processor with last branch record register storing transaction indicator
PCT/US2011/045797 WO2012016085A2 (en) 2010-07-28 2011-07-28 Last branch record indicators for transactional memory

Publications (1)

Publication Number Publication Date
IN2013CN00694A true IN2013CN00694A (en) 2015-07-03

Family

ID=45527938

Family Applications (1)

Application Number Title Priority Date Filing Date
IN694CHN2013 IN2013CN00694A (en) 2010-07-28 2011-07-28

Country Status (8)

Country Link
US (4) US8479053B2 (en)
KR (1) KR101423480B1 (en)
CN (1) CN103154908B (en)
DE (1) DE112011105042B4 (en)
GB (1) GB2504858B (en)
IN (1) IN2013CN00694A (en)
TW (1) TWI468937B (en)
WO (1) WO2012016085A2 (en)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8607241B2 (en) 2004-06-30 2013-12-10 Intel Corporation Compare and exchange operation using sleep-wakeup mechanism
US20130013899A1 (en) * 2011-07-06 2013-01-10 International Business Machines Corporation Using Hardware Transaction Primitives for Implementing Non-Transactional Escape Actions Inside Transactions
US20130205284A1 (en) * 2012-02-02 2013-08-08 Dhruva Chakrabarti Ownership acquire policy selection
US8682877B2 (en) 2012-06-15 2014-03-25 International Business Machines Corporation Constrained transaction execution
US9442737B2 (en) 2012-06-15 2016-09-13 International Business Machines Corporation Restricting processing within a processor to facilitate transaction completion
US9384004B2 (en) 2012-06-15 2016-07-05 International Business Machines Corporation Randomized testing within transactional execution
US9361115B2 (en) 2012-06-15 2016-06-07 International Business Machines Corporation Saving/restoring selected registers in transactional processing
US8688661B2 (en) 2012-06-15 2014-04-01 International Business Machines Corporation Transactional processing
US8966324B2 (en) * 2012-06-15 2015-02-24 International Business Machines Corporation Transactional execution branch indications
US9367323B2 (en) 2012-06-15 2016-06-14 International Business Machines Corporation Processor assist facility
US8880959B2 (en) * 2012-06-15 2014-11-04 International Business Machines Corporation Transaction diagnostic block
US9448796B2 (en) 2012-06-15 2016-09-20 International Business Machines Corporation Restricted instructions in transactional execution
US9436477B2 (en) 2012-06-15 2016-09-06 International Business Machines Corporation Transaction abort instruction
US9348642B2 (en) 2012-06-15 2016-05-24 International Business Machines Corporation Transaction begin/end instructions
US9772854B2 (en) 2012-06-15 2017-09-26 International Business Machines Corporation Selectively controlling instruction execution in transactional processing
US20130339680A1 (en) 2012-06-15 2013-12-19 International Business Machines Corporation Nontransactional store instruction
US9740549B2 (en) 2012-06-15 2017-08-22 International Business Machines Corporation Facilitating transaction completion subsequent to repeated aborts of the transaction
US10437602B2 (en) 2012-06-15 2019-10-08 International Business Machines Corporation Program interruption filtering in transactional execution
US9317460B2 (en) 2012-06-15 2016-04-19 International Business Machines Corporation Program event recording within a transactional environment
US9336046B2 (en) 2012-06-15 2016-05-10 International Business Machines Corporation Transaction abort processing
US9268598B2 (en) 2012-09-13 2016-02-23 International Business Machines Corporation Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories
US9411739B2 (en) * 2012-11-30 2016-08-09 Intel Corporation System, method and apparatus for improving transactional memory (TM) throughput using TM region indicators
US9182986B2 (en) 2012-12-29 2015-11-10 Intel Corporation Copy-on-write buffer for restoring program code from a speculative region to a non-speculative region
US9519586B2 (en) 2013-01-21 2016-12-13 Qualcomm Incorporated Methods and apparatus to reduce cache pollution caused by data prefetching
US9535744B2 (en) 2013-06-29 2017-01-03 Intel Corporation Method and apparatus for continued retirement during commit of a speculative region of code
US9244724B2 (en) * 2013-08-15 2016-01-26 Globalfoundries Inc. Management of transactional memory access requests by a cache memory
EP3039608B1 (en) * 2013-08-28 2018-07-04 McAfee, LLC Hardware and software execution profiling
US9442775B2 (en) * 2014-02-27 2016-09-13 International Business Machines Corporation Salvaging hardware transactions with instructions to transfer transaction execution control
US9442853B2 (en) 2014-02-27 2016-09-13 International Business Machines Corporation Salvaging lock elision transactions with instructions to change execution type
US9305167B2 (en) 2014-05-21 2016-04-05 Bitdefender IPR Management Ltd. Hardware-enabled prevention of code reuse attacks
US10049211B1 (en) 2014-07-16 2018-08-14 Bitdefender IPR Management Ltd. Hardware-accelerated prevention of code reuse attacks
GB2533416A (en) * 2014-12-19 2016-06-22 Advanced Risc Mach Ltd Monitoring utilization of transactional processing resource
US10007549B2 (en) * 2014-12-23 2018-06-26 Intel Corporation Apparatus and method for a profiler for hardware transactional memory programs
GB2533650B (en) * 2014-12-23 2021-07-21 Advanced Risc Mach Ltd Debugging data processing transactions
US11048516B2 (en) * 2015-06-27 2021-06-29 Intel Corporation Systems, methods, and apparatuses for last branch record support compatible with binary translation and speculative execution using an architectural bit array and a write bit array
US20210026950A1 (en) * 2016-03-07 2021-01-28 Crowdstrike, Inc. Hypervisor-based redirection of system calls and interrupt-based task offloading
GB2548845B (en) 2016-03-29 2019-11-27 Imagination Tech Ltd Handling memory requests
US10600141B2 (en) * 2016-09-23 2020-03-24 Nvidia Corporation Monitoring execution in a graphics processing unit
US10140056B2 (en) * 2016-09-27 2018-11-27 Intel Corporation Systems and methods for differentiating function performance by input parameters
US20180211046A1 (en) * 2017-01-26 2018-07-26 Intel Corporation Analysis and control of code flow and data flow
CN107506638B (en) * 2017-08-09 2020-10-16 南京大学 Kernel control flow abnormity detection method based on hardware mechanism
US10445211B2 (en) * 2017-08-28 2019-10-15 Microsoft Technology Licensing, Llc Logging trace data for program code execution at an instruction level
CN108681500B (en) * 2018-04-28 2021-09-07 格兰菲智能科技有限公司 System with transaction recording capability and transaction recording method
US11354440B1 (en) * 2019-06-21 2022-06-07 NortonLifeLock Inc. Analyzing and mitigating privacy issues on a computing device using cookie generation flows
US11275712B2 (en) * 2019-08-20 2022-03-15 Northrop Grumman Systems Corporation SIMD controller and SIMD predication scheme

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6658557B1 (en) 2000-05-25 2003-12-02 Advanced Micro Devices, Inc. Synthesizing the instruction stream executed by a microprocessor from its branch trace data
JP4362096B2 (en) * 2004-09-30 2009-11-11 富士通株式会社 Information processing apparatus, replacement method, replacement program, and computer-readable recording medium recording the replacement program
US8813052B2 (en) * 2005-12-07 2014-08-19 Microsoft Corporation Cache metadata for implementing bounded transactional memory
US8180967B2 (en) * 2006-03-30 2012-05-15 Intel Corporation Transactional memory virtualization
US8180977B2 (en) 2006-03-30 2012-05-15 Intel Corporation Transactional memory in out-of-order processors
US7930695B2 (en) 2006-04-06 2011-04-19 Oracle America, Inc. Method and apparatus for synchronizing threads on a processor that supports transactional memory
US20080005504A1 (en) 2006-06-30 2008-01-03 Jesse Barnes Global overflow method for virtualized transactional memory
US9798590B2 (en) 2006-09-07 2017-10-24 Intel Corporation Post-retire scheme for tracking tentative accesses during transactional execution
US8296749B2 (en) * 2007-12-28 2012-10-23 Intel Corporation Program translation and transactional memory formation
US8078850B2 (en) 2008-04-24 2011-12-13 International Business Machines Corporation Branch prediction technique using instruction for resetting result table pointer

Also Published As

Publication number Publication date
CN103154908A (en) 2013-06-12
US20160232041A1 (en) 2016-08-11
GB201314780D0 (en) 2013-10-02
KR101423480B1 (en) 2014-07-25
GB2504858B (en) 2018-06-20
US20130179668A1 (en) 2013-07-11
US8782382B2 (en) 2014-07-15
DE112011105042T5 (en) 2014-01-02
GB2504858A (en) 2014-02-12
WO2012016085A3 (en) 2012-05-31
US8479053B2 (en) 2013-07-02
US9354878B2 (en) 2016-05-31
WO2012016085A2 (en) 2012-02-02
US10073719B2 (en) 2018-09-11
KR20130041295A (en) 2013-04-24
US20140258695A1 (en) 2014-09-11
TWI468937B (en) 2015-01-11
TW201224749A (en) 2012-06-16
CN103154908B (en) 2015-11-25
US20120030518A1 (en) 2012-02-02
DE112011105042B4 (en) 2020-12-03

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