IN2013CH04449A - - Google Patents

Info

Publication number
IN2013CH04449A
IN2013CH04449A IN4449CH2013A IN2013CH04449A IN 2013CH04449 A IN2013CH04449 A IN 2013CH04449A IN 4449CH2013 A IN4449CH2013 A IN 4449CH2013A IN 2013CH04449 A IN2013CH04449 A IN 2013CH04449A
Authority
IN
India
Prior art keywords
data block
core
stored
ready state
stored data
Prior art date
Application number
Other languages
English (en)
Inventor
Vajapeyam Sriram
Original Assignee
Empire Technology Dev Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Empire Technology Dev Llc filed Critical Empire Technology Dev Llc
Priority to IN4449CH2013 priority Critical patent/IN2013CH04449A/en
Priority to US14/383,895 priority patent/US9864709B2/en
Publication of IN2013CH04449A publication Critical patent/IN2013CH04449A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements
    • G06F2212/622—State-only directory, i.e. not recording identity of sharing or owning nodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
IN4449CH2013 2013-09-30 2013-09-30 IN2013CH04449A (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IN4449CH2013 IN2013CH04449A (de) 2013-09-30 2013-09-30
US14/383,895 US9864709B2 (en) 2013-09-30 2013-11-21 Data transfer in a multi-core processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IN4449CH2013 IN2013CH04449A (de) 2013-09-30 2013-09-30

Publications (1)

Publication Number Publication Date
IN2013CH04449A true IN2013CH04449A (de) 2015-04-03

Family

ID=54209872

Family Applications (1)

Application Number Title Priority Date Filing Date
IN4449CH2013 IN2013CH04449A (de) 2013-09-30 2013-09-30

Country Status (2)

Country Link
US (1) US9864709B2 (de)
IN (1) IN2013CH04449A (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115114192A (zh) * 2021-03-23 2022-09-27 北京灵汐科技有限公司 存储器接口、功能核、众核系统和存储数据访问方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2533414B (en) * 2014-12-19 2021-12-01 Advanced Risc Mach Ltd Apparatus with shared transactional processing resource, and data processing method
JP5949977B1 (ja) * 2015-02-19 2016-07-13 日本電気株式会社 情報処理装置、情報処理方法、メインプロセッサコア、プログラム、情報処理方法、サブプロセッサコア
CN108986015B (zh) * 2015-11-17 2022-12-06 格兰菲智能科技有限公司 数据单元的关联性检查方法以及使用该方法的装置
CN105427368B (zh) * 2015-11-17 2018-03-20 上海兆芯集成电路有限公司 数据单元的关联性检查方法以及使用该方法的装置
CN105243685B (zh) * 2015-11-17 2018-01-02 上海兆芯集成电路有限公司 数据单元的关联性检查方法以及使用该方法的装置
CN110413210B (zh) * 2018-04-28 2023-05-30 伊姆西Ip控股有限责任公司 用于处理数据的方法、设备和计算机程序产品
US11269799B2 (en) * 2019-05-03 2022-03-08 Arm Limited Cluster of processing elements having split mode and lock mode
CN112732628A (zh) * 2019-10-29 2021-04-30 Oppo广东移动通信有限公司 核间数据处理方法、系统、片上系统以及电子设备
US11579799B2 (en) * 2020-03-18 2023-02-14 Micron Technology, Inc. Dynamic selection of cores for processing responses
CN116594758B (zh) * 2023-07-18 2023-09-26 山东三未信安信息科技有限公司 一种密码模块调用优化系统及优化方法

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5493668A (en) * 1990-12-14 1996-02-20 International Business Machines Corporation Multiple processor system having software for selecting shared cache entries of an associated castout class for transfer to a DASD with one I/O operation
US5933855A (en) 1997-03-21 1999-08-03 Rubinstein; Richard Shared, reconfigurable memory architectures for digital signal processing
US6128677A (en) * 1997-10-15 2000-10-03 Intel Corporation System and method for improved transfer of data between multiple processors and I/O bridges
US6487652B1 (en) * 1998-12-08 2002-11-26 Sun Microsystems, Inc. Method and apparatus for speculatively locking objects in an object-based system
US6349350B1 (en) * 1999-05-04 2002-02-19 International Business Machines Corporation System, method, and program for handling failed connections in an input/output (I/O) system
US7062582B1 (en) * 2003-03-14 2006-06-13 Marvell International Ltd. Method and apparatus for bus arbitration dynamic priority based on waiting period
JP4692826B2 (ja) * 2003-07-28 2011-06-01 ソニー株式会社 情報処理装置および方法、記録媒体、並びにプログラム
US7174437B2 (en) * 2003-10-16 2007-02-06 Silicon Graphics, Inc. Memory access management in a shared memory multi-processor system
US7206966B2 (en) * 2003-10-22 2007-04-17 Hewlett-Packard Development Company, L.P. Fault-tolerant multi-core microprocessing
US7774783B2 (en) * 2004-12-23 2010-08-10 Microsoft Corporation Method and apparatus for detecting deadlocks
US20070271450A1 (en) 2006-05-17 2007-11-22 Doshi Kshitij A Method and system for enhanced thread synchronization and coordination
US8131941B2 (en) * 2007-09-21 2012-03-06 Mips Technologies, Inc. Support for multiple coherence domains
US8200917B2 (en) * 2007-09-26 2012-06-12 Qualcomm Incorporated Multi-media processor cache with cache line locking and unlocking
US7930574B2 (en) 2007-12-31 2011-04-19 Intel Corporation Thread migration to improve power efficiency in a parallel processing environment
US8214603B2 (en) * 2008-02-01 2012-07-03 International Business Machines Corporation Method and apparatus for handling multiple memory requests within a multiprocessor system
JP2010044578A (ja) * 2008-08-12 2010-02-25 Toshiba Corp マルチコアプロセッサ
DE102009004810A1 (de) 2009-01-13 2010-07-15 Universität Augsburg Verfahren zum Ausführen eines oder mehrerer Programme auf einem Mehrkernprozessor und Mehrkernprozessor
US8180963B2 (en) 2009-05-21 2012-05-15 Empire Technology Development Llc Hierarchical read-combining local memories
US8291430B2 (en) 2009-07-10 2012-10-16 International Business Machines Corporation Optimizing system performance using spare cores in a virtualized environment
US8312470B2 (en) * 2009-12-22 2012-11-13 International Business Machines Corporation Recursive locking of a thread-shared resource
US8452835B2 (en) * 2009-12-23 2013-05-28 Citrix Systems, Inc. Systems and methods for object rate limiting in multi-core system
US8473683B2 (en) 2010-01-08 2013-06-25 International Business Machines Corporation Ordering of guarded and unguarded stores for no-sync I/O
JP5121896B2 (ja) 2010-08-11 2013-01-16 株式会社東芝 マルチコアプロセッサシステムおよびマルチコアプロセッサ
CN103080921B (zh) 2010-08-30 2015-11-25 富士通株式会社 多核处理器系统、同步控制系统、同步控制装置、信息生成方法
US8677331B2 (en) * 2011-09-30 2014-03-18 Oracle International Corporation Lock-clustering compilation for software transactional memory
US8966494B2 (en) * 2012-03-16 2015-02-24 Arm Limited Apparatus and method for processing threads requiring resources
JP6139010B2 (ja) * 2013-03-15 2017-05-31 インテル・コーポレーション デバイス
US9542238B2 (en) * 2013-05-23 2017-01-10 Nxp Usa, Inc. Systems and methods for direct memory access coherency among multiple processing cores

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115114192A (zh) * 2021-03-23 2022-09-27 北京灵汐科技有限公司 存储器接口、功能核、众核系统和存储数据访问方法

Also Published As

Publication number Publication date
US20150286597A1 (en) 2015-10-08
US9864709B2 (en) 2018-01-09

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