IN2013CH01005A - - Google Patents

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Publication number
IN2013CH01005A
IN2013CH01005A IN1005CH2013A IN2013CH01005A IN 2013CH01005 A IN2013CH01005 A IN 2013CH01005A IN 1005CH2013 A IN1005CH2013 A IN 1005CH2013A IN 2013CH01005 A IN2013CH01005 A IN 2013CH01005A
Authority
IN
India
Prior art keywords
connection
address frame
open address
established
established connection
Prior art date
Application number
Other languages
English (en)
Inventor
T More Shankar
Pinglikar Vidyadhar
Original Assignee
Lsi Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lsi Corp filed Critical Lsi Corp
Priority to IN1005CH2013 priority Critical patent/IN2013CH01005A/en
Priority to US13/970,991 priority patent/US9436412B2/en
Publication of IN2013CH01005A publication Critical patent/IN2013CH01005A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0689—Disk arrays, e.g. RAID, JBOD
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Communication Control (AREA)
IN1005CH2013 2013-03-08 2013-03-08 IN2013CH01005A (https=)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IN1005CH2013 IN2013CH01005A (https=) 2013-03-08 2013-03-08
US13/970,991 US9436412B2 (en) 2013-03-08 2013-08-20 Preemptive connection switching for serial attached small computer system interface systems

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IN1005CH2013 IN2013CH01005A (https=) 2013-03-08 2013-03-08

Publications (1)

Publication Number Publication Date
IN2013CH01005A true IN2013CH01005A (https=) 2015-08-14

Family

ID=51489323

Family Applications (1)

Application Number Title Priority Date Filing Date
IN1005CH2013 IN2013CH01005A (https=) 2013-03-08 2013-03-08

Country Status (2)

Country Link
US (1) US9436412B2 (https=)
IN (1) IN2013CH01005A (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9026702B2 (en) * 2012-11-12 2015-05-05 Avago Technologies General Ip (Singapore) Pte Ltd Methods and apparatus for fast context switching of serial advanced technology attachment in enhanced serial attached SCSI expanders
US9043529B2 (en) * 2012-11-21 2015-05-26 Avago Technologies General Ip (Singapore) Pte Ltd Method to facilitate fast context switching for partial and extended path extension to remote expanders
US9026704B2 (en) * 2013-02-25 2015-05-05 Lsi Corporation Priority based connection arbitration in a SAS topology to facilitate quality of service (QoS) in SAS transport
US10671549B2 (en) * 2015-03-25 2020-06-02 Toshiba Memory Corporation Memory system
KR102728195B1 (ko) 2018-11-09 2024-11-08 삼성전자주식회사 호스트와 통신을 수행하는 전자 장치 및 그 동작 방법
US11816052B2 (en) * 2019-10-22 2023-11-14 Intel Corporation System, apparatus and method for communicating telemetry information via virtual bus encodings

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7584319B1 (en) 2005-03-31 2009-09-01 Pmc-Sierra, Inc. Connection management in serial attached SCSI (SAS) expanders
US7958295B1 (en) 2005-03-31 2011-06-07 Pmc-Sierra Us, Inc. Method and apparatus for finding subset maxima and minima in SAS expanders and related devices
JP4775846B2 (ja) * 2006-03-20 2011-09-21 株式会社日立製作所 物理リンクの割当てを制御するコンピュータシステム及び方法
US20080040564A1 (en) 2006-08-10 2008-02-14 International Business Machines Corporation Sychronized Light Path Scheme Across Mutiple SAS Storage Enclosures
US7624223B2 (en) 2006-12-29 2009-11-24 Lsi Corporation Apparatus and methods for multiple unidirectional virtual connections among SAS devices
US20140143464A1 (en) * 2011-09-21 2014-05-22 Hewlett-Packard Development Company, L.P. Sas expander
JP5842639B2 (ja) * 2012-01-31 2016-01-13 富士通株式会社 接続装置、ストレージ装置、接続要求送信制御方法、および接続要求送信制御プログラム
US8843671B1 (en) * 2012-02-27 2014-09-23 PMC-Sierra US Inc. Dynamic resource allocation for serial attached SCSI devices
US9176917B2 (en) * 2013-02-28 2015-11-03 Hewlett-Packard Development Company, L.P. SAS latency based routing

Also Published As

Publication number Publication date
US9436412B2 (en) 2016-09-06
US20140258572A1 (en) 2014-09-11

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