IN2012DE00124A - - Google Patents

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Publication number
IN2012DE00124A
IN2012DE00124A IN124DE2012A IN2012DE00124A IN 2012DE00124 A IN2012DE00124 A IN 2012DE00124A IN 124DE2012 A IN124DE2012 A IN 124DE2012A IN 2012DE00124 A IN2012DE00124 A IN 2012DE00124A
Authority
IN
India
Prior art keywords
integrated circuit
data bus
voltage regulators
embed
timing signal
Prior art date
Application number
Other languages
English (en)
Inventor
Jayesh Iyer
Edward R Stanford
Waseem Kraipak
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to EP12864702.1A priority Critical patent/EP2802994B1/en
Priority to PCT/US2012/071993 priority patent/WO2013106206A1/en
Priority to IN124DE2012 priority patent/IN2012DE00124A/en
Priority to US14/126,135 priority patent/US9858226B2/en
Publication of IN2012DE00124A publication Critical patent/IN2012DE00124A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0052—Assignment of addresses or identifiers to the modules of a bus system
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Power Sources (AREA)
  • Information Transfer Systems (AREA)
  • Semiconductor Integrated Circuits (AREA)
IN124DE2012 2012-01-13 2012-12-28 IN2012DE00124A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP12864702.1A EP2802994B1 (en) 2012-01-13 2012-12-28 Two wire serial voltage identification protocol
PCT/US2012/071993 WO2013106206A1 (en) 2012-01-13 2012-12-28 Two wire serial voltage identification protocol
IN124DE2012 IN2012DE00124A (ja) 2012-01-13 2012-12-28
US14/126,135 US9858226B2 (en) 2012-01-13 2012-12-28 Two wire serial voltage identification protocol

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IN124DE2012 IN2012DE00124A (ja) 2012-01-13 2012-12-28

Publications (1)

Publication Number Publication Date
IN2012DE00124A true IN2012DE00124A (ja) 2015-05-22

Family

ID=48781811

Family Applications (1)

Application Number Title Priority Date Filing Date
IN124DE2012 IN2012DE00124A (ja) 2012-01-13 2012-12-28

Country Status (4)

Country Link
US (1) US9858226B2 (ja)
EP (1) EP2802994B1 (ja)
IN (1) IN2012DE00124A (ja)
WO (1) WO2013106206A1 (ja)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013106206A1 (en) 2012-01-13 2013-07-18 Intel Corporation Two wire serial voltage identification protocol
US10168758B2 (en) 2016-09-29 2019-01-01 Intel Corporation Techniques to enable communication between a processor and voltage regulator
US11669145B2 (en) * 2021-09-15 2023-06-06 Apple Inc. Power management unit

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6067585A (en) 1997-06-23 2000-05-23 Compaq Computer Corporation Adaptive interface controller that can operate with segments of different protocol and transmission rates in a single integrated device
US6532506B1 (en) 1998-08-12 2003-03-11 Intel Corporation Communicating with devices over a bus and negotiating the transfer rate over the same
US6539443B1 (en) 1998-08-12 2003-03-25 Intel Corporation Bus communication and transfer rate negotiation system
US6735633B1 (en) 1999-06-01 2004-05-11 Fast Forward Networks System for bandwidth allocation in a computer network
WO2000073870A1 (de) * 1999-06-02 2000-12-07 Micronas Munich Gmbh Schaltungsanordnung mit integriertem schaltkreis und spannungsregelkreis
US7049798B2 (en) 2002-11-13 2006-05-23 Power-One, Inc. System and method for communicating with a voltage regulator
US7345495B2 (en) * 2004-06-30 2008-03-18 Intel Corporation Temperature and voltage controlled integrated circuit processes
US7779167B2 (en) 2006-09-28 2010-08-17 Delphi Technologies, Inc. Universal integration system for auxiliary digital audio playback
US8330436B2 (en) * 2008-06-30 2012-12-11 Intel Corporation Series and parallel hybrid switched capacitor networks for IC power delivery
US8412976B2 (en) 2009-12-23 2013-04-02 Intel Corporation Data negotiation using serial voltage identification communication
US8417986B2 (en) 2009-12-23 2013-04-09 Intel Corporation Time negotiation using serial voltage identification communication
US8400091B2 (en) 2010-03-19 2013-03-19 Renesas Electronics America Inc. Voltage regulator and cooling control integrated circuit
WO2013106206A1 (en) 2012-01-13 2013-07-18 Intel Corporation Two wire serial voltage identification protocol

Also Published As

Publication number Publication date
EP2802994A4 (en) 2015-11-11
EP2802994A1 (en) 2014-11-19
EP2802994B1 (en) 2018-10-10
US20140317330A1 (en) 2014-10-23
WO2013106206A1 (en) 2013-07-18
US9858226B2 (en) 2018-01-02

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