IL94115A - Dynamic process for creating pseudo-random test templates for pompous hardware design violence - Google Patents

Dynamic process for creating pseudo-random test templates for pompous hardware design violence

Info

Publication number
IL94115A
IL94115A IL9411590A IL9411590A IL94115A IL 94115 A IL94115 A IL 94115A IL 9411590 A IL9411590 A IL 9411590A IL 9411590 A IL9411590 A IL 9411590A IL 94115 A IL94115 A IL 94115A
Authority
IL
Israel
Prior art keywords
test pattern
accordance
execution
design
test
Prior art date
Application number
IL9411590A
Other languages
English (en)
Hebrew (he)
Other versions
IL94115A0 (en
Inventor
Aharon Aharon
Ayal Bar-David
Raanan Gewirtzman
Emanuel Gofman
Moshe Leibowitz
Victor Shwarzburd
Original Assignee
Ibm Israel
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm Israel filed Critical Ibm Israel
Priority to IL9411590A priority Critical patent/IL94115A/en
Priority to US07/612,349 priority patent/US5202889A/en
Publication of IL94115A0 publication Critical patent/IL94115A0/xx
Priority to JP3052385A priority patent/JPH0778751B2/ja
Priority to EP91810187A priority patent/EP0453394B1/de
Priority to DE69119972T priority patent/DE69119972D1/de
Publication of IL94115A publication Critical patent/IL94115A/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31704—Design for test; Design verification
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318307—Generation of test inputs, e.g. test vectors, patterns or sequences computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318385—Random or pseudo-random test pattern

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Debugging And Monitoring (AREA)
IL9411590A 1990-04-18 1990-04-18 Dynamic process for creating pseudo-random test templates for pompous hardware design violence IL94115A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IL9411590A IL94115A (en) 1990-04-18 1990-04-18 Dynamic process for creating pseudo-random test templates for pompous hardware design violence
US07/612,349 US5202889A (en) 1990-04-18 1990-11-13 Dynamic process for the generation of biased pseudo-random test patterns for the functional verification of hardware designs
JP3052385A JPH0778751B2 (ja) 1990-04-18 1991-03-18 バイアスされた疑似ランダム・テスト・パターンを動的に生成する方法
EP91810187A EP0453394B1 (de) 1990-04-18 1991-03-21 Dynamisches Verfahren zur Generierung von Pseudozufallstestmustern zur Funktionsprüfung von Hardwaredesigns
DE69119972T DE69119972D1 (de) 1990-04-18 1991-03-21 Dynamisches Verfahren zur Generierung von Pseudozufallstestmustern zur Funktionsprüfung von Hardwaredesigns

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IL9411590A IL94115A (en) 1990-04-18 1990-04-18 Dynamic process for creating pseudo-random test templates for pompous hardware design violence

Publications (2)

Publication Number Publication Date
IL94115A0 IL94115A0 (en) 1991-01-31
IL94115A true IL94115A (en) 1996-06-18

Family

ID=11061110

Family Applications (1)

Application Number Title Priority Date Filing Date
IL9411590A IL94115A (en) 1990-04-18 1990-04-18 Dynamic process for creating pseudo-random test templates for pompous hardware design violence

Country Status (5)

Country Link
US (1) US5202889A (de)
EP (1) EP0453394B1 (de)
JP (1) JPH0778751B2 (de)
DE (1) DE69119972D1 (de)
IL (1) IL94115A (de)

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Also Published As

Publication number Publication date
JPH0778751B2 (ja) 1995-08-23
EP0453394A2 (de) 1991-10-23
IL94115A0 (en) 1991-01-31
DE69119972D1 (de) 1996-07-11
JPH04251339A (ja) 1992-09-07
US5202889A (en) 1993-04-13
EP0453394A3 (en) 1993-01-20
EP0453394B1 (de) 1996-06-05

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