IL45879A - Method and arrangement for multiplexing slow data channels within standard speed pcm-tdm systems - Google Patents

Description

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This invention relates to a method of and an arrangement for establishing and releasing data channels within a switching unit of a communication switching system.

In the presence of an integrated PCM telecommunication network, it is desired to be able to transmit via the same network both speech and data, especially data having a smaller bit rate than that of the PCM system. Normalized PCM systems have PCM highways with 30 + 2 channels, i.e. 30 speech channels and 2 channels for signalling and synchronising purposes, wherein with a sampling frequency of 8 kHz and with code v/ords of 8 bits a transmission capability of 64 kBit/s per channel results.

It is obviously possible to transmit via such a speech channel a slow data channel of e.g. 3.2 kBit/s by increasing the bit rate of the slow data channel to the bit rate of 64 kBit/s of the system by a suitable addition of redundancy. However, the seizure of a speech channel having a possible information flow of 64 kBit/s by a slow data channel of e.g. 3,2 kBit/s results in a very bad utilisation of the transmission capability. This drawback may not be important for a connection between a switching network and an associated periphal over a short line, but for long distance connections such a bad utilisation of the transmission capability is unacceptable.

It is therefore an object of this invention to provide a method and an arrangement enabling the establishing and releasing of a multiplex of several data channels in a switching unit with a small additional expense and without special programme in the central control. - - i According to the invention there is provided a method^ of establishing and within a switching unit of a PCM-TDM telecommunication switching system, in which the bit clock frequency of the PCM system is a multiple of the data bit frequency, in which system peripheral units are interconnected via PCM highways each having a first number of time channels to a switching network with several switching units each being able to set up a connection to highways of a second number of PCM highv/ays, in which each of the, data channels between the peripherals and the switching unit is used for forming and releasing the multiplex occupies a time channel of a highway and is switched v/ithin the switching network to said switching unit, in which to form the multiplex the contents of n highway channels occupied with data are offered in the switching unit in a first switching operation to a distinct channel of a highway called a virtual highway, in which a logic circuit performs a selection among the offered data information, and the selected data information is stored in a store row allocated to said channel of the virtual highway, in which in a second switching operation the contents of the store row are switched to a distinct channel of a further PCM highway used as the data multiplex channel for a certain destination, in which to release the multiplex the contents of the incoming data multiplex channel are switched in a first switching operation to the virtual highway, said logic circuit distributing the incoming information onto n storage rows such that each row receives only the information for an individual PCM highway channel going to one of the peripherals and being occupied with data, and in which in a second switching operation the storage contents of each row are switched in each frame to the PCM highway channel used as a data channel.

An embodiment of the invention will now be described in conjunction with the accompanying drawings in which: Fig. 1 shows the general principle of a data multiplex using a virtual highway; Fig. 2 is a schematic diagram of the interface between a low-speed data channel and a PCM channel for establishing a multiplex connection by the time slot interleaving method; Fig. 3 is a schematic diagram of a switching unit with a virtual highway v/ith indications for establishing a multiplex connection by the time slot interleaving method; Fig. 4 shows the relation between the writing time and the store rows of the speech store of the virtual highway according to fig. 3; Fig. 5 tabulates the establishment of a multiplex connection; Fig. 6 tabulates the releasing of a multiplex connectio Fig. 7 is a schematic diagram of a switching unit with a virtual highway v/ith indications for establishing the multiplex connection by the bit interleaving method.

First some general considerations shall be taken into account. It is assumed that between two places A and B which are a considerable distance apart, a rather regular demand exists for slow bit rate data channels. As mentioned it is possible but inefficient to make available a PCM speech channel to each such data channel, the speech channel having a bit rate which is a multiple of the data bit rate. The use of a multiplex suggests itself, but it is required that the through -connection of data connections does not need special handling in the central control.

In fig.. 1 a switching network DN is provided at each of the places Λ and B. At least one switching unit. Ο!5 η each of the networks DNW has at least one virtual highway unit VVF, which is made as a printed circuit board. This virtual highway circuit unit has unlike the other highway circuit units, neither an incoming nor an outgoing highway. The central control is so programmed that slow data channels to be switched from A to B or vice versa are switched via the virtual highway VVF as long as there are free channels, so that due to the properties of the switching unit used a maximum of 30 slow data channels can be collected in a multiplex per virtual highway.

From the virtual highway WF-A the data stream which reaches the switching network DNW-A via different channels, e.g. Κ13' Κ21' K5 °^ different highways VFl - VF3 and which was switched to the virtual highway WF-A in a first switching operation goes via a semi- permanently allocated time channel to a time channel of a highway VF5 going to the place B, is switched in the switching network D W-B via a semi-permanently allocated time channel to a virtual highway WF-B and therefrom to the appropriate individual time channels, e.g. K^, K23' K7 of highways VF7 - VF9 leaving the region B.

Semi-permanently allocated means in this context that the through-connection is normally permanent, but can be released or changed under control. of the central control. Such a semi-permanent allocation is obtained with TDM connections such that the corresponding switching addresses remain in the address store permanently or up to cancellation by the central control respectively.

Since for establishing a data connection for a slow data channel from A to B and from B to A the central control must give only orders for the through-connection to the respective virtual highways WF the conditions for the cental ^ control are the same, as the dashed line in fig. 1 between Λ and B would 'exist really. For this reason this line was called "virtual highway". In reality this data stream occupies between A and B instead of a complete highway having 30 + 2 channels only one channel of a highway.

There are different possibilities for establishing multiplexes. With a complete utilisation of the transmission capability of a PCM channel of 64 kBit/s and in consideration of the' already mentioned limitation of the number of the slow data channels to be combined in a multiplex the following multiplexes are possible: a) 20 data channels of 3.2 kBit/s = 64 kBit/s b) 5 data channels of 12.8 kBit/s = 64 kBit/s The establishment of a multiplex of data channels with different data flows is also possible, e.g.: c) 2 data channels of 12.8 kBit/s j 8 data channels of 3.2 kBit/s j> = total 64 kBit/s 16 data channels of 0.8 kBit/s With complete utilisation of the transmission capability of 64 kBit/s one of the data channels must be idle for taking over a superframe synchronisation. The superframe synchronisation signal can have any bit pattern but is preferably so chosen that the same systematic manner for the superframe synchronisation can be used as that for the PCM frame synchronisation.

It is assumed here in that each data channel arriving at the sv/itching centre orginates from a single data source, o but in fact a combination of several data channels into a single channel can be performed at the data subscriber in any manner if all such channels must have the same destination. ^ As already mentioned each slow data channel occupies from its peripheral to the switching unit used for establishing and releasing the multiplex connection TDM channel of a highway. The manner by which a slow data channel is brought to the bit rate of 64 kBit/s needed for using PCM channels and by which the bit rate of 64 kBit/s is brought back to the bit rate of the slow data channel is not part of this invention, but is described as far as it is necessary to describe the establishment and releasing of the multiplex.

To combine data signals of different sources into a multiplex two different methods are usually used. In the first method, code words are interleaved, and the method is called "time slot interleaving". In this method each code word within a superframe in a multiplex channel is allocated to a different data source or data receiver, respectively. To establish a multiplex from n slow data channels code words from different data sources are transmitted in each of n successive PCM frames and for an unambiguous allocation of the code word a superframe structure of n PCM frames is needed.

With the second method bits are interleaved, each avilable bit in the channel being allocated to a different data source or receiver, respectively. Since most normalised PCM systems use code words of 8 bits, it is possible to so combine 8 slow data channels to a multiplex v/here no superframe structur is needed since the position of each bit within a code word is given by the PCM frame synchronisation. To combine a higher number of slow data channels to a multiplex it is also possible to use a superframe structure consisting of m PCM frames so that a bit in a distinct position of a code word of the multiplex channel corresponds in each m-th PCM frame to the' momentary condition of a distinct slow data channel.

These two methods need different methods for conversion or reconversion, respectively, of the slow data channel to the PCM bit rate of 64 kBit/s or from the PCM bit rate to the data bit rate.

The first method for establishing and releasing a multiplex, i.e. the time slot interleaving method will now be described in more detail, assuming a multiplex of 20 equal data channels each of 3.2 kBit/s to be established.

Fig. 2 shows an intersection point between a slow data channel and a PCM channel. The incoming slow data line 1 has an information flow of 3.2 kBit/s, and the serially-arriving data are written into a serial-parallel register 2. As soon as the register 2 is filled with eight bits the 8-bit word is transferred parallel to the buffer store 3, whose output is connected to the channel no. 4 of the PCM terminal 4. During the time slot ZS4 of the channel the data word is read out from the buffer 3 at the PCM clock rate. Since only each 3.5 ms a new data word is written into the buffer store and the latter is read each 125 us, the same data word exists on channel no. 4 in 20 successive frames.

At the switching unit partially shown in fig. 3 this data word arrives on channel 4 of the highway VF1. In the switching unit a highway circuit unit i.e. a printed circuit board which carries the circuitry for one TDM highway, is allocated to each connected highway which unit comprises essentially a series-parallel converter (not shown) for the incoming highway, a parallel-series converter P/S for the outgoing highway, a speech store SS and an allocation store ZOS. As already mentioned a maximum of 28 highways can be connected to a switching unit, but operation with a lesser number of highways is also possible. The outputs of all speech stores of a switching unit are connected to a set of interhighways IH via which the through-connection is performed in a bit parallel manner .

To facilitate understanding the following description, the known operations performed in the switching unit for a speech connection will be described. For this reason we assume a two-way speech connection between channel 7 VFl and channel 11 of VF2. For such a call, with the aid of the central control, the address "VF2 Kll" is written into row 7 of Z0S1 and the address "VFl K7" is written on row 11 of Z0S2. A code word arriving during the time slot of channel 7 of VFl is written into row 7 of the store SSI after a series-parallel conversion. When, during the cyclic scanning of the allocation stores, it is the turn of row 11 of Z0S2, the code word in row.7 of SSI is read out onto the interhighway set IH according to the aldress "VFl K7" in row 11 and after a parallel-series conversion transmitted during the time slot of channel 11 on the highv/ay VF2. In the opposite direction a code word arriving on the highway VF2 during the time slot of channel 11 is written into row 11 of the speech store SS2 and is transmitted via the interhighway set IH during the time slot of channel 7 of the highway VFl. The store positions in the stores SS and the allocation stores ZOS occupied for this connection are indicated in the respective stores by dashed lines where the figure at the side indicates the number of the store row.

To establish and release a multiplex of several data channels at least one highway circuit unit of a switching u^-t is replaced by a multiplex circuit unit. The highway with the replaced circuit unit is called a virtual highway, as already mentioned, because the control is performed as for a normal highway circuit unit, and the circuit unit has neither an outgoing nor an incoming highway, but the output of its parallel-series converter is connected to the input of the respective speech store via a multiplexer logic, hereinafter called MUX-logic. In the present case the highway VF12 is the virtual highway.

The mode of operation of the virtual highway and the allocated MUX-logic can be explained with the embodiment of figure 3, where we assume that a multiplex according to (a) must be established and released, i.e. a maximum of 20 data channels each having an information flow of 3.2 kBit/s. For reasons of clearness in fig.. 3 only channel 4 of VFl and channel 18 of VF2 are occupied by a data channel where channel 26 of VF22 carries the multiplex channel.

The establishment of the multiplex is performed with two switching operations. IN a first operation all channels occupied with data are offered to the virtual highway. For this reason the addresses "VF2 K4" and "VF2 K18" are written into the row 8 and 10, respectively, of the allocation store Z0S12 of the virtual highway VF12.

The data v/ords arriving over the channel indicated by these addresses are stored as for speech code words in the respective speech store and are read out to the interhighway set IH at the respective scanning times of Z0S12. However they do not leave the switching unit since the output of the parallel-series converter P/S-^ ^s connected to the input of the MUX - logic. The storing and reading operation is performed for _ each channel once per frame of ±25jU s, but in this case the respective data word remains the same for 20 frames.

The MUX-logic is so designed that in each frame only one of the data words offered by the 20 different data channels is selected and stored into row 1 of the speech store SS12 of the virtual highway. During 20 successive frames a different channel is always selected, so that each of the data words of the 20 channels is stored into the speech store SS12 once during 20 frames. The MUX-logic is a wired logic circuit designed for t a certain kind of multiplex, e.g. having a distribution as mentioned under (a) , (b) or (c) .

In a second switching operation the contents of row 1 of the speech store SS12 are read out onto channel 26 of VF22. For this purpose the address "VF12 Kl" is se i-permanently stored in row 26. of the allocation store Z0S22. The read-out is performed in as already described. Since in row 1 of the speech store SS12 data words from different incoming channels are stored during 20 successive frames, but all such data words are read out onto channel 26 of VF22, these 20 data channels appear in a time multiplex on a single channel 26 of VF22 where an individual data channel appears at each 20th frame. To secure the correct release of the multiplex, a superframe synchronisation must be provided.

Fig. 4 shows that at the establishment of the multiple the writing operation is always performed into row 1 of the speech store SS12, e.g. in frame 7 within the superframe during the channel time 8.

This indicates why the. address "VF1 K4" is stored in row 8 of the allocation store Z0S12 although the data word is stored in reality into row 1 of SS12.

The release of the multiplex is also performed b ^twcj^ switching operations. In a first operation the data words arriving on' channel 26 of VF22 are transferred to the virtual highway, for which reason the address "VF22 K26" is semipermanently stored into row 1 of the allocation store ZOS 12. As for the first switching operation for establishing the multiplex, the code words pass from the interhighway set - IH to the MUX-logic. The latter ensures that the 20 data words of a superframe are written into 20 successive rows of the speech store SS12, starting with frame 1 into row 2 up to frame 20 into row 21, fig. 4. The start of the frame 1 is detected with the aid of the above-mentioned superframe synchronisation.

In a second switching operation the data words are read from the speech store SS12 to the respective highways. For this purpose the addresses "VF12 K8" and "VF12 K10" r respectively, are written into row 4 of Z0S1 and row 18 of Z0S2, respectively.

Since in each frame there is writing operation onto each channel, the contents of a distinct row of the speech store SS12 change only each 20th frame and the same data word is read out 20 times to a distinct channel. At the PCM terminal a buffer store operation is performed like that of fig. 2 with successive read-out onto the data line with the slow clock frequency.

Fig. 5 shows in tabular form the establishment of a-multiplex from 20 data channels DK. In the columns D l to DK20 the data words are indicated which are transmitted over different channels to the switching unit(s) and are offered to the MUX-logic of the virtual highway in the first switching operation. The framed data words are selected by the MUX-logic for storing into row 1 of the speech store SS12 during the frames indicated in the column next to the last. ^ The last column at the right side shows how the individual data words are arranged in the multiplex channel "VF22 K26" where the superframe structure can be seen.

Fig. 6 shows, also in tabular form, the release of a multiplex where the framed data words in the columns DKl to DK20 indicate in which of the frames indicated in the second column a new data word is written into the speech store rows 2 to 21 of SS12.

Thus it can be seen that to. switch slow data channels to remote receivers, addresses must be written into respective allocation stores as for speech connections, wherein the forming and releasing of the multiplex is performed in the virtual highway circuit unit, and that the second ' switching operation onto the really occupied single time channel used for the transmission of the data to the remote destination ' is performed with the aid of semi-permanently stored addresses. Thus the conditions for the central control are similar to what is required if the virtual highway were a real highway, so that no special programme at the central control is needed to switch slow data channels over a multiplex channel, with better utilisation of the transmitting capability of PCM channels.

To describe the second method of establishing and releasing a multiplex, which uses bit interleaving, it is assumed that a multiplex of 8 data channels each having an information flow of 3.2 kBit/s must be established and released. To transmit the data for each channel from a peripheral to the switching unit used for forming and releasing the multiplex, the data bit frequency of 3.2 kBit/s must be brought to the PCM bit frequency of 64 kBit/s. This is achieved in that the slow data signal controls a flip-flop, whose normalized output -^ ^ signal is scanned at the scanning time of the allocated channel. In response to the momentary conditions of the flip flop, code words OQOO 0000 or 1111 1111 can be transmitted to the switching network, and in the present case the same code word is sent alternately two or three times, respectively, until the condition of the flip-flop changes again.

Clearly in this case any one of the 8 bits of each code word can be selected to indicate the momentary condition of the signal of the slow data line. This fact is used in establishing the multiplex. Fig. 7 shows a portion of a switchin unit with a virtual highway, and is substantially the same as fig. 3 but contains indications to establish and release a multiplex with the bit interleaving method.

For. clarity only channels 4 and 9 highway VF1, channel 7 of VF2 and channel 17 of VF3 are occupied with data, where channel 3 of VF4 carries the multiplex channel and the highway VF7 is designed as the virtual highway.

Hence also, establishing the multiplex uses two switching operations. In a first operation all channels occupied with data are offered to the virtual highv/ay VF7. Fcr this reason the corresponding addresses are v/ritten into the allocation store Z0S7 of the virtual highv/ay. As for switching a normal speech channel e.g. the code word in the speech store row 9 of VFl is read out on to the interhighway set IH during the time slot of channel 6 of VF7 in accordance with the address stored in row 6 of Z0S7. Since the output of VF7 goes to the input of the MUX- logic this code v/ord does not leave the switching unit but it is offered to the MUX-logic.

The MUX-logic is so designed that it selects from each offered code word one bit for storing into a distinct bit position of row 1 of speech store SS7. Since this store is^ equipped in the same manner as the speech store of normal highway circuit units, i.e. for storing 8-bit code words, 8 possible bit positions are provided. Thus one bit of 8 different data channels can be stored. As mentioned, any one of the bits read from the corresponding speech store rows can be selected for storing in row 1 of SS7, since each bit indicates the momentary condition of the data line arriving at the periphery. To protect against bit errors in transmission between a peripheral and the switching unit the MUX~logic could also perform a majority decision for each channel and store the result of this decision in row 1 of SS7.

With a second switching operation the contents of row 1 of SS7 are read out ONTO channel 3 of VF4 for which the address "VF7 l" is semi-permanently stored in row 3 of Z0S4. Each bit of the code words going on channel 3 of VF4 to a remote virtual highway (demultiplexer) indicates the momentary condition of another one of the data channels connected to the virtual highway (multiplexer) . A superframe structure is not required since the bit position can be used for the correct allocation and the bit position is given by the normal PCM synchronisation.

Release of the multiplex also uses two switching operations. In a first such operation the code words arriving on channel 3 of VF4 are applied to the MUX-logic. The latter takes care that each bit of a code word is stored in a different row of the speech store SS7 with a simultaneous completion to a 8-bit code word, the completion being performed by bits equal to the respective one received from the multiplex channel.

Oil the strength of the addresses written into the allocation stores Z0S1 Z0S2 and ZOS3 in a second switching operation the code words in the speech store SS7 are transmitted to the peripherals during the corresponding time slot where e.g. one of the bits' of each code word controls a flip-flop the output signal of which is scanned with the data clock frequency of the slow data channel.

If only 7 instead of 8 slow data channels are combined to a multiplex and a scanning frequency of 4 khz does not cause an inadmissible distortion of the data stream of the slow data channel, it is possible to use the channel 0 reserved for the synchronisation as the data multiplex channel since the synchronisation information is distributed onto two frames and occupies only one bit position in each second frame.

Since the speech store and the allocation store, respectively, of the virtual highway are provided for storing 30 code words or 30 switching addresses, respectively, thus would be adapted for establishing and releasing a multiplex of 30 channels a superframe structure can be used also with the bit interleaving method. In this case only 7 of the 8 bits of the code words of the multiplex channels can be occupied with data since one bit is needed for the superframe synchronisation.

With a superframe consisting of 4 PCM frames in this manner 4 X 7 = 28 slow data channels can be combined to a data multiplex channel.

The corresponding MUX-logic has to select in this case for establishing the multiplex in each of four successive PCM frames one bit from each of seven speech channels occupied v/ith slow data channels for storing into corresponding bit positions of a speech store row of the virtual highway. For the releasing operation of the multiplex the MUX-logic has to detect the start of the superframe and to allocate each of the bits used for data of the data multiplex channel of four successive frames to' a different row of the speech store of the virtual higlway with a simultaneous completion to an 8-bit code word.

As in the case of the time slot interleaving method, for the bit interleaving method no special programme of the central control is needed. It is also possible to equip a switching unit with several virtual highway circuit units, some of which operate according to the time slot interleaving method and some of which according to the bit interleaving method.

Claims (8)

1. WHA33TWE CLAIM IS: Λ method of establishing and releasing a multiplex of n data channels within a switching unit of a PCM-TDM telecommunication switching system, in which the bit clock frequency of the PCM system is a multiple of the data bit frequency, in which system peripheral units are interconnected via PCM highways each having a first number of time channels to a switching network with several switching units each being able to set up a connection to highways of a second number of PCM highways, in which each of the data channels between the peripherals and the switching unit is used for forming and releasing the multiplex occupies a time channel of a highway and is switched within the switching network to said switching unit, in which to form the multiplex the contents of n highway channels occupied with data are offered in the switching unit in a first switching operation to a distinct channel of a highway called a virtual highway, in which a logic circuit performs a selection among the offered data information, and the selected data information is stored in a store row allocated to said channel of the virtual highway, in which in a second switching operation the contents of the store row are switched to a distinct channel of a further PCM highway used as the data multiplex channel for a certain destination, in which to release the multiplex the contents of the incoming data multiplex channel are switched in a first switching operation to the virtual highway, said logic circuit distributing the incoming information onto n storage rows such that each rov; receives only the information for an individual PCM highway channel going to one of the peripherals and being occupied with data, and in which in a second switching operation the storage contents of i each row are switched in each frame to the PCM highway channel used as a data channel. ^

2. An arrangement for carrying out the method of claijn 1, in which an individual highway circuit unit is provided for each PCM highway connected to a switching' unit, and in which at least one switching unit of a switching network has at least one highway circuit unit to the input of which a multiplexer logic is connected in series and the output highway of which goes to the input of the multiplexer logic.

3. A method according to claim 1, in which each data word arriving on one of n data channels from the outside is buffer-stored and repeatedly read out in successive PCM frames into a time channel of a PCM highway to the switching network, in which code words arriving from the switching network are stored at the periphery and read out to the data channel with the data clock frequency, in which to establish the multiplex the said logic circuit selects in the f-irst switching operation in each PCM frame one code word of only one of the n offered channels for storing into said storage row, and in which to release the multiplex the said logic circuit allocates in the first switching operation the code words of n successive frames of the data multiplex channel for storing in n different storage rows, where n is less or equal to said first number minus one.

4. A method according to claim 1, in a system wherein code words of k bits are used for all PCM highways, in which each data signal arriving from outside on one of n data channels is scanned once in each PCM frame and the sample is sent as a code word to the switching network, in which from the code words arriving from the switching network a corresponding data signal is produced, stored and read out to the outgoing data channel with the data bit frequency, in which to establish the multipl<| the said logic circuit in the first switching operation selects during m frames one bit from each of n offered code words for storing in said storage row in a different bit position, and in which to release the multiplex said logic circuit allocates in the first switching operation each data bit of a code word of the data multiplex channel for the storage in n different storage row with a simultaneous completion to a complete code word, where k, m, n are integers and either ^k if m=l or n:m'^k-l and n is Jess or equal to the'said first, number minus one if m -1.

5. A method according to claim 4, and in which the channel used for the PCM frame synchronisation is used in common as the data multiplex channel.

6. An arrangement according to claim 2, and in which the multiplexer logic is a wired logic circuit.

7. A method of establishing and releasing a multiplex of n data channels within. a switching unit of a TDM-PCM telecommunication . system, substantially as described with reference to the accompanying drawings.

8. Apparatus using the method of any one of- claim 1, 3, 4 , 5 or 7.