1. 43781/2 GLAIRSI 1· In a oalculaor system of the type implemented on semiconductor chips having a plurality of data register systems, one primary register system disposed on a first primary set of chips, and other peripheral data register systems each disposed on separate peripheral semiconductor chips, the method of addressing selected registers In selected registers in selected peripheral chips comprising ■tiie steps oft (a) communicating flag information from said primary system to said peripheral chips at a preselected timeI (b) communicating an address word to said peripheral chips in bit parallel/digit serial format| (c) discontinuing said flag communication! and (d) communicating data words between said primary register system and said pfei-ipheral register system* 2* The method according to claim 1 wherein said step of communicating data words comprises the step of transmitting from said primary set a bit arallel/digit serial data word which Is disposed Into a preselected register of said peripheral set in accordanc with system connection generated In response to said address word. \ k ; · I, 43781/2 2 · 3. The method according to Claim -wherein said primary system is timed in accordance with a first set of timing signals, and said peripheral set is timed in accordance with said first set of timing signals displayed by a selected interval. 3 4. The method according to Claim7*r wherein said step of communicating flag information comprises the steps of: (a) communicating a first flag signal indicating that a register in said peripheral set is to be addressed; and (b) communicating a second flag signal indicative of the rate at which said first flag signal, is communicated. ^ .— 5. The method according to Claim -and including the step of synchronizing the timing of said peripheral systems in accordance with said second flag signal. , 1 °· A method according to Claim ■¾· wherein the steps' of communicating an address word and communicating data words include transmitting the address word and the data words via the same path. 7. The method according to Claim 1 and further including the steps of entering & set of data bits into a data storage memory comprising: (a) sequentially entering a first subset of said data word into said memory without delay; (b) enetering a second subset of said set of said data word into a temporary register means; and (c) entering said second subset into said memory after a preselected delay. 43781/2 ' * .' ■· ■ 7 · 8. The method according to Claim and further including the step of right shifting said first subset in said memory prior to the step of entering "said second subset. . An electronic system having a decoder circuit comprising means for de-energizing said decode circuit to thereby decrease overall power dissipation. 1Q. The system according"'to Claim -ϋ- wherein said means for de-energizing comprises means for decoupling said decoder from an energization source. The system according to Claim' wherein said decoder is comprised of a matrix of rows and columns of logic elements and has load devices coupled thereto for actuating the rows and columns of logic elements, and further including means for de-energizing comprising means for gating said loads so as to energize said matrix only upon occurrence of input data to be decod 2, The system according to Claim-ri^ -and further including means for selectively gating the data input to said matrix. 1? , 5. ( The system according to Claim-4 -wherein actuation of said matrix provides an output of one logic state and the system further includes means for returning the logic state of said output to said other logic state. 13 14. The system according to Claim 4 wherein said decoder is a programmable logic array. 14 15. The system according to Claim l - wherein said system is a calculator system of semiconductor implementation. v or performing Jfte method_ of claim 2 characterized 16. A calculator sys eiff miiijjigy'first data "memory means implemented in one integrated semiconductor unit and 43781/2 auxilliary data memory means implemented in a second inte- 'v grated, semiconductor unit, means for addressing the auxilliary memory means by generating in said one unit indicia that an address follows and generating an address in said first data memory means, and means in said second unit responsive to said indicia to receive said address from the data memory means. 16 17. A calculator system according to Claim -ϊβ- wherein data is conveyed between the data memory means and the auxilliary memory means via the same path as said address .