IL42113A - Digital computing systems - Google Patents
Digital computing systemsInfo
- Publication number
- IL42113A IL42113A IL42113A IL4211373A IL42113A IL 42113 A IL42113 A IL 42113A IL 42113 A IL42113 A IL 42113A IL 4211373 A IL4211373 A IL 4211373A IL 42113 A IL42113 A IL 42113A
- Authority
- IL
- Israel
- Prior art keywords
- store
- operators
- automatically
- parameter
- statement
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
- G06F9/4482—Procedural
- G06F9/4484—Executing subprograms
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Devices For Executing Special Programs (AREA)
- Stored Programmes (AREA)
Claims (4)
1. What we claim is:~ lo A digital computer comprising a processor, a main store for containing digital data in the form of statements comprising operators and parameters in a compacted high level language as hereinbefore defined, a statement store, a parameter store, means automatically-operative to transfer operators or alternatively operators and parameters from the main store to the statement store, means automatically operative to transfer parameters from the main store to the parameter store in the sequential order in which they appear in the statement, sequence decode logic which automatically examines the operators in the statement store to determine their priority levels, a sequence store receiving the output of the sequence decode logic so as to automatically store the operators in accordance with their assigned priorities and a micro programme arrangement settable automatically in dependence upon the content of the sequence store and operative automatically to control the processor to process digital data automatically supplied thereto under the control of the parameter store and in accordance with the micro programme set up in the micro programme arrangement.
2. A digital computer comprising a processor, a main store for containing digital data in the form of statements comprising operators and parameters in a compacted high level language as hereinbefore defined, the operators and 4 parameters being of variable length coding, said length being determined by the amount of usage to which the operators and parameters are to be subjected and being in general of length inversely related to the amount of usage as aforesaid, a statement store, a parameter store, means automatically operative to transfer operators, or operators and parameters, of variable length from the main store to the statement store, means automatically -operative to transfer parameters of variable length from the main store to the parameter store in the sequential order in which they appear in the statement, sequence decode logic which automatically examines the operators in the statement store to determine their priority levels, a sequence store receiving the output of the sequence decode logic, so as to automatically store the operators in accordance with their assigned priorities and a micro programme arrangement settable automatically in dependence upon the content of the sequence store and operative automatically to control the processor to process digital data automatically supplied thereto under the control of the parameter store and in accordance with the micro programme set up in the micro programme arrangement „
3. , Digital computer as claimed in claim 1 or 2 and which has parameter decode logic operative to detect successive parameter units between operators in order to automatically determine the number of parameter units employed to form a parameter,
4. -„ A digital computer as claimed in claim 35 in which the parameter decode logic shares common elements with the sequence decode logic „ 5° A digital computer substantially as hereinbefore described with reference to the accompanying drawings toi&ey for App icants
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1979372 | 1972-04-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
IL42113A0 IL42113A0 (en) | 1973-07-30 |
IL42113A true IL42113A (en) | 1976-02-29 |
Family
ID=10135314
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IL42113A IL42113A (en) | 1972-04-28 | 1973-04-26 | Digital computing systems |
Country Status (5)
Country | Link |
---|---|
DE (1) | DE2321262A1 (en) |
FR (1) | FR2182569A5 (en) |
IL (1) | IL42113A (en) |
IT (1) | IT980931B (en) |
NL (1) | NL7305927A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AT336928B (en) * | 1975-04-28 | 1977-06-10 | Ibm Oesterreich | CIRCUIT ARRANGEMENT FOR TRANSLATING PROGRAM TEXT |
DE3069871D1 (en) * | 1979-09-24 | 1985-02-07 | Siemens Ag | Circuit arrangement for a microcomputer with an interpreter storage |
-
1973
- 1973-04-26 IL IL42113A patent/IL42113A/en unknown
- 1973-04-27 NL NL7305927A patent/NL7305927A/xx unknown
- 1973-04-27 DE DE2321262A patent/DE2321262A1/en active Pending
- 1973-04-27 FR FR7315547A patent/FR2182569A5/fr not_active Expired
- 1973-04-30 IT IT68200/73A patent/IT980931B/en active
Also Published As
Publication number | Publication date |
---|---|
DE2321262A1 (en) | 1973-11-15 |
IL42113A0 (en) | 1973-07-30 |
IT980931B (en) | 1974-10-10 |
FR2182569A5 (en) | 1973-12-07 |
NL7305927A (en) | 1973-10-30 |
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