IL35513A - Signal synthesizer - Google Patents

Abstract

1310036 Speech synthesiser LTV ELECTRO-SYSTEMS Inc 22 Oct 1970 [22 Oct 1969] 50267/70 Heading H4R In a speech synthesizer an input signal comprises a succession of frames of digital words, each frame comprising one word, defining the fundamental frequency of a speech signal, and a number of other words, defining the energy in respective predetermined frequency bands of the original speech signal. The frequency information word is used to produce digital signals indicative of the fundamental frequency and its harmonics up to a predetermined upper frequency limit. The digital signals corresponding to the various frequencies are combined with the respective amplitude information words to derive digital signals corresponding to instantaneous values of a sine wave of the corresponding frequency and amplitude. The derived digital signals in respect of each frame are summed, preferably equalized in level by reference to the number of harmonics contained, and the resulting digital signal converted to analogue form to provide the output speech signal. As described with respect to Fig. 1 the input control signal at 14 comprises a frame of 54 bits, six bits denoting the pitch frequency followed by fifteen groups of three bits and one group of two bits denoting the energy level in sixteen bands across the speech spectrum. A serial to parallel converter 18 feeds the incoming pitch frequency information to a pitch frequency register 26 and the amplitude signals to amplitude register 30. The pitch signals in register 26 are converted to signals defining the pitch frequency in binary form in converter 28 and the resulting signals are stored in store 29 for the remainder of the frame. During the remainder of the frame the pitch signal is fed to adder 35 and accumulator 36 which, at times defined by a clock signal from timing control 12, successively adds the pitch signal to itself a number of times to identify each of the pitch harmonics. A magnitude comparator 50 compares the various pitch harmonics with signals from the table of channel bandwidths 70 so that it is determined which pitch harmonics are associated with each of the energy level signals in the envelope register 30. A complete comparison cycle is completed in 1/256 th of the period of the period of the frequency corresponding to the pitch signal in the register 26 and a complete cycle of comparisons is signalled by a "K" pulse on line 52. The "K" pulse, as well as triggering the operation of output circuits 84, 85, 86, also triggers a K counter 80 which has a counting range of 256 so that the counter cycles at the pitch frequency. The actual state of the count of the K counter 80 is fed to the adder 77 and K-H accumulator 75 so that the signal on the output of the K-H accumulator increases at a steady rate between K pulses, the rate of increase varying with the state of the K pulse counter 80, and being reset by each K pulse. The signal appearing at the output of accumulator 75 is fed, via adder 78, to the table of amplitude modulated trigonometric functions 90 where, together with amplitude information for the various speech frequency analysis bands, appropriate binary numbers are selected corresponding to instantaneous values of each of the harmonics of the pitch frequency. These values are added and stored in 85, multiplied, in 84, by a scaling factor, to compensate for the change in level dependent on the number of harmonies present, and converted to analogue form by D to A converter 86, to provide an output sample of synthesized speech. During unvoiced sounds the pitch frequency information signal will be all zeros, this is detected by unvoiced detector 33 to cause energization of a noise generator 127 which injects, via adder 78, random numbers into the digital signal from the K-H accumulator. At the same time a number corresponding to a pitch frequency of 128 Hz is fed into the store 29 so that the "K" counter and K-H accumulator operate as for 128 KHz pitch, and the result is a natural sounding unvoiced signal output.

Description

Aims ιπκο SI&NAL SYNTHESIZER This invention relates to a synthesizer for converting consecutive frames of digital words into analog signals for producing a sound, each frame including bits relating to the fundamental frequency or pitch of the sound at a certain instant and to the amplitudes of a plurality of its harmonics at that inst nt .

It is recognized in the communications art that the transmifflsion of speech in the form of electrical signals, can be accomplished by digital rather than analog means, and certain favorable; results are achieved. Usable bandwidth is conserved under certain circumstances, less power is required and digital messages are harder to intercept. A graphic example is that digital voice^ -signals can.;be interleaved with other data from spacecraft, thus reducing the requirement for radio-frequency links with the spacecraft.

Scientists have recognized that a description of the speech signal, rather than the speech signal itself, e?an be transmitted, and the speech signal can be reconstructed from the description. The description includes carefully selected functions or parameters inherent in the speech and from which the speech can be reconstructed. The description t converted to a digital word format, and! in this form it requires less bandwidth when transmitted than the original, analog speech signal would have required.

Speech data are carried largely by the varying shape of th power density spectrum rather than by the sound-pressure versus time characteristic, as many erroneously believe. Thus, in one system the description of the speech is formed by an analysis of the power spectrum of a first signal by a series of band-pass filters that divide the audio spectrum into a series of adjacent bands. The energy in each band is measured at the output of each filter, and the energy measurement gives a rough, but continuous, description of the power^at^discrete portions of the incoming speech.

In addition to the channel amplitude-analysis, the analyzer provides data relating to the fundamental frequency or pitch inform-ation. Additionally, speech is composed of "voiced" and "unvoiced" sound. The voiced sounds include the vowels arid, the voiced consonants and are produced by vibrating the vocal cords with air^in the lungs.

Voiced sounds are composed primarily of harmonics of the frequency at which the larynx vibrates. The fundamental frequencies of the voiced sound lie primarily in a range from about 70 to 350 Hz.

The unvoiced sounds are the consonants formed by the lips, teeth, and/or tongue. They have no definite harmonic pattern, but consist essentially of frequencies randomly distributed throughout the audio spectrum and varying in amplitude in accordance with the sound being reproduced. Thus, the description of the speech includes the pitch frequency, amplitude information relating to bands of the voice-frequency spectrum, an indication that unvoiced sounds are present, end amplitude data relating to the unvoiced sounds.

To synthesize the voice with a channel synthesizer, a series of band- ass filters similar to those described above is: used in cooperation with the output of a buzz or hiss generator and balanced modulators to reconstruct intelligible speech.

Voice signal synthesizers utilizing filters are subject to at least two major objections. Since band-pass filters with infinitely short cutoff are not technically feasible, energy from one channel often appears in the next adjacent channel output, thereby producing a substantial amount of distortion. Additionally, a filter cannot have an infinitely short response time, and accordingly, energy is stored in each respective filter such that oscillations are set up in the filter circuit, again producing distortion of the voice-signal produced. Also, the use of a plurality of filters results in a construction that is too large and too heavy for applications where size and weight are critical factors, as in a space vehicle. Filters also require large amounts of power input with respect to the power of the output signal produced, since substantial losses are normally associated with filters. Still further, the error associated with the use of filters prevents the repeatabil ty, when required, of a particular signal with a requisite degree of accuracy.

Channel analyzers of the type described do not possess the requisite degree of flexibility required for present day application. It may be desirable in certain situations to shift the phase of a single harmonic or to modulate a harmonic with a second signal or to completely eliminate a particular harmonic in a given situation, thereby to improve or change the quality of the signal which is to be synthesized. For example, in some deep-sea exploration vehicles an atmosphere' is utilized which includes a high percentage of helium. The propagation of sound in helituti is distorted with respect to propagation of the same sound in air , thus producing an unnaturalness in the sound in the vehicle . If this distortion could be compensated for by a synthesizer which is capable of altering the pitch of the sound produced to compensate for the distorted propagation, it would be possible to thereby return to the sound of naturalness which has been lost .

Scientists and engineers have for some extended period of time sought to build a completely all-digit el , voice-signal synthesizer but have previously had only limited success. Any digital portions: of synthesizers presently known require extensive memory apparatus which limits the utility of the synthesizer with which the digital apparatus is; associated. A digital synthesizer which operates in real-time , thus avoiding the requirement for extensive memory apparatus , would be useful in many applications where synthesizers could not have been used previously .

According to the invention there is provided a synthesizer for converting consecutive frames of digital words into analog signals for producing a sound, each frame including bits relating to the fundamental frequency or pitch of the sound at a certain instant and to the amplitudes of a plurality of its harmonics at that instant, the synthesizer comprising:- (a) means for storing bits representing the fundamental frequency and its amplitude, (b) means for providing and storing bits representing the frequency of the harmonics, (c) means for storing bits representing the amplitudes of the harmonics, (d) means for providing bits representing respective bandwidth markers, each marker characterizing a terminal frequency of one of a series of predetermined consecutive bands in said sound; (e) means for comparing the content of (b) with the bandwidth marker bits to provide bits representing the harmonic frequencies In the selected bands; and (f) means responsive to (a) and to associate the content of (c) with the bits representing the harmonic frequencies in the selected bands for providing and storing a train of bits for the purpose of formulating a predetermined number of terms in a harmonic series, which terms include the product of the fundamental frequency and its amplitude and the.: product of the harmonic frequencies in selected bands and their respective amplitudes at said instant, (g) means; to accumulate the bits in the train to sum the series, and (h) means to generate an analog signal corresponding with the sum of said series, which analog signal represents an instantaneous value of said sound, whereby said sound is reproduced by converting the consecutive frames into the analo signals.

Additional objects; and advantages of the invention will be readily apparent from the; reading of the follov/ing description of devices constructed in accordance with the invention, and reference to the accompanying drawings thereof, wherein: Brief Description of the Drawings.

Figure ΐ is a block diagram of a signal synthesizer embodying the invention; ' ' ' ' . ' Figure 2 is a diagrammatic illustration of a digitally coded, serial-input signal coupled to the synthesizer of Figure 1;.

Figure 3 is a graph illustrating the computation of the frequency components of the synthesized signal; Figure 4 is a graph illustrating a technique used to obtain sine information in the synthesized signal; Figure 5 is a graph illustrating the basic method of computation; · > * Figure 6 is a simplified schematic drawing of the serial-to-parallel converter of FIG. 1; Figure 7 is a simplified schematic drawing of the amplitude buffer register of' FIG. 1; Figure 8 is a simplified schematic drawing of the 12-bit adder-accumulator combination of FIG.'l; magnitudej Figure 9 is a simplified schematic drawing of the{frwgr""1 fcwjn) comparator , the envelope update control , and the table of channel bandwidths of FIG. 1; Figure 10 is a simplified schematic of the K-index and synchronization control of FIG. 1; Figure 11 is a simplified schematic of the table of amplitude modulated trig functions of FIG. 1; Figure 12 is a diagrammatic illustration of the general timing of various components of the synthesizer of FIG. 1; and Figure 13 is a simplified schematic of the noise generator/, of FIG. 1. res 1 and 2 of the drawing, the illustrated embodiment of the invention is a synthesizer 10 used to convert digitally coded information r- relating to a first analog signal into analog signals which may in turn be used to reproduce th© fir#t signal. ί ' Voice analyzers for translating speech into digital code >known* or signals are well ***** A digital signal produced by one of these analyzers may comprise, as illustrated in FIG. 2, ,190 consecutive frames F, such a Q&, of digital words containing information relating to the fundamental parameters of speech at consecutive, predetermined, spaced instants of time. In. 0 the analyzer described* digital signals are transmitted at the rate of 2400 bits per second. Additionally, each frame contains information relating to whether the speech at a particular instant of time is voiced or unvoiced, a definition of the fundamental frequency of the speech at the given instant 5 . to which the frame' is related if the sound is voiced sound, and the amplitude of the energy level of a predetermined, consecutive series of bands or spectrum segments spaced within the band of voice frequencies jf nQi.d&aftinifrg-, whether the speech . is voiced or unvoiced at that time. Thus, each frame 90 includes 0 17 words, the first being a 6-bit word^^coded to identify the fundamental frequency of the voiced sound or to indicate that ined, consecutive band or spectrum segment of the band of voice frequencies at the one instant of time with which the frame is associater". The seventeenth word similarly , provides the amplitude information for the sixteenth band, but as opposed to the other words in the series, it does so with two bits; \ ; the last bit of the frame being a synchronization bit .

For example , the firsrt 3-bit word 93 indicates the amplitude energy of the speech in the band between 200 Hz to 332 Hz and so on with the last word 96 indicating the amplitude of the energy in the spectrum sigment between 3331 Hz and 3β20 Hz. The consecutive bands of the frame related to a respective word each increase in width with respect to frequency in a predetermined, selected manner, for example, the expansion may be on a logarithmic " scale.

The synchronization bit 97 serves to maintain proper synchronization of the timing relationships between th operation of the various circuits of the voice synthesizer Ί0· The synthesizer of this invention is a special purpose computing device. It receives the input information at a rate of 2400 bps, and the bit stream consists of serially arranged 54-bit frames of the^ type previously described.

To fully understand the method of reconstruction of the original, analog signal from the description of the sound represented by that signal , the method of computation": must be explored. The general form of the computation is as follows In this equation is the summation of a sequence of computations r elating to the amplitude and frequency of the analog signal to be constructed, where the summation computation is performed for specific time instants . The term f is the pitch or fundamental frequency in Hz for which the computation is performed, and the term H represents the harmonic number (i.e., 1i , 2, 3 » . . . .N ) for the harmonics associated with the^. pitch frequency. The term A^H ^ represents the amplitude of the envelope during a particular time-instant of a fundamental frequency (where H = 1 ) or a sine-wave harmonic (for values of H in excess of 1 ) of the sound to "be generated. The term T is an incremental unit of time associated with the computation of the amplitude of one point for one particular harmonic; L represents the greatest product of H.f that is less than 3820 Hz; C represents a scaling factor relating to the number of computations to be performed during the cycle of the basic pitch period; and K represents a time index related to the number of computations to be performed with respect to a particular cycle of the pitch frequency.

The terms K, T, and C are fully explained in the following portions: of the disclosure. The upper limit of the band of frequencies considered has been selected, in the embodiment disclosed, as 3820 Hz. This use of this upper limit, as opposed to -4000 Hz, facilitates computation and does not substantially effect the intelligibility or quality of the output produced.

In its expanded form, equation (*t) above can be written as follows for successive periods of time: ) X ... Ά(Η.ί) Sin 2-iT(H.f')(K,T) Referring no particularly to Pig, 5, a pitch or fundamental frequency f is illustrated with each of its harmonics (2f, 3f, f....n«f) included in a speech-hand of frequencies having a top frequency of 3820 Hz. For purposes of illustration, an output curve 9t is shown which theoretically represents the summation of the pitch frequency with each of its harmonics fallin within the prescribed speech-hand.

In the embodiment described, the lowest pitch-frequency which is dealt with is; 7k Hz, since this corresponds approximately with the lower-end of the band of fundamental or pitch frequencies. It has been decided arbitrarily to compute 256 points during any one complete cycle of a 7k Hz signal and 256 Ί@& points for each harmonic thereof where the points computed for the harmonics are equally spaced over a t ime span equal to the period of the ftmdamental; thus a representative scale, where the pitch frequency is equal to 7k Hz, is set forth in Fig. 5, and as will be fully explained in the material that follows, the pitch frequency on which a computation is based will change, but the computing rate of K ¾ 256 will remain constant. In other words, at a pitch frequency of 7k Hz, 256 computations are made in a time-span of approximately 13·5 m sec. (the period of one cycle of a 7k Hz signal). For each harmonic of the 7^pitch frequency, 256 computations are made in the same time span; thus, the time-duration of a point to be computed (for the 7k Hz fundamental and each of its harmonics) will be: 13.5 m sec. B 52.7 A sec. 25b Since the upper-limit of the voice-band for this embodiment is set at 3820 Hz, with a fundamental frequency of 74 Hz there will be 3820 or 51 harmonics lying in the 74 voice-band. The total time of the computation is 52.7 μ sec, thus the value of a point for each harmonic or the fundamental is computed in approximately 52,7 or 1.03 μ sec. 51 Examining now the equations (2), (3), and (4) set forth above with respect to FIG. 5» it can be seen that the amplitude of tl\e output curve 91 at a particular time increment t is computed by providing the correct values of the unknowns and solving a respective equation, thus, if = equation (3) provides a value for the amplitude of the output signal at the second increment of time (t2) . In equations (2), -(3)» and (4), the portions of the respective e a ions labeled a, a-^,....an represent the first harmonic component of the computation, b^-^, and bn represent the second harmonic component, and similarly m, m^, and mn represent the mth harmonic of the computation. Upon close examination, it will also be apparent now that if the respective components a, a^,....an are plotted for respective time periods K, that the pitch frequency will be reproduced and that as the number of increments are increased, the accuracy of the reproduction of the sine wave representing the pitch frequency is improved.

The pitch frequencies utilized in this device fall in the range from 74 to 310 Hz. Those skilled in the art will recognize that the band of pitch frequencies is normally considered to be approximately 7-+-330 Hz, but this band can be modified slightly without seriously effecting the quality of the sound produced (when voice is the object) and without effecting operations of the machine. Consider now a specific example of a computation for the pitch frequency of 310 Ηζ· The expansion of the general equation (i) can be summarily written, as follows: 12.38/^sec ( 5 ) X( tl ) + ... + A( 3M 0) Sin 2° ( 6) 0)gin 2*2*2Τϊ Τ W + (Spectrum component segment (8.) adds to aero for the value K=256, since the time t^ is taken as Q + 1.) The total computation time for computing the components X + Xf+ ....X + \ would be only 3.17 milliseconds, since there are only 11 computations, i.e., 12. possible harmonics of the pitch frequency that lie between 3 0 Hz and 3820 Hz ^310° = 12^ * Tlie ^oi:al ^11^^"^011 time for any ¾k where the pitch frequency is 310 Hz, is 12.38 μ sec, thus the total computation time for all the time-segments at 310 Hz —6 pitch frequency would be 3.17 milliseconds (12.38 x 10"" x 256= 3.17 x 10" t as compared to the total computation time of 13» 5 milliseconds when the pitch frequency was 74 Hz.

The computation time required to compute each element of the equations (5) - (8) is still 1.03 microseconds, as with the previous equations.

Each frame of the digitally coded input information (the description of the sound) contains the information necessary to accomplish the general computation set forth above for one pitch frequency and for each harmonic thereof.

Referring particularly to FIG. 2 and to equations (2), (3)» and (4) the 6-bit word 92 identified the basic pitch-frequency f relating to a frame, and each 3-1)it word such as 93 contains the amplitude information relating to at least one harmonic which falls within one of a preselected series of divisions of the voice-band or spectrum. Because of the spacing of the preselected divisions or bands of the voice-band, and the spacing of the harmonics relating to the pitch frequency identified, more than one harmonic may lie within a particular division or there may be no harmonic in the division. Where more than one harmonic occurs in a division, the A^H f^ information represented by a word is representative of the total power in the harmonics falling in this division o the original signal which was coded, A eat&sfactory representation of the voice spectrum of the original signal at the output of the synthesizer 10, may be obtained by employing a frame period of the order of the magnitude of the largest pitch period associated with a fundamental frequency. If the frame is too long, insufficient information would be transmitted to adequately represent the original signal. On the; other hand, the frame may be made as short as desired, limited only by the speed of response of the circuits used* In the embodiment disclosed the frame repetition period is 22.5 m sec, and the frames are presented without interruption, in series.

A. Input Means.

Re erring now to Pig. , the digitallyTSput information is applied to an input terminal li+ which is coupled to an input control-unit 13· The input control-unit 13 operates to synchronize the input information to the input means located generally at 15 and including a serial-to-parallel converter 8, a 148-bit, amplitude-data buffer-register 22, a 6-bit pitch-frequency buffer-register 26, a logic-unit 28 input control 13 generates a 2400 bit-per-second (bps), square wave, pulse-train or clock signal which is substantially independent of other timing apparatus within the synchronizer 10 and this clock signal is coupled. to the serial-to-parallel converter 18 by a lead 19. The serial input-data applied to the input control 13 is transferred from the input control, over line 17, to the converter 18, and each frame of the serial input-data is synchronized with a clock pulse from lead 19, on a bit-by-bit basis, in the converter such that the data received by the converter over line 17 is synchronized to the operation of the input means. Additionally, a signal corresponding to the synchronous bit associated with each frame of input data is coupled through a lead 16 to the amplitude buffer-register 22, to the pitch-frequency buffer-register 26, and to the K-index and synchronization control unit 20. The signal appearinq on line -16 is essentially a pulse-train with a repetition rate of 44.44 bps or one pulse every 54 counts of the 2400 bps clock.

Referring to FIG. 6, the serial-to-parallel converter 18 is of a type well-known to the art relating to digital computer technology.

The converter 18 utilizes flip-flops which are also well-known, and those skilled in the art will recognize that a flip-flop has first and second input connections, first and second output connections, generally labeled Q and Q ("not Q"), a clock input which operates in response to a pulse applied thereto to set the data at the input to the output, and a reset connection which operates in response to a pulse applied thereto to clear the output of the flip-flop. Flip-flops are too well known in the art to require more than the general description provided. Additionally, a one or high referred to herein implies the presence of a D.C. voltage of a given magnitude, and a low or zero refers to the absence of a voltage. In the embodiment illustrated, a voltage of 5 volts D.C. is used as a one. Essentially, a first output connection of each flip-flop corresponds to the first input connection of the same flip-flop, and similarly, a second output connection corresponds to the second input connection, such that when a timing pulse is applied to a clock input of the flip-flop, the output changes state to a condition corresponding to the condition at the input at the time the timing pulse was applied.

The serial data on line 17 is coupled to the input of converter 18 wherein the serial signal is divided into two parallel paths 17, 17a, one path 17a including an inverter 21, and each of the parallel paths are applied directly to respective input connections of a first flip-flop 23 of a group of 54 parallel-connected, flip-flops 23. The first flip-flop 23 includes a first input connection to which line 17 is coupled and a second input connection to which line 17a is coupled; however, the second coupling is through the inverter 21, such that if one bit of the input serial data is a one, the one is applied directly to the first input-connection, and a zero is applied to the second input connection. Conversely, if a zero is applied to the first input connection, a one is applied to the second input connection. The output connections of the first flip-flop 23 are coupled to the input connections of the second flip-flop 23 and so on through the remaining flip-flops of the group. The lead 19 is coupled to the clock input of each flip-flop 23 in the -string. Thus., where each set-reset input is pulsed simultaneously at a rate of 2400 pulses-per-second by the clock signal on line 19, the 2400 bps input data on line 17 is stepped serially through the flip-flops 23, and at the end of each 54 consecutive steps, the serial bits clocked into the first output- connection of each flip-flop corresponds to a respective bit of the 54-bit frame of input data, as shown in FIG. 2.

Thus, a lead, such as 24 , is coupled to the first output-connec tion of each respective flip-flop 23 to provide the desired parallel-data output from the converter 18.

As shown in FIG. 2, the first bit of data to enter the converter 18 with respect to time is the first bit of the 6-bit word related to the pitch frequency of the frame. The last . word entering the converter 18 is a 3-bit word representative of the energy level of the harmonics located in the 16th segment of the voice band, and this 3-bit word includes a synchro-. nization bit which is actually the last bit in the frame. For this reason, the amplitude of the energy level associated with this last word is treated in the synthesizer as having only two significant bits.

Referring now to FIG. 7, the 48-bits of amplitude infor- 22) mation are coupled to the amplitude buffer-register ¾S through parallel leads 24 and are coupled interiorly of the register to input of flip-flops 27. As previously explained, a signal synchroniza-1-. 2, and this signal is applied to the clock input of each respective flip-flop 27, simultaneously. Thus, the output of each flip-flop 27 is set in accordance with the data on its input and is set at a time when a complete frame of data is available in parallel-form from the serial-to-parallel converter 18; therefore, the- arallel data is stored in buffer-register 22 for a time- synchronization pulse on line 16 or 22.5 milliseconds. Λ sep- ~^ arate lead, such as 25, is coupled to the noninverted output (Q) connection of each flip-flop 27 and; is coupled to the envelope register 30 (PIG. 1) for use therein at a subsequent time. The buffer-register 22 operates to store the amplitude data while a new frame of serial input data is being converted to parallel form by converter 18 and while the last frame of data stored in the register 22 is being processed by the other circuitry of the synthesizer 10.

Similarly, the six bits of pitch frequency information of each frame is coupled through parallel leads, such as 24, > to a pitch frequency buffer-register 26 (FIG. 1). Refer to FIG. 1. Except for the number of flip-flops used therein, the register 26 is substantially identical in operatibn and construction to the register 22. The output of register 26 includes conversion unit 28.

The frequency data conversion unit 28 of FIG. 1 operates to convert the digitally coded input information to binary format and operates to change the frequency format arrangement of the digitally coded input information into a binary format usable in the digital equipment of the synthesizer.

Specifically, channel analyzers available at present code eubstscut1ally v the pitch-frequency data-in accordance with the following code: TABLE 1 Frequency Value (Hz) Word Code (Approximate) 1 000000 0 (SPECIAL CODB) 2 000001 74 3 000010 78 4 000011 82 dooioo 86 6 000101 91 7 000110 95 4' 64 xxxxxx As will be explained in the following description, it is important to obtain even multiples of the word of the description relating to a pitch frequency in order to obtain binary- . language numbers relating to the harmonics of the pitch frequency of a particular frame. It is common computing practice to double a binary number in the manner illustrated by the following example: 000001 = 1 + 000001 = +_1 000010 = 2 Referring to Table 1/ set forth above, it is easy to see that if word 2 is doubled in accordance with the example, i.e., adding the coded word 000001 to itself would result in a word in the code of Table 1 that would correspond to 78 Hz and not 148 Hz (2f) . Thus, the conversion': from the coded information to standard binary arithmetic units is necessary. A frequency-data conversion unit useful in the embodiment illustrated and for the purpose described is manufactured by the National Semiconductor Company (Model MM422) of Santa converting In the process of Jjsennoofein jf he coded data to binary arithmetic units, still another result is obtained. Referring again to Table 1, it is apparent that there exists a substantially linear change in frequency between words 2-64, but not between words 1 and 2. By converting the coded data to r the standard binary arithmetic terms, the nonlinear change which would otherwise disrupt computations is rendered insig-nificant. · ' " Additionally, the frequency data conversion unit 28 operates to expand the coded data to a 9-bit word, as opposed to the 6-bit word of the coded input data'. It will be appar-ent to those skilled in the art that a 6Ht>it word of standard binary arithmetic would not add to 310 Hz. For instance, a standard lows: It is common knowledge that a one in, for example, place 3 (000100) represents the number 4 to the base 10; a one in • I " · . ' place 3 and in place 2 (000110) would be the number * to the base 10; and so until there is a one in each of the places 1-6 (111111) whereupon the number represented is 63, which is also the maximum number that can be represented with one 6-bit word; thus, if the binary number is expanded to 9 bits (in lieu of 6) , the binary number for 310 is easily formed (100110110) , and 9 places is the first possible combination enabling a representation of the number 310. It follows that the frequency data conversion unit 28 has nine, parallel, output-leads, such as 32, and these leads couple the conversion unit to the frequency storage unit 29 and to the unvoiced detector 33.

The frequency storage unit 29 is a storage register including flip-flops and is similar in construction and operations to the amplitude buffer-register 22 and the pitch frequency buffer-register 26, except that in the storage unit 29 there are at least 9 flip-flops, one corresponding to each bit, and a respective one of the leads 32 are coupled to the input of each respective flip-flop and the ncninverted output of each flip-flop is coupled through a respective lead, such as 34, to a 12-bit adder 35. The frequency storage unit 29 operates to store the data input thereto from the conversion unit 28 until such time as the pitch frequency reaches the end of a cycle, thus enabling the synchronization of the data out of the input means 15. with the operation of the other circuitry of the synthesizer 10. The flip-flops of the frequency storage unit 29 are gated by a signal from the K-index and synchronization control unit 40, as will be shown in .the following description, to cause the data stored in the storage unit to be transferred to the adder 35. The timing of the gating signal is set to prevent the interruption of the computation cycle by the introduction of new data into the computing portion of the synthesizer 10 at an inopportune moment.

B. Control Means.

The 12-bit adder 35 and the accumulator 36 operate to produce binary words corresponding to certain, successive harmonics of the pitch frequency of a respective frame.

The timing and output control unit 12 is the master timing unit for the computing portion of the synthesizer 10.

The unit includes a crystal-controlled oscillator and a series of flip-flops which serve as frequency dividers in a manner which is well known to those skilled in the art, such In the embodiment disclosed, clock 0 is 7.76 MHz p'ulse-train, clock 1 is 3.88 MHz, clock 2 is 1.94 MHz, clock 4 is 0.97 MHz, and clock 8 is 0.425 MHz, and through connection to the inverted output of each respective flip-flop of the divider, 5 addi-tional timing signals, each 180w out of phase with a respective one of the above clocks 0-8, are also available. Additionally, where required, combinations of the above disclosed timing signals are used to generate still other timing signals. For ~ instance, a'.1.03 ,M$ia/clock is generated by the conibination of dockland clock^ . In FIG. 1, the timing pulses are coupled to the various units by certain ones of ten separate leads, such as 42. \ Each bit of the 9-bit word is transferred from the frequency storage unit 29 to, the adder 35 over parallel leads, such as 34, and is applied to a respective adder section, such as 39 in FIG. 8. There are more adder sections (12) than there are input data bits (9) to allow room f6r binary expansion of i-the number. The input data bits are coupled to the adder inputs corresponding to the nine least significant bits. ; Each of the adder sections 39 is of a type which is well-known, and a^ FairchiId -integrated circuit chip model 9304 , manu acturer by Fairchild Semiconductor of Mountain View, California, is a typical device useful in this embodiment. The Fairchild device incorporates two of the respective adder sections, such as 39, in one chip. Each adder section 39 includes three inputs, identified as IN#1, IN#2, carry input (C^n) and two outputs, identified as carry output (cout) an3 sum, respectively, and the adder sections operate in accordance with the following truth table: 5 1 ADDER TRUTH TABLE IN#1 IN#2 c SUM COUT 0 0 0 Ό 0 0 0 1 0 1 0 1 Q 0 1 0 1 1 X 0 1 0 0 0 1 1 0 1 ■1 ■ 0 1 1 0 1 0 1 1 1 :i i table that if a one only^input oi the respective inputs, then the sum is 1 or decimal 2° = 1, but if any two of the inputs have ones applied thereto, then a one appears at CQ.

An adder-accumulator arrangement illustrative of the operation of this portion of this invention is shown in FIG. 8 The accumulator 36 includes 12 flip-flops 53, and the sum output of each adder section 39 is coupled through a lead 37 to both the inverting and noninverting input connection" a respective flip-flop 53. The noninverting output ^©wof . . . . \ · . . . '" . each flip-flop 53 is coupled through a lead 38 to the second input connection (I^) of a respective adder section 39 and through a second lead, such as 44, to the magnitude comparator 50 (FIG. 1) . There are 12 corresponding adders 39 and flip-flops 53 in the two units and the carry input (Cj^) of the first adder section is grounded to prevent accidental input of false information. The carry output (CQ) of each respective adder section 39 is coupled directly to the carry input (C.„) of the next adjacent adder section, and the of the IN J 0 last adder section 39 is left open. In the accumulator 36, the clock input of each respective flip-flop 53 is coupled through the lead 42 to the timing and control unit 12 (FIG. 1) and the reset input of each respective flip-flop is coupled through a lead 43 to the K-index and synchronization control unit 40 (FIG. 1) . As will be described in the material that follows, the pulse on lead 43 is used to re-set the accumulator 36 when processing of a particular frame of data is completed. With this description, it will now be apparent that each time a strobe or clock pulse is applied to the lead 42 by the timing and output control unit 12 (FIG. 1) , that the binary number appearing on leads 34 will be added to itself, such that the binary word at the output leads 44 will increase in even multiples, and therefore will represent successive harmonics of the pitch frequency, i.e., 2f, 3f, 4f, etc. For instance, if the pitch frequency is 74 Hz, the binary word on lead 34 is 000001001010, on application of the first strobe-pulse the number on lead 44 becomes 000010010100 or 148 (22 + 24 + 27 = 4 + 16 + 128 = 148).

In the embodiment described, it was decided that an operating frequency range of from 200 Hz to 3820 Hz would produce the accuracy of sound reproduction desired; thus, sixteen convenient bands of frequencies within the voice frequency band selected were chosen for use and are identified as lying between the bandwidth markers set forth below: BW Marker 0 200 HZ 1 332 " 2 464 " 3 596 " 4 ■ 728 " 860 " 6 992 " 7 1,135 " 8 1,300 " 9 1,485 " 1,700 " 11 1,945 " 12 2,225 " 13 2,545 " 14 2,910 " 3,330 " 16 3,820 " 17 Recycle The table of channel bandwidths 70 operates to produce on its output leads, such as 46, 7-b L binary word representative of a respective one of the frequency markers set table/ forth above. When the/fB#^e 70 isLproperly signaled, as by a pulse from the envelope update control 60 over "a lead 45, the output switches to a 7-bit wore! representative of the Only the 7 most-significant bits (MSB's) of the output of the accumulator 36 are coupled ¾o the magnitude comparator 50 by seven parallel leads, such as 44, and the output of the table of channel bandwidths 70 is coupled to the comparator U . · · -, ' by seven leads, such as 46, The comparator 50 operates to compare the words coupled thereto from the table 70 and the accumulator 36, and if the value of the binary word presented by the accumulator is equal to or greater than the value of the binary word presented by the table 70, then the output of the comparator, at lead kit changes state; for instance, the output may change from zero volts to a substantially constant D.C. voltage of a few tenths of a volt. Comparators suitable for use in this circuit are available from several sources, and in particular, a pair of National Semiconductor Corporation -bit comparators, model DM7200/DRT8200, coupled in parallel, are suitable for use in this embodiment.

Referring now to Pig. 9, the comparator 50, the envelope update control 60 and the table of channel bandwidths 70 cooperate to produce the result set forth above. As previously stated, the smallest frequency represented by the output of the table 70 is 200 Hz, thus there is always a word on line i+6 equal to or greater than 200 Hz. From the timing considerations set forth in the following material, it will be apparent that new data is presented on line k only when the output of table 70 equals or exceeds 200 Hz. If at a particular instant, the value of a number represented on line k is smaller than 200 Hz, the output of comparator 50 does not change; however, as successive strobe-pulses are applied to the adder-accumulator combination 35» 36, over lines ½, as previously described, the accumulator output builds up until it eventually represents 8 frequency which equals or exceeds the 200 Hz magnitude, and at this time, the output of the comparator 50 changes state, typically from zero to some positive D.C. value. The output of the comparator 50 is coupled by a lead k7 to the envelope update 60 and specifically to a NAND-gate 55 located therein. The NAND-gate 55 has three input-connections and operates in response to the presence of three positive signals, one on each respective input to produce a negative swing or low at its output. The clock pulses from lead 42 are coupled to the input of gate 55 and are normally high, but periodically swing low for the' purpose set forth below. A negative swing at the output of gate 55 is inverted by an inverter 56 and coupled to the input of a digital counter 57 which responds to the application of a positive-going signal at its input to increase the number represented by its outpu by one. · The output of the digital counter 57 is a 4-bit word which has 16j specific combinations of binary digits (0000 through 1111) , i representing the numbers from l-16T-on [^thus , the counter output provides an address for the first 16 successive marker frequencies set forth above. When the marker frequency is 2CC Ks , the c o of the counter is 0000, and v/hen the or, on line 44 represents a value equal to or larger' than 200 Hz, then the comparator 50 output changes state and the output of the digital counter 57 changes to 0001 . This address, (0001) is coupled by lines 45 to the table of channel bandwidths 70 and is coupled therein to each of seventeen detect-only gates 58. A digital counter of the type described herein is a model S8281J 4-bit binary counter/storage element manufactured by Sigrtetics Corporation, Sunnyvale, California.

Each detect-only gate 58, except the seventeenth, recognizes only one of the sixteen possible combinations of the output of the counter 57.. The read-only or detect-only memories 58 are of a type which are well-known and a typical integrated, circuit chip for use as the read-only gate of this invention is a model MM-422 manufactured by National Semiconductor Com an of Santa Clara California. The out ut of each read-only memory 58 is coupled to a respective bank 59 of parallel-connected diodes 61. Upon the application of the proper binary word to the input of the respective detect-only gate 58 the output of the gate changes states, typically from positive to zero. Certain diodes 61 are omitted from the bank 59 associated with each gate, and the omission gives the indication of a zero at the output of the bank; thus, a particular 7-bit word is created in association with each respective detect-only gate 58. The output of each respective diode bank 59 is connected in parallel with the respective outputs of other diode banks, and all the bank outputs are coupled through leads 46 to the input of the comparator 50. When the output of the digital counter 57 is increased in value, by one step, the next succeeding detect-only gate 58 is addressed and activated, and the corresponding diode bank 59 produces a binary word representing the next marker frequency. Again, the output of the accumulator 36 (FIG. 1) increases, and the harmonic value thus produced is compared to the new frequency marker until a comparison is again achieved, in which case the entire process is repeated such that the next marker frequency is brought up for comparison.

A pair of timing signals from the timing and output control 12 are applied to respective inputs of the NA D-gate 55, and, as previously stated, the gate responds to high voltages (ones) on each of the gate leads, in this case 3, to cause the envelope update 60 to operate. Specifically, the timing signals are arranged to force the gate 55 to operate when a harmonic of the pitch frequency does not fall within the specific band. For instance, consider the pitch frequency of 180 Hz and its second harmonic of 360 Hz. Examining the list \ of marker frequencies set forth above, it is clear that a harmonic of the pitch frequency does not fall within the band defined by markers 200 Hz and 332 Hz. When the processing of this pitch frequency begins, the signal from the Table 70 represents 200 Hz and the signal from the accumulator represents 180 Hz, thus' a compare signal is not generated on line 47.

As the accumulator 36 is strobed again, over line 42, the signal at e output of the accumulator goes high, i.e., changes state from zero to a positive voltage, thus indicating that a comparison has been made. After a short delay which update 60' output signal, which in our example is now 332 Hz, but notice that the signa.1 from the accumulator 36 is still larger than the signal from the table, This being the case, the counter 57 of the envelope update 60 cannot be made to step, since the input to the comparator 50 does not call for a change at its output on line 47. As a result, the process of cycling bandwidths by units 50, 60 and 70 is halted, and the computation is disrupted. The timing pulses applied to NAND-gate 55 are arranged to cure the problem relating to the lack of harmonics falling in a band, between markers. In the embodiment illustrated, the three inputs to the NAND-gate 55 must be high, each representing ones, to cause the output of the gate to switch low, thereby enabling the circuitry .to cause the counter 57 to switch.

Thus, timing pulses are arranged on at least one of the lines 42 coupled- to the input of the gate 55 such that at least once every cycle of the comparator 50, the voltage on the at least one lead drops to zero for a short period, and if the compare signal has not been generated by a normal; compare, i.e., the presence of a harmonic in the band, then as the voltage on th^ at least one lead returns to a high, a false compare is generated, and the counter 57 steps, thus calling up a new bandwidth marker, for example marker 3, which is 442 Hz, and counter/ the compare circuitry is then/^jaablLo to operate in its normal manner.

When the pitch frequency is very high, i.e., approaching 310 Hz, it is possible to have two bands which have no harmonics lying therein. For this reason, a double pulse arrangement is established on the at least one lead of lines 42 coupled to the NAND-gate 55, and the pulses come in rapid succession to provide successive false compare signals, if necessary. Similarly, the pulses on the input of gate 55 are arranged to allow time for the comparator 50 to respond, if a normal compare is experienced.

Since the digital counter 6'J has only a -bit output with 16 possible word combinations'; the address of the seventeenth marker must be created in some other manner. This input is provided by producing a high-voltage, representing a one, from the input line 47. All the outputs from the digital counter 57 are now ones (1111), and they are applied to the bandwidth 17 gate which produces a zero out The output of the bandwidth 17 gate is then inverted and applied to a" NAND-gate 63, which is similar to gate 55, such that as the sixteenth marker, frequency is reached, a one is applied to one of the three inputs to the NAND-gate 63. When a compare signal again appears on line 47, indicating tihat the harmonic signal on lead 44 equals or exceeds 3330 Hz, a signal representing a one is applied to the second input to NAND-gate 63. The third signal representing a one is applied to the NAND- unit 12 and is timed to assure that the bandwidth 16 address -and bandwidth 16 compare process is complete. When the third signal is applied to the NAND-gate 63, the gate switches to a zero output which in turn sets a flip-flop 64 to produce an output one to the respective diode bank 59, which produces the proper bandwidth 17 comparison signal out of the bank, in the manner previously described. As will be described in the following material, a pulse is applied to the reset terminal of flip-flop 64 by the K-index and synchronization control 40, thus causing the table 70 to recycle.

The table of channel bandwidths 70 cycles through each of the sixteen bands for each l/256th part of one cycle of the basic pitch frequency. In other words, data relating to the pitch frequency and each of its harmonics is generated during each 1/256 part of a cycle of the pitch frequency, thus the above with respect to the general equation (1) and its expansion in equations (2) , (3) , and (4) . The output signal on lead 65 of the envelope update control 60 is coupled to the A^ ^ register 66 and to the envelope update register 30, and by prop erly signaling these units, harmonic amplitude information in the register 30 is related to at least one sine function of the equations (2), (3), and (4).

As is shown in FIG. 1, the output of the comparator 50 is coupled through a lead 47 to the K-index and synchronization control unit 40. The K-index and synchronization control unit 40 operates to produce a bandwidth 17 marker, which indicates the end of the cycle of the 16 bands for 1/256 of a cycle of the pitch frequency and provides a means for synchronizing the operation of the K-counter 80, the K-H accumulator 75, the reset signals on line 43, the output accumulator 85, and the digital-to-analog (D/Λ) converter 86.

Referring to FIG. 10, the K-index and synchronization control 40 includes a first NAND-gate 68 which has 4 input connections. Two of the input connections are coupled to leads 42 from the timing and output control unit 12 while the third lead is coupled to the output of the comparator 50 through a lead 47, and the fourth lead is coupled to the table of channel bandwidths the noninverting output of flip-flop 64 (FIG. 9), i.e., the bandwidth 17 address output. The gate 68 operates in response to high-voltages (ones) on each of its respective inputs to produce a low output (zero). When the bandwidth 17 address is generated in the table of channel bandwidths and the flip-flop .64 (FIG. 9) is set, a high-voltage is generated on line 51 and remains there at least during the processing of the 17th band for the particular cycle in question; therefore, a high appears o one lead of the input of gate 68 during that time. Additionally, high voltages are applied on clock leads 42 coupled to the input of gate 68 at a time corresponding to the completion of the cycle through bandwidth markers 1-17 , thus providing only a limited span of time during which the bandwidth 17 marker can be generated.

The timing described serves to disable the bandwidth 17 marker, except for a preselected time window, to prevent the accidental actuation of the bandwidth 17 marker in response to spurious signals which may appear on the line, thereby improving the reliability of the computations during each cycle.

Finally, the output of the comparator 50 through a lead 47 to the fourth input of (FIG. 10) . After the bandwidth 17 address is generated and a compare signal is generated in response thereto, the output --of comparator 50 goes positive, as previously described, and the fourth high is applied to the gate 68 to cause the output thereof to switch to zero. The output of gate 68 is coupled to flip-flop 67 and sets the flip-flop when the output falls to zero, since the flip-flop 67 has an inverter coupled to its set input. In its set state, the flip-flop 67 has a high on its noninverted output (Q) and a low (zero) on its inverted output (Q) . The noninverted output is coupled to line 52 and to the input of gate 69 and provides the bandwidth 17 marker" signal. The inverted output (Q) provides the bandwidth 17 "not" signal, which is referred to hereinafter, and is coupled to line 43. The bandwidth 17 "not" signal is used to reset various equipment in the synthesizer.

A reset-disable circuit including NAND-gate 87 is coupled between the output of gate 68 and the reset input of flip-flop 67. The gate 87 has four inputs, and a first of the inputs is coupled to the output of gate 68. The remaining three inputs to gate 68 are coupled by line 42 to the timing and output control 12. Thus, while the output of gate 68 is low, at least one of the inputs on gate 87 is low, and the flip-flop 67 cannot be accidentally reset at the wrong time, i.e., when the bandwidth 17 marker is turned "on". When the output of 68 is high, as when one of the clock pulses on line 42 is removed, and the flip-flop 67 is set to produce the bandwidth 17 marker, as previously described, the flip-flop 67 remains set until clock pulses on lines 42 provide the necessary highs on the remaining three lines to cause the output of gate 87 to go low. The low at the output of gate 87 is inverted at the reset input of flip-flop 67, and thus, the bandwidth 17 marker is removed. The timing on lines 42 at the input to gates 68 and 87 are arranged to set the pulse width of a respective bandwidth 17 marker.

The noninverted output of flip-flop 67 is coupled to NAND gate 69, as previously stated, and the output of gate 69 is coupled through an inverter 73 to lead 41. Gate 69 has a second input connection which is coupled to the noninverted output of a flip-flop 71, and the output of gate 69 is coupled to the reset input of flip-flop 71. The frame synchronization signal is coupled from the input means (FIG.l) through lead 16 and through an inverter 74 to a first input connection of NAND-gate 72, and a pitch synchronization signal from the K-counter (FIG. 1) is coupled through lead 49 to a second input of gate 72. The frame synchronization signal is normally low but is inverted by inverter 74, thus, a positive signal is applied to one input of gate 72 at all times, except when the frame sync signal is present on line 16. The pitch sync signal on line 49 is generated in the K-counter 80 and corresponds to the start of a full-cycle of the pitch frequency (K = 0) . When the frame sync signal and the pitch sync signal are both present simultaneously, since the frame sync is inverted, the gate 72 is disabled. When a pulse is produced by the K-counter 80 on line 49 at any time, except when there is a frame sync present on line 16, two positive pulses are produced on the input of NAND-gate 72, and a low appears at the output. This low is coupled to the set gate of flip-flop 71 and is there inverted to cause the flip-flop to set. When the flip-flop 71 is set in this manner, a high is produced on lead 88 which is coupled to the input" of a NAND-gate 69. When the gate 69 has highs on each of its two inputs, as when there is a bandwidth 17 marker, and when the -counter 80 (FIG. 1) steps to any position other than K = 0, the output described, the frame sync pulse (on line 16) causes the amplitude information data to shift from the amplitude buffer-register 22 to the envelope register 30. If a change of frame information is called for, as by a pulse on line 41, at the precise moment that the amplitude information is being transferred from the register 22 to the envelope register 30 and before the transfer lines 25 have settled, erroneous data may be recorded in the envelope register, 'thereby disrupting the operation of further computations by introducing error. Thus, the gate 72 is disabled, as described, to prevent these errors.

The bandwidth 17 marker, on line 52, is coupled to the K-counter 80, the output digital-to-analog converter 86, the scaling multiplier 84, and the accumulator 85. When the output of gate 69 goes low, it is inverted by an inverter 73 to which it is coupled and a positive or high is produced on lead 41 out of the inverter. Additionally, when the output of 69 goes low, the low is coupled through a lead 89 to the reset connection of flip-flop 71 where the signal is inverted to reset the flip-flop, thus removing a high from the input of gate 69. It is how apparent that the pulse produced on line 41 has a duration which corresponds to the response time of the reset circuit of flip-flop 71.

The disable circuitry associated with flip-flop 71 prevents the occurrence of a K = 0 pulse from the K-counter 80 at the same time that a frame synchronization pulse occurs. As previously stated, a pulse on line 41 is coupled to the envelope register 30 to cause the register 30 to load from storage unit 29, and the synchronization pulse thereon causes data to transfer from the frequency storage unit 29 to the adder 35. Note that these operations occur only when K = 0, since, as previously described, a K = 0 pulse is required from the K-counter 80 to enable the generation, in the control unit 40, of the pulse on line 41.

The envelope register 30, FIG. 1, accepts and stores the amplitude data from the amplitude buffer-register 22 upon the receipt of a pulse over line 41 from the K-index and synchronization control unit 40 and is properly a part of the input means 15. Since the pulse on line 41 corresponds to the bandwidth 17 marker, it represents the end of a cycle through the 16 segments of the voice band for the l/256th increment of one cycle of the pitch frequency that is present, thus a new frame of amplitude data is called up and stored in the envelope re st 30 for use with the next full-cycle of the pitch frequency.

Once the amplitude data from a particular frame is stored in the register 30 in response to a pulse on line 41, and a compare signal is generated for each of the 16 bands, the proper amplitude data in register 30 must be synchronized with the respective band to which it relates. Therefore, each time a new bandwidth marker address is called up in the table of channel bandwidths 70, a pulse is extracted from the input of the counter 57 in the envelope update control 60 (FIG. 9) on lead 65, and this pulse strobes the envelope, register 30 to cause the amplitude data at the output of the register to change to the next word of amplitude data within the frame in order of time. The circuitry in the envelope register 30 is similar to that of register 22 in that it includes a group culation of the amplitude words of each frame.

T^r> nodate signal oh line 65 from the envelope update control^is coupled to the A(H.£) register 66, also, and when an envelope update pulse is generated on line 65, the amplitude data on leads 76 at the output of the envelope register in order of time instead of the first. In this manner, the envelope register 30 shifts through each successive word of amplitude data in response to a shift signal from the envelope update 60. ' The A/TT register 66 stores the 3-bit words of data on (Η· I) line 76 in response to a pulse on line 65. Clock pulses on line 42 are applied to the register 66 to provide a time- window when storage can occur, thus preventing the erroneous storage of data in response to transients. Similar techniques and circuitry for providing the time-window have already been described. The output of the A (JJ. fj register 66 is coupled over leads 81 to the table of amplitude modulated trig func1- tions 90.

C. Means for Computing Preliminar Sine Data.

The K-counter 80 is a counter similar to the counter 57 (FIG. 9) previously described,' ahd is a commercially available unit The basic difference between the counter 80 and' counter/ the t9«iwd#^«- 57 is the counting range or magnitude of the output word which is produced. The -counter 80 has a 8-bit.,^ > output and can therefore count to a higher level than the counter 57 which has only a 4-bit output. Each bandwidth 17 marker pulse on line 52 strobes the K-counter 80 causing it to step. The K-counter 80 is designed to step successively from K = 0 through K = 255 in response to the successive pulses on line 52. When the K-counter 80 reaches the K = 0 step, it generates a pulse on line 49 that signals the start of a new cycle of the pitch frequency. The binary output of K-counter 80 is arranged such that it is all zeros (lows) when K =.0. Eight parallel-connected logic-gates are coupled respectively to respective ones of the output bit-positions of the K-counter 80, and' each gate operates to invert the signal applied to its input, whether it is high or Low. As will be recognized by one skilled in the art, the gates can be arranged such that wh n the ouL uL of each gate is high, and only in this case, a high output is produced. This case occurs only when the K-counter recycles in response to a bandwidth 17 marker, such that its output is all zeros. This high output is applied to lead 49 to signal K = 0 to the respective units previously described.

The adder 77 and K-H accumulator 75 are similar in construction and operation to the adder-acumulator combination 35, 36. The output of the K-counter 80 is coupled to the input of adder 77, and the adder 77 is coupled to the accumulator 75 in substantially the same manner that adder 35 is coupled to accumulator 36. Each time the K-H accumulator 75 is clocked by a pulse from the timing and output control 12 , the binary number at the input to the adder 77 adds to itself. Each time a bandwidth 17 marker is generated on line 52, the K-counter steps, placing a new "binary number representing a number from K = 0 to K = 255 at the input to the adder, and the bandwidth 17 "not" signal on line 1+3 resets the K-H accumulator 75 at the appropriate time, such that the computation begins again. The output of the K-H accumulator 75 is; coupled over eight parallel lines, through adder 78 , to the input of the table of amplitude modulated trig functions 90. The adder 78, as will be described hereinafter, operates to add in the unvoiced data to improve the intelligibility of the voice signal produced.

At the particular moment when K = 0, the binary output o the K-counter 80 is all zeros,, and the adder-accumulator 77-75 correspondingly also produces an all zero output. Since thiB is the case, the time span between K = 0 and K = 1 is used to accomplish data transfer into the envelope register 30 and into the frequency storage unit 29» and time is provided to allow, the circuit transients to settle-out before the computation for the next cycle begins.

Referring now to Fig. 3i as the K-counter 80 is pulsed and its output switches to a binary word equal to 1 , the adder-accumulator 77-75 begins to operate and the output of the accumulator 75 begins; to increase at a gradual rate.

Further, as the K-counter 80 (Fig. 1) is pulsed by a bandwidth 17 marker on line 52 at any one of the K = 2 to K = 255 steps, the output of the adder-accumulator 77-75 begine to produce increasingly larger digital words. Since the timing pulse applied on lead U2, coupled to the K-H accumulator 75» occurs at a constant rate, the output of th K-H accumulator increases at a constant rate.

Assuming that the binary output of the K-H accumulator 75 were applied to an analog-to-digital converter and plotted, the plotted curve would look like curve 91 of FIG. 3. As has been described, the output of the accumulator 75 does not increase, but remains at zero during the time interval from - = 0 to K = 1.

It is apparent from the curve 91 that the output of the K-H accumulator 75 begins to increase from zero with each bandwidth 17 marker strobe. This is true because the accumulator 75 is reset by the bandwidth 17 "not" pulse which is coupled to the K-H accumulator by lead 43. The slope of the curve 91 during any one bandwidth 17 period is determined by the value of the word at the output of the K-counter 80 (FIG. 1). Thus, when the output of the K-counter 80 is a binary word equal to one, as at the time K = 1, then the curve has a certain slope, as in curve 91a. When the output of the K-counter 80 increases in response to being strobed by the next bandwidth 17 marker, slope during this bandwidth 17 period is steeper than that during the first period, for instance see curve 91b. When the K-counter 80 output word is equal to 2, then the slope increases twice as fast, where the output word is equal to 3, as at K = 3, the slope is three times as steep and so on for successive ones of the 255 counts before the counter recycles. Since the output of the accumulator 75 includes only 8 bits, the accumulator output increases in steps and the maximum number of successively increasing words which can be produced at the output is 54 (at 74 Hz) , thus the accumulator output builds up for 54 steps, unless cutoff by the next bandwidth 17 marker. When the output of the accumulator 75 reaches the maximum number of steps, it recycles to zero and begins to build up again, as in curve 91b, 91c, etc., of FIG. 3.

It is now apparent, in view to FIG. 1, that the bandwidth 17 markers occur at a tf^n^ r'a^fr-rate which is proportional to the rate at which comparisons are made at the magnitude comparator 50 of PIG. 1. · Thus , the higher the pitch frequency associated with a frame of data being processed, the shorter will be the time the output of accumulator 75 will build up. Additionally, when the pitch frequency is 74 Hz, the accumulator output builds up for 54 steps, but at a pitch frequency of 310 Hz, the output will build up for only 11 steps, and for pitch frequencies lying between 74 and 310-Hz, the output of accumulator 75 will build up a number of discrete steps between 54 and 11. The number of steps in the marker band is in an inverse proportion to the value of the word at the output of the K-counter. Therefore, as the K-counter 80 is strobed by successive bandwidth 17 marker pulses, the output of the accumulator 75 builds up for successive periods in a manner similar to the analog representation . of the output provided in curve 91 of FIG. 3. The output of the K-H accumulator 75 is produced, in the manner described, simply as a mechanical means for producing sine information from the table of amplitude modulated trig functions 90.

D. Means for Computing Α(.Η·ί) .£Sln 2ΤΓ(Η·:Γ)3, Considering now FIG. 11, the output of the K-H accumu-lator 75 is fed through the 8-bit adder 78 and lead 79 to the table of amplitude modulated trig functions 90. The output of the accumulator 75 is in digital format, in 8-bit words.

Interiorally of the table of amplitude modulated trig functions 90, the data on line 79 is fed, with the exception of the most significant bit, to a first inverter-adder 111. Con sidering the 8-bit word on line 79, the two most significant \ bits of the word represent quadrant information, i.e., 00 for the first quadrant, 01 for the second quadrant, 10 for the thir,d quadrant, and 11 for the fourth quadrant. The most significant bit is fed through line 119 to the second inverter-adder 115, and its use will be discussed in association with respect to the second inverter-adder operation. The second most significant bit is fed directly to the first inverter-adder 111 along with the remaining 6-bits of data on line 79. The most significant bit of the 7-bit word fed to the inverter adder 111 provides an indication to the inverter-adder as to when inversion is required. For instance, when the most sig- \ nificant bit is 0, i.e., information goes through the inverter-adderii÷6!5' without inversion, and when the most significant bit of the 7-bit word is a 1, then the inverter-adder inverts the information and adds one before passing the information on to the first holding register 112. The inversion and addition is accomplished in unit 112 by circuitry incorporati ητ well known techni ue . --complement/ oomplement commonly known as the 21 s fee*-*-1-'— . The 2 ' s ^^-—- ft*7 is , fully explained at page 367 of the text Digital Computer by . McGraw-Hlllj Yauhan Chu, published byjMcGroy-n lύ Publishing Co. of New York. The most significant bit of the 7-bit word applied to the input of the inverter-adder 111 is dropped from the data stream in the inverter-adder, and the six remaining bits of information are passed to the first holding register 112.

Curve 96 of FIG. ' 3 provides an analog representation of the digital output of the inverter-adder 111. As the seventh, or second most significant bit of the 8-bit word on line 79 changes to a 1, the next data input to inverter-adder 111 is inverted and a one is added, and the curve 96, between respective bandwidth 17 markers, becomes a triangularly-shaped, oscillating wave (if plotted as an analog) ,· and the "number of steps in each rising or falling segment of the oscillating wave depends on the value of the word at the output of the. K-counter 80 of FIG. 1 The clock pulses on line 42 are coupled to gate 116 which is in turn coupled to the first holding register 112. The register 112 is similar in construction and operation to other registers described herein, for instance, the pitch-frequency buffer-register 26, and therefore includes a series of parallel connected flip-flops. The output of gate 116 is coupled to the clock input connection of each respective flip-flop in the register 112. When a respective flip-flop is strobed with a clock pulse, the 6-bit digital word appear-ing on the inputs of the parallel connected flip-flops is set Oil tilt; ilOiixxiVt; Led Output Of the flip flop.

The output of the first holding register 112 is coupled to the read-only memory 113, which includes a total of 512 separate recognition gates, which for the embodiment described, are manufactured in two integrated circuit chips, with each respective chip including 256 of the gates. Each gate has at least 9 inputs. The six lines out of the holding register 112 are coupled in parallel to 6 of the inputs of each of the recognition gates. The amplitude data in the ^ register (FIG. 1) is coupled over lead 81 (3-bits) through the second holding register 114 to the read-only memory 113 and specifically is parallel to the remaining 3 input leads of each of ,the recognition gates. Each recognition gate has a plurality of parallel output lines, and upon the applica-tion by a particular combination of amplitude data and preliminary sine data, the recognition gate produces an o t ut digital word on the output parallel lines which is equal to the computation of a specific point on the voice curve to be produced, in accordance with the equation (1) set forth at page 10 herein. The output of the respective recognition gate is therefore equal to the sine of an angle lying (at this point in time) between 0 and 90°, times the amplitude information relating to one of the sixteen bands of voice frequencies previously described.

Each 1.03 microseconds, the preliminary sine information changes at the output cf the first holding register 112. If the curve 96 of FIG. 3 is taken to represent a pitch frequency 74 Hz, a portion of the curve 96, for instance 96a, builds up in 54 steps, as previously' described. The word corresponding to each step also corresponds to an even multiple of the output of the K-counter 80. Since there will be 54 steps in the curve 96a, a particular point on the curve corresponds to a particular harmonic of the pitch frequency of 74 Hz. The digital word corresponding to a step represents the sine of that harmonic, and when during a articular bandwidth 17 cycle, there is an amplitude word 66 corresponding to this harmonic, then a particular recogni-tion gate is turned on, and the value of the output word produced equals the sine of the angle represented by the harmonic point times the amplitude data.

Each of the recognition gates described above is similar to the detect-only gates described with respect to the table of channel bandwidths 70, and each differs only in the number of input and output leads. The word produced at the output of the diode bank equals the sine of the angle related to the harmonic times the amplitude data from the amplitude register 66 The second holding register 114 is substantially the same in operation and design as the register 112, but include 'three flip-flops. The timing and output control 12 of FIG. 1 is coupled to the second holding register, through leads 42 and gate 117.

In FIG. 11, the clock pulses provided on line 42 through gate 117 to the second holding register 114 are arranged that the gate 117 provides a pulse to the second holding register to enable it to pass the information in the register to the read-only memory 113 at a time prior to the time that the pulses on line 42 through gate 116 provide a pulse to the first holding register 112 to enable the first holding register 112 to pass the preliminary sine information to the read-only memory 113. Each of the nine parallel lines, including six lines from the first holding register 112 and the three lines from the input of each of the respective recognition gates Of the readonly memory 113. It will be apparent to those skilled in the art that the output of the A(H.f) register 66 of FIG. 1 will produce, since its output consists of only a 3~bit word, only eight possible combinations of amplitude data which are coupled to the table of amplitude modulated trig functions 90 of FIG. 1. Similarly, the sine information out of the register 112 and into the table of amplitude modulated trig functions 90 con-sists- of only 64 possible combinations. Each recognition gate of the read-only memory 113 recognizes a respective one of the eight possible words relating to amplitude information and only 1 of the 64 possible words relating to sine information, and in response to recognition of these two words, produces an output word which is related to a particular .frequency, i.e., either the fundamental or a particular har- monic and has an amplitude which is determined by the amplitude information by the A register. The output of each the harmonic^at tnat time . j: there is no related harmonic and amplitude information, the output of the read-only memory 113 will be zero at that time, thus that harmonic is absent time period, where corresponding amplitude data is available.

Now consider FIG. 4. At a particular frequency F where F is the pitch frequency, curve 120 shows the envelope response of 256 bandwidth 17 markers for two cycles of the basic- frequency F . This curve (120) corresponds to the curve 93 of FIG. 3 and relates to only one frequency in the band. At the output of the read-only memory 113, the respective outputs 121 of each respective recognition gate will be only positive in direction. Therefore, the output of the read-only memory 113, in FIG. 11, is coupled to the input of a second inverter-adder 115 which is similar to the firs* inverter-adder · The most significant bit of the 8-bit word out of the 8-bit adder 78 and coupled to the input of the table of amplitude modulated trig functions 90 is coupled through lead 19 to the input of the second inverter-adder 1 5· As previously described, this most significant bit on lead 119 is a portion of the quadrant data made up of the two most significant bits of the data on lead 79· When the most significant bit on lead 119 is a zero, this indicates that the half cycle presently coupled to the second inverter-adder 115 from the output of the read-only memory 113 is not to be inverted. Similarly, a one appearing on lead 119 and coupled to the second inverter-adder 115 would mean that the one-half cycle presently appearing at the input of the second inverter-adder 1 5 is to be inverted. As with the; first inverter-adder 11, the inversion is; accomplished through the use of a 2fs complement circuitry of the type previously described. The output of the second inverter-adder 115» on output leads 82, is; a series of digital words representing points on a wave whose envelope is; plotted in Pig. h for only one harmonic ( curve 122) . Curves 123 and 12k of Fig. 2+ illustrate the envelop of a similarly plotted wave 123 of a basic frequency an a simularly plotted wave 12i+ of a harmonic thereof. At all times, except when there is a 0 on the output of the first orj holding register 112 of Pig. 11 the output of the second holding register l†i+ of Pig. 11, there is; an output from the read-only memory 113· Ξ. Means fo Computing T The output of the table of amplitude modulated trig functions 90 is coupled over leads 82 to; an adder-accumulator 83- adder-accumulator previously described, i.e., adder-accumulator 35-36. The accumulator 85 is clocked by a clock pulse on lead 42 each 1.03 microseconds, such that each time a new word, relating to a harmonic, is produced by the table 90, the accumulator cycles. The accumulator 85 is reset by each bandwidth 17 marker. The adder 83, however, is not reset, as was the adder 35, and the output of the adder-accumulator 83-85 continues to build up in response to every output of the table 90. The output of the accumulator 85 is a digital word (10-bits) representing the summation of the words output from the table 90 during an instant of time, i.e., the time span between the respective bandwidth 17 markers.

The output of the accumulator 85 is coupled by 10 parallel leads to the scaling multiplier 84. If a pitch frequency of 310 Hz is being processed, eleven words are added in the accumu ~~ . r _ -(H.f) — corresponding to each of the harmonics. Similarly, if a pitch frequency of 74 Hz is being processed, 54 words could be added in the accumulator for one bandwidth 17 period. Thus,, it is apparent that the amplitude of the word transferred to the digital-to-analog converter 86 must be scaled to prevent an unbalance between the sound at various instants of time.

The scaling multiplier 84 accomplishes the required equalization. The scaler 84 includes a counter similar to the counter described with respect to the envelope update control unit 60. The counter is coupled to a 1.03 microsecond clock pulse from the timing and output control unit 12 over lead 42. This clock pulse effectively counts the number of harmonics included in the output of the accumulator 85, since the computation of a word relating to each harmonic word, from the accumulator 85, is then divided by the output of the counter to equalize the band. Since both the divisor and dividend are digital words, the division can be accomplished digitally by any ' one of several well known techniques.

F. Output Means.

When the equalization process is completed, the output of the scaling multiplier 84 is a digital word which represents a point on the curve which corresponds to the speech to be synthesized, thus, the output of the multiplier '84 is coupled to a standard digital-to-analog converter 86, and the converter produces an analog voltage output which has an amplitude corresponding to the magnitude of the digital word produced. The bandwidth 17 marker on line 52 is coupled respectively to the accumulator 85, the multiplier 84, and the digital-to-analog converter 86 to reset each unit upon the application of a bandwidth 17 pulse. It follows that a new poin i o i d to the di gital -to-anal og converter 86 corresponding to each bandwidth 17 pulse. The analog output of the converter 86 is a step-voltage function, however, the timing of each step is short enough that the steps in the curve are not perceptible to the ear, and when the analog output of the converter 86 is coupled to a loudspeaker or the like, speech is effectively synthesized from the digital description of the original sound.

G. Means for Introducing Unvoiced Sounds.

It has previously been stated that when unvoiced sound has been analyzed, the frame of data at the input to the synthesizer 10 will include all zeros for the pitch frequency data word. The amplitude data of the unvoiced frame will accurately relate to the amplitude of the unvoiced sound in the respective bands of the original voice spectrum. unvoiced detector 33. The nine parallel lines 32 out of the , frequency data conversion unit 28 are coupled respectively into one of nine paralle'l diode-transistor-logic (DTL) gates in the unvoiced detector 33. The DTL is well known in the electronics art and it is also! icf-ew r.hat one characteristic of parallel-connected DTL's is that when all zeros (lows) are applied to the respective inputs and the outputs are coupled together, the output signal produced is a one (high) . Thus, when unvoiced sound is represented by a frame of data, in register 29 which sets the flip-flop to produce an output word (from register 29) representing the pitch frequency of 128 Hz. This produces the result, in the frequency storage 29/ of a voiced sound having a pitch frequency of 128 Hz.

This particular frequency is chosen because it will provide at least one harmonic in each of the 16 bands of the voice-frequency spectrum. The 128 Hz frequency is used as a carrier which is modulated in a manner described in the following material to produce a balanced noise spectrum in the sound to make the sound appear more natural and to thereby improve the intelligibility and quality of the sound reproduced. on lead 125 from the unvo ced detector 33, the 1 8 Hz bas c pitch frequency establishes through the remainder of the circuitry, and particularly from the K-index and synchroni-^ zation control unit 40, a bandwidth 17 marker that occurs •at a particular repetition rate. This bandwidth 17 marker is then 'coupled to the noise generator 127. by lead 52, and is coupled to the K-counter 80, as previously described. With this particular bandwidth 17 repetition rate applied to the K-counter 80, the K-counter begins to step, thereby causing the adder-accumulator 77, 75 to produce an output which increases through some 29 steps (corresponding to the number of harmonics of 128 Hz) .

Refer now to FIG. 13. Inside the noise generator 127;, the bandwidth 17 marker on lead 52 is coupled to a counter 128 which, in the embodiment described,' functions to produce an output pulse in response to each 25th bandwidth 17 marker.

The output of the counter 128 is coupled to a pseudo-random generator 129. The pseudo-random generator is a device well known to those skilled in the art and is described fully in a text entitled Digital Communications with Space Applications by Golomb, Baumert, Easterling, Stiffer and Viterbi published varies in response to a pulse from the counter 128 in a random manner over a fixed period of time. For instance, the output of the pseudo-random generator may vary at random for 1000 strobes of the output of counter 128, and then the cycle will repeat in the same random manner for the next 1000 cycles etc. The repetition of the pseudo-random generator 129 occurs at approximately 25,000 counts of the K-counter, and therefore is completely random for the purposes of. this noise generator.

The output of the pseudo-random generator 129 is coupled to the input of the second pseudo-random generator 131 through logic gates 130. Each of the parallel bits of the output of the pseudo-random generator 129 is coupled through a respective logic gate 130, to the leads coupled to the pseudo-random generator 131. ' The bandwidth 17 marker signal on lead 52 is coupled directly to each of the respective logic gates 130.

Each bandwidth 17 marker on lead 52 causes the respective logic gate to set, thereby placing the 8-bit word at the output of pseudo-random generator 129 at the input of pseudo.- random generator 131. it is apparent now that the output of the pseudo-random generator 129 changes at a time corresponding to each 25th bandwidth 17 marker, and the 8-bit word at the output of the generator 129 is transferred through the logic gates 130 upon the occurrence of each bandwidth 17 itid J- « nc j ^ u ^ a* u.» wm s__.,i.s_ struction to the pseudo-random generator 129, but each of the generators 129, 131 includes parallel input flip-flops, and the clock input of the input flip-flops of generator 131 are coupled to the bandwidth 17 marker lead 52, thus a band- . width 17 marker pulse on lead 52 serves to preset the data output from the pseudo-random generator 129 at the input of the pseudo-random generator 131. Also, timing pulses from coupled to the applied to the pseudo-random generator from the envelope update each 1.03 microseconds. The envelope update control signal, as was previously described, occurs each time a comparison is made at the magnitude comparator 50. Thus, the pseudo-random generator 131 advances 16 times during the time span between bandwidth 17 markers. This means that during the bandwidth 17 marker period, only 16 of the random words produced by pseudo-random generator 131 will appear at its output. The envelope update signal on lead 65 is also coupled to the serial register recirculating memory 133. The output of the pseudo-random generator 131 is coupled to the input of a 10-bit adder 132.

Each time the envelope update pulse on line 65 strobes the generator 131, the word on the output of the generator 129 is placed on the input of the adder 132.

The output of the generator 131 is a 5-bit word, including 4 -bits of amplitude modulation data and 1-bit of sign data, v/ith the sign data included as the most significant bit. The five bits are coupled to the five least significant bit positions of the 10-bit adder 132. The 10-bit adder 132 provides ample expansion oom Γυ auuiiiy tu he WOJLU plctueu at the input of the adder.

As the first word is strobed into the adder 132 by the envelope update pulse on lead 65, the word is set in the serial register 133. The register 133 includes 16 banks of ten parallel-connected flip-flops each. The clock input of each flip-flop is coupled to the envelope update lead 65, and when the first envelope update pulse strobes the first bank of flip-flops, the word on the output of generator 129 (and 131) is set in that bank, since generator 131 is slaved to the output of generator 129 on the first count.- Upon the second strobe by an envelope update pulse, the word in the first bank transfers to the second bank, and the first random word out of the generator 131 is set in the first bank. The output of the memory 133, i.e., the last bank, is coupled to the input of the adder 132 , but nothing is added until the sixteenth strobe pulse on lead 65. Just prior to the occurrence of the 16th strobe- pulse, 16 random words are stored in the memory 133, one in each bank. Upon . the 16th pulse, the first word adds to the output of the generator 131. Since a bandwidth 17 pulse on line 52 occurs shortly after the occurrence of the 16th envelope update pulse, it is coupled to the reset inputs of the generator 131 and resets the generator such that the random generator 131 starts over on the same random cycle, thus each of the words recycled to the input of the adder 132 is added to itself. The output of the random generator 129, 131 can be positive or negative, thus the recirculated signals are added algebraically. Upon the occurrence of each 25th bandwidth 17 marker, the output of generator 129 changes, and a new reference is applied to the input of generator 131, but the output of the niemox y 133 is not reset to zero at this time, therefore a completely new random pattern is established.

The output of the memory 133 is coupled to the input of the 8-bit adder 78 and operates thus to jitter, in response to the random output of the memory, the sine data being generated for use in the table of channel bandwidths 90.

The jitter thus produced shows up in the output of the synthesizer 10 as /whi e/ noise, but the noise is carefully controlled, as described, to equalize the amount of noise associated with each frequency and with each respective piece of amplitude information. No particular harmonic in each band is unduly enhanced. The result which follows is that the intelligibility and quality of the speech produced is substantially enhanced by adding back to the voice signals otherwise produced a synthesized unvoiced sound which very closely approximates the original unvoiced speech.

Claims (2)

1. 35513/2/3 V Claims : 1. A synthesizer for converting consecutive frames of digital words into analog signals for producing a sound, each frame including bits relating to the fundamental frequency or pitch of the sound at a certain instant and to the amplitudes of a plurality of its harmonics at that instant, the synthesizer comprising:- (a) means for storing bits representing the fundamental frequency and its amplitude, (b) means for providing and storing bits representing the frequency of the harmonics, (c) means for storing bits representing the amplitudes of the harmonics, (d) means for providing bits representing respective bandwidth markers, each marker characterising a terminal frequency of one of a series of predetermined consecutive bands in said sound; (e) means for comparing the content of (b) with the bandwidth marker bits to provide bits representing the harmonic frequencies in the selected bands and (f) means responsive to (a) and to associate the content of (c) with the bits representing the harmonic frequencies in the selected bands for providing and storing a train of bits for the purpose of formulating a predetermined number of terms in a harmonic series, which terms include the product of the fundamental frequency and its amplitude and the product of the harmonic frequencies- in selected bands and their respective amplitudes at said instant , 35513/2/3 (g) means to accumulate the bits in the train to sum the series, and (h) means to generate an analog signal corresponding wit the sum of said series,which analog signal represents an instantaneous: value of said sound, whereby said sound is reproduced by converting the consecutive frames into the analog signals.

2. A synthesizer according to claim 1 in which (b) comprises means for multiplying the content of (a) to provide bit3 representing multiples of the fundamental frequency corresponding to the harmonic frequencies. 3· A synthesizer according to claim 1 or 2 including means to provide bits representing instantaneous values of sine functions for the purpose of formulating the frequency portion of each term in the series. k» A synthesizer according to claim 3 in which the bits representing each term of the series represent amplitude modulated sine functions. 5. A synthesizer according to any one of the preceding claims including:- (i) means responsive (a) for storing bits representing the presence of unvoiced speech; ( j) means for providing bits representing a fundamental speech frequency; (k) means for providing bits representing noise; (l) means, responsive to (e) and (k) for providing bits representing modulation of the fundamental speech frequency with said noise; and (m) means for supplying the bits produced by (l) to (c) whereby the analog signals include those representing the unvoiced speech. 6. A synthesizer according to claim 5 in which (k) comprises a pseudo-random noise generator. 7· A synthesizer according to claim 5 or 6 including a pair of logically connected pseudo-random noise generators respectively controlled by bits derived from (e) and means for providing bits representing synchronous timing signals, the output of one of the pseudo-random noise generators being connected to a recirculating memory controlled by (i) for providing bits representing controlled amounts of noise. 8. A synthesizer according to claim 8 in which ( j ) includes means for providing bits representing harmonics of the fundamental speech frequency in a selected bandwidth and means for associating the bits representing the fundamental and harmonic frequencies with the bits representing the controlled amount of noise. 9. A synthesizer according to any one of the preceding claims including means to modify the output of (g) effectively to change th frequency bandwidth of the output sound. 10. A synthesizer for converting frames of digital words into analog signals for producing a sound, each frame including bits relating to the fundamental frequency or pitch of the sound at a certain instant and to the amplitudes of a plurality of its harmonics at that instant , which synthesizer is substantially as herein described with reference to Figure 1 of the accompanying drawings.