IL310932A - Optimal bit apportionments for digital functions subject to soft errors - Google Patents

Optimal bit apportionments for digital functions subject to soft errors

Info

Publication number
IL310932A
IL310932A IL310932A IL31093224A IL310932A IL 310932 A IL310932 A IL 310932A IL 310932 A IL310932 A IL 310932A IL 31093224 A IL31093224 A IL 31093224A IL 310932 A IL310932 A IL 310932A
Authority
IL
Israel
Prior art keywords
bit
data value
bits
copies
subset
Prior art date
Application number
IL310932A
Other languages
Hebrew (he)
Other versions
IL310932B1 (en
Inventor
Steven J Manson
Original Assignee
Raytheon Co
Steven J Manson
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US17/464,827 external-priority patent/US11586511B1/en
Priority claimed from US17/464,938 external-priority patent/US11755431B2/en
Application filed by Raytheon Co, Steven J Manson filed Critical Raytheon Co
Publication of IL310932A publication Critical patent/IL310932A/en
Publication of IL310932B1 publication Critical patent/IL310932B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
    • G06F11/167—Error detection by comparing the memory output
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/183—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/186—Passive fault masking when reading multiple copies of the same data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/187—Voting techniques
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/12—Computing arrangements based on biological models using genetic models
    • G06N3/126—Evolutionary algorithms, e.g. genetic algorithms or genetic programming

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biophysics (AREA)
  • Bioinformatics & Cheminformatics (AREA)
  • Bioinformatics & Computational Biology (AREA)
  • Evolutionary Biology (AREA)
  • Physiology (AREA)
  • Genetics & Genomics (AREA)
  • Artificial Intelligence (AREA)
  • Biomedical Technology (AREA)
  • Computational Linguistics (AREA)
  • Data Mining & Analysis (AREA)
  • Evolutionary Computation (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Claims (20)

1.CLAIMS 1. A method comprising: storing one or more bit copies of each of at least some bits of a data value in at least one memory, wherein a number of bit copies of each bit of the data value is based on a specified apportionment, and wherein different bits have different numbers of bit copies; retrieving the bit copies of the at least some of the bits of the data value from the at least one memory; in response to determining that a specified bit of the data value has multiple retrieved bit copies that differ from one another, estimating a bit value for the specified bit using the multiple retrieved bit copies of the specified bit; and outputting or using the data value having the estimated bit value for the specified bit.
2. The method of claim 1, wherein the specified apportionment defines (i) multiple subsets of the bits of the data value and (ii) for each subset, a number of bit copies to be stored for each bit of the subset.
3. The method of claim 2, wherein the specified apportionment indicates that: each bit in a first subset of the bits of the data value is associated with a first number of bit copies to be stored; each bit in a second subset of the bits of the data value is associated with a second number of bit copies to be stored; and each bit in a third subset of the bits of the data value is associated with a third number of bit copies to be stored.
4. The method of claim 3, wherein: the first subset of the bits of the data value comprises a specified number of most significant bits of the data value; the second subset of the bits of the data value comprises a specified number of least significant bits of the data value; and the third subset of the bits of the data value comprises a specified number of bits between the most significant bits and the least significant bits of the data value.
5. The method of claim 4, wherein: the first subset of the bits of the data value includes seventeen most significant bits of the data value; the second subset of the bits of the data value includes four least significant bits of the data value; and the third subset of the bits of the data value includes eleven bits between the most significant bits and the least significant bits of the data value.
6. The method of claim 5, wherein: the first number of bit copies to be stored equals five; the second number of bit copies to be stored equals zero; and the third number of bit copies to be stored equals one.
7. The method of claim 1, wherein a total number of bit copies of the data value is equal to or less than three times a total number of bits in the data value.
8. The method of claim 1, wherein: the at least one memory comprises a radiation-hardened memory and a non-radiation-hardened memory; and at least one bit of the data value has one or more bit copies stored in the radiation-hardened memory and one or more bit copies stored in the non-radiation-hardened memory.
9. An apparatus comprising: at least one memory configured to store one or more bit copies of each of at least some bits of a data value, wherein a number of bit copies of each bit of the data value is based on a specified apportionment, and wherein different bits have different numbers of bit copies; and at least one processing device configured to: retrieve the bit copies of the at least some of the bits of the data value from the at least one memory; in response to determining that a specified bit of the data value has multiple retrieved bit copies that differ from one another, estimate a bit value for the specified bit using the multiple retrieved bit copies of the specified bit; and output or use the data value having the estimated bit value for the specified bit.
10. The apparatus of claim 9, wherein the specified apportionment defines (i) multiple subsets of the bits of the data value and (ii) for each subset, a number of bit copies to be stored for each bit of the subset.
11. The apparatus of claim 10, wherein the specified apportionment indicates that: each bit in a first subset of the bits of the data value is associated with a first number of bit copies to be stored; each bit in a second subset of the bits of the data value is associated with a second number of bit copies to be stored; and each bit in a third subset of the bits of the data value is associated with a third number of bit copies to be stored.
12. The apparatus of claim 11, wherein: the first subset of the bits of the data value comprises a specified number of most significant bits of the data value; the second subset of the bits of the data value comprises a specified number of least significant bits of the data value; and the third subset of the bits of the data value comprises a specified number of bits between the most significant bits and the least significant bits of the data value.
13. The apparatus of claim 12, wherein: the first subset of the bits of the data value includes seventeen most significant bits of the data value; the second subset of the bits of the data value includes four least significant bits of the data value; and the third subset of the bits of the data value includes eleven bits between the most significant bits and the least significant bits of the data value.
14. The apparatus of claim 13, wherein: the first number of bit copies to be stored equals five; the second number of bit copies to be stored equals zero; and the third number of bit copies to be stored equals one.
15. The apparatus of claim 9, wherein a total number of bit copies of the data value is equal to or less than three times a total number of bits in the data value.
16. The apparatus of claim 9, wherein: the at least one memory comprises a radiation-hardened memory and a non-radiation-hardened memory; and the at least one processing device is configured to store one or more bit copies of at least one bit of the data value in the radiation-hardened memory and one or more bit copies of the at least one bit of the data value in the non-radiation-hardened memory.
17. A non-transitory computer readable medium containing instructions that when executed cause at least one processor to: store one or more bit copies of each of at least some bits of a data value in at least one memory, wherein a number of bit copies of each bit of the data value is based on a specified apportionment, and wherein different bits have different numbers of bit copies; retrieve the bit copies of the at least some of the bits of the data value from the at least one memory; in response to determining that a specified bit of the data value has multiple retrieved bit copies that differ from one another, estimate a bit value for the specified bit using the multiple retrieved bit copies of the specified bit; and output or use the data value having the estimated bit value for the specified bit.
18. The non-transitory computer readable medium of claim 17, wherein the specified apportionment defines (i) multiple subsets of the bits of the data value and (ii) for each subset, a number of bit copies to be stored for each bit of the subset.
19. The non-transitory computer readable medium of claim 18, wherein the specified apportionment indicates that: each bit in a first subset of the bits of the data value is associated with a first number of bit copies to be stored; each bit in a second subset of the bits of the data value is associated with a second number of bit copies to be stored; and each bit in a third subset of the bits of the data value is associated with a third number of bit copies to be stored.
20. The non-transitory computer readable medium of claim 19, wherein: the first subset of the bits of the data value comprises a specified number of most significant bits of the data value; the second subset of the bits of the data value comprises a specified number of least significant bits of the data value; and the third subset of the bits of the data value comprises a specified number of bits between the most significant bits and the least significant bits of the data value.
IL310932A 2021-09-02 2022-06-15 Optimal bit apportionments for digital functions subject to soft errors IL310932B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/464,827 US11586511B1 (en) 2021-09-02 2021-09-02 Optimal bit apportionments for digital functions subject to soft errors
US17/464,938 US11755431B2 (en) 2021-09-02 2021-09-02 Identification of optimal bit apportionments for digital functions subject to soft errors
PCT/US2022/033661 WO2023033898A1 (en) 2021-09-02 2022-06-15 Optimal bit apportionments for digital functions subject to soft errors

Publications (2)

Publication Number Publication Date
IL310932A true IL310932A (en) 2024-04-01
IL310932B1 IL310932B1 (en) 2024-08-01

Family

ID=82547357

Family Applications (1)

Application Number Title Priority Date Filing Date
IL310932A IL310932B1 (en) 2021-09-02 2022-06-15 Optimal bit apportionments for digital functions subject to soft errors

Country Status (3)

Country Link
EP (1) EP4396683A1 (en)
IL (1) IL310932B1 (en)
WO (1) WO2023033898A1 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013078439A2 (en) * 2011-11-22 2013-05-30 Silicon Space Technology Corporation Memory circuit incorporating radiation hardened memory scrub engine
US10884850B2 (en) * 2018-07-24 2021-01-05 Arm Limited Fault tolerant memory system

Also Published As

Publication number Publication date
IL310932B1 (en) 2024-08-01
EP4396683A1 (en) 2024-07-10
WO2023033898A1 (en) 2023-03-09

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