IL258971A - Methods to store dynamic layer content inside a design file - Google Patents

Description

Ur l0 WO 2017/091676 PCT/US2016/063506 ll:/lE'l"HOE}S TO STORE l}Yl“ilAl‘ldl(‘. LAYER CON'l"ENT El“ilSlDE A DESlGl\l FILE Cross~Rel’ereiitte to Related Applications {G991} liled on February l l, 2.0l 6 and Patent Application No. 6342./Cl-lE/’20l 5, liled on November This application claims priority to U Provisional Application No. 62/294.2373, 26, 2Ul 5, both pending, the disclosures of which are incorporated herein by reference.

Field of the Disclosure {GW2} The present disclosure relates to chip design and defect detection.

Background of the Disclosure {GW3} such as electronic design automation (EDA), computer aided design (CAD), and other IC design An integrated circuit (IC) design may he developed using a niethod or systeni software. Such methods and systeins may he used to generate a. circuit pattern database front the IC design. The circuit pattern database includes data representing a plurality of layouts for various layers of the EC. Data in the circuit pattern datahase may he used to determine layouts for a plurality ofreticles. A layout of a reticle generally includes a plurality of polygons that define features in a pattern on the reticle. Each reticle is used to fa.hricate one of the various layers of the lC. The layers of the lC niay include, for example, ajunction pattern in a seiniconductor substrate, a gate dielectric pattern, a gate electrocle pattern, a contact pattern in an interleyel dielectric, and an interconnect pattern on a rnetallization layer.

{GOG4} (layout) of an hi and data derived from the physical design through complex sirnulation or The term “design data” as used herein generally refers to the physical design sirnple geonietric ancl Boolean operations.

{G995} production of lt’_7s. For example, the semiconductor‘ device design is clieclted hy software A serniconcluctor device design is verilied by dili‘li‘ei'ent procedures lielore siinu.lation to verify that all features will he printed correctly after lithography in rnanufacturing.

Such checlring cornrnonly includes steps such as design rule checking (DRE), optical rule {J1 ll) WO 2017/091676 PCT/US2016/063506 checking (ORG), and more sophisticated software hased verification approaches that include process simulation calibrated to a specitic lab and process. races} incl odes processing a substrate such as a seniicoriductor wafer usii'ig a large number of Fabricating semiconductor devices such as logic and memory devices typically semiconductor fahrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involv transferring a pattern from a reticle to a resist arranged on a semiconductor wafer.

Additional examples of semiconductor fabrication processes include, hut are not limited to, cheniical—niechanical polishing {Cl\/ll’), etch, deposition, and ion irnplantatiori. lvltiltiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices racer} manufacturiiig process to detect defects on wafers to promote higher yield in the niantifacturing inspection processes are used at various during a seniicoriductor process and thus higher protits. lnspection has always been an important part of fabricating semiconductor devices such as lCs. However, as the diinensions of seiniconductor devices decrease, inspecti on becomes even more important to the successfu.l manufactu.re of acceptable semiconductor devices because smaller defects can cause the devices to fail. F or instance, as the dimensions ofseiniconductor devices decrease, detection of defects of decreasing size has become necessary since even relatively small defects may cause unwanted aberrations in the semiconductor d.evi ces. {secs} operating closer to the limitation on the performance capability of the processes. ln addition, As design rules Sllllflli, however, semiconductor rnanufactnring processes may be smaller defects can have an impact on the electrical parameters of the device as the design rules shrink, which drives niore sensitive inspections. Therefore, as design ru.les shrinlc, the population of potentially yield relevant defects detected by inspection grows dramatically, and the population of nuisance defects detected by inspection also increases dramatically. Therefore, rnore and more defects may be detected on the wafers, and correcting the processes to eliiminate all of the defects may be difficult and expensive. As such, determining which of the defects actually have an effect on the electrical parameters of the devices and the yield may allow process control methods to he focused on those defects while largely ignoring others.

{J} WO 2017/091676 PCT/US2016/063506 lliirthermore, at smaller design rules, process induced failures may, in some cases, tend to he systematic. That process induced failures tend to fail at predetermined design patterns often repeated many times within the design. Elimination of spatially systematic, electrically relevant defects is iniportant because eliniinating such defects can have a sigiiiticant overall impact on yield. ‘Wlietlier or not defects will affect device parameters and yield often cannot be determined from the inspection, review, and analysis processes described above since these processes may not be able to determine the position of the defect with respect to the electrical design.

Brief Siiininaity of the Disclosure {G999} storing dynamic layer content in a design file for a chip. The method comprises receiving a Qne einbodiinent of the present disclosure may be described as a method for design lile having design data corresponding to a plurality of process layers. The design tile may he received by a processor. The processor may also receive a geometric operation formula. The geometric operation formula may be associated with a specific chip area. The geometric operation forniula may he an OR, AND, GRCYW, and/or SHRINK operation, or any combination tlier'eo‘l‘.

{G919} dynaniic layer content that is formed by applying the geonietric operation forniula on two or The method further comprises generating with the processor a. polygori having more of the plurality of process layers.

{G011} having dynamic layer content.

The method further comprises the processor storing in the design lile the polygon {EN 2} indexes in the design tile. Eacli cell index may have cell bounds and data corresponding to cell ln one ernhodiment, the method lurther comprises reading a plurality of cell data of the chip. The method further comprises retrieving the cell hounds associated with a cell index, determining whether the cell bounds intersect with a region of interest and vvhether the cell bounds contain a layer‘ ofiriterest, well as retrieving the cell data if the cell hounds intersect with a region of interest and contain a layer of interest. hi this ernhodirnent. the polygon is generated by applying the geometric operation formula on two or more of the plurality of process layers in the retrieved cell data.

{J1 l() »---i U1 WO 2017/091676 PCT/US2016/063506 {Gdt3} architecture—specitic outlines in the design file. In this embodiment, the polygon may be formed ln another enilicdinient, the method may further comprise detecting one or more hy applying the geometric operation formula on the one or rnore architecture—specifc outlines. racial storing dynarnic layer content in a design file. The system may comprise a design file storage Another enihodinient of the present disclosure may he described as a system for device configured to store one or more design files. Each design file may have design data corresponding to a plurality of process layers for a chip. The system may further comprise a geometric operation formula database coiifi gured to store one or more geometric operation formulas. The geometric operation formula may he an OR, AND, GROW, and/or SHRINK operation, or any combination thereof The geometric operation forrniila may corres pond to a specific chip or one or more process layers on a chip. ln one enihodinient, each geometric operation forinula is associated with a specific chip structure.

{G015} design tile storage device and the geometric operation formula datahase.

The system may also comprise a processor in electronic communication with the {G91 $3 design file for a specific chip; receive, from the geometric operation iorniula database, a geometric operation formula; generate a polygon having dynamic layer content lay applying the geometric operation formula on two or more of the plurality of process layers of the design file; and update the design llle to include the polygon having dynamic lay er content. {0fii?} index has cell bounds and cell design data. ln this einhodinient, the processor is further ln another ernhodirnent, each design tile has a plurality of cell indexes. Each cell configured to retrieve the cell bounds associated with a cell index, determine whether the cell bounds intersect with a region of interest, determine whether the cell bounds contain a layer of interest; and retrieve the cell design data if the cell bounds intersect with a region ofinterest and contain a layer of interest. The polygon may be generated lay applying the geometric operation formula on two or more of the plurality of process layers in the retrieved cell design data. racist more architecttire—specitlc outlines in the design llle. ln this ernhodirnent, the polygon is ln one enihodirnent, the processor may he furtlier configured to detect one or The processor may he configured to receive, from the design file storage device, a {J1 l0 WO 2017/091676 PCT/US2016/063506 generated by applying the geometric operation forrnula on the one or more architecture—specilic outlines.

{G019} transient ccrnptiter readable niediuin containing prograrn instructions for causing a computer to Another einhodiinent of the present disclosure inay he described as a non~ perforrn the method of receiving, at the computer, a design tile having design data correspondiiig to a plurality of process layers; receiving, at the contputer, a geometric operation formula; generating, using the coniputer, a polygon having dynaniic lay er content that is formed hy applying the geonietric operation formula on two or more of the plurality of process layers; and storing in the design tile, using the computer, the polygon having clynantic layer content.

EGQZG} program instructions that further cause the computer to read a plurality of cell indexes in the ln one enrhodinrent, the non~transient computer readable nrediurn may contain design lile, each cell index having cell bounds and data corresponding to cell data of the chip; retrieve the cell bounds associated with a cell index; determine whether the cell hounds intersect with a region ofinterest; determine whether the cell hounds contain a layer of interest; and retrieve the cell data if the cell hounds intersect wi th a region of interest and contain a layer of interest. The polygon is generated hy applying the georn etric operation formula on two or more of the plurality of process layers in the retrieved cell data.

Description of the Drawings EGQE1 } should he made to the following detailed description taken in conjunction with the For a fuller understanding of the nature and ohjects of the disclosure, reference accompanying f.lf{,t‘Wll’l,gS, in which: Figure l is a llowchait illustrating one emhodirnent of the present disclosure; Figure 2 is a graphical representation of a design tile; Figure 3 is a system drawing of a computer systein used in con_iunction with one embodiment of the present disclosure; Figure 4- is a diagram sh owing a. l1OU,'tfa",l.U,Sll0l':y’ computer-readable inediurn storing program instructions executable on a coniputer sy stern for performing a coniputeruiniplenientecl niethod of the present disclosure; and Figure 5 is a llowchait illustrating other einhodinients of the present disclosure.

{J1 l0 >-A U1 WO 2017/091676 PCT/US2016/063506 Detailed Description ofthe Disclosure recast ernhodirnerits, other embodiments, incl udihg embodiments that do not provide all of the henetits Although clainied suhject matter will he described in terms of certain and features set forth herein, are also within the scope of this disclosure. Various s‘tructura.l, logical, process step, and electronic changes may be made without departing from the scope of the disclosure. Accordiriglyg the scope of the disclosure is defined only by reference to the appended cl ai nis. races} seniicon.d.u.ctor or non-seiniconductor material. Examples of such a semicondu.ctor or non— As used herein, the term “wat”er"’ generally refers to substrates forined ofa semiconductor material include, but are not limited to, nioriocrystalhne silicon, gallium arsenide, and indium phosphide. Such substrates may be commonly found and/or processed in semi conductor fabri cation facilities. gases} such layers may include, but are not limited to, a resist, a dielectric material, and a conductive A wafer may include one or more layers foinied upon a substrate. For example, material. Many different types of such layers are lmown in the art, and the term water as used herein is intended to encompass a water including all types ofsucli layers. races} ex.arnple, a wafer may include a plurality of dies, each ha.vi.ng repeatable patterned. features.

Qne or more layers formed on a. water may he patterned or unpatterned. For Formation and processing of such layers of material rnay ultimately result in completed devices. lvlariy dillererit types of devices such as His may he formed on a wafer, and the term wafer used herein is intended. to encoi.npa.ss a wafer on which any type of device known in the art is being fabricated. As used herein, the term “chip” may comprise a collection of lCs designed for a particular purpose. gases} understood that the ernhodirnerits may be used for another specirnen such as a reticle, which may Although embodiments are described herein with respect to wafers, it is to he also he commonly referred to as a inask or a photoniaslt. it/laiiy different types of reticles are 97 known in the art, and the terms “reticle, “mask,” and “photoniasl<” as used herein are intended to encompass all types of reticies kriown in the art. l Ex) [.11 {J} 0 LI: WO 2017/091676 PCT/US2016/063506 {sear} physical design (layout) ofan EC and data derived from the physical design through coniples The ternis “design” and “design data” as used herein generally refer to the siniulation or sirnple geometric and Boolean operations. "the physical design may be stored in a. data structure such as a graphical data stream (6708) file, any other standard. ina.chine—readable file, any other suitable lile hnowii in the art, and a design database. A GDSH tile is one of a class of files used for the representation of design layout data. Qther exainples of such tiles include Glgl and OASlS tiles and proprietary tile l°orinats such RI)? data, which is proprietary to l§LA—"l‘eneor, Milpitas, Calif. ln addition, an iniage of a reticle acquired by a reticle inspection system and/or derivatives thereot‘ can he used as a “proxy” or “proxies” for the design. Such a retiele image or a derivative thereot‘ can serve as a substitute for the design lay out in any einbodiinents described herein that use a design. The design may include any other design data or design data proiries described in conirnonly owned US. Patent Nos. 7,570,796 issued on August 4, 2009 to Zafar et al. and 7,676,077 issued on March 9, 2010 to Kulkarni et al, both of which are incorporated by reference as if fully set forth herein. ln addition, the design data can be standard cell library data integrated layout data, design data for one or more layers, derivatives of the design data, and full or partial chip design data. {seas} and data that is generated by seiniconductor device designers in a design process and is therefore in addition, the “design” and “design data” described herein refers to inforrnation available for use in the einbodinients described herein well in advance of printing of the design on any physical wafers. genes} to the design as it would be ideally lorrned on the wafer‘. hi this niann er, a design or physical Preferably, the “design” or “pliysical design” as those ternis are used herein refer design described herein would preferably not include 7eatures of the design that would not be printed on the wafer such as optical prcxiinity correction (OPC) features, which are added to the design to enhance printing of the leatures on the tV’&f€f without actually being printed thernselyes. ln this manner, in some einhodiinents, the design for the water used for steps described further herein does not include features of the design that will not be printed on the wafer. Each of the steps of the niethod niay he perfornied as described further herein. The method may also include any other steplsl that can he peri’ornied by the design data acquisition subsystein and/or coinputer subsystein(s) or systeni(s) described herein. The steps are perl’orined {J1 WO 2017/091676 PCT/US2016/063506 by one or more computer systems, which may be configured according to any of the embodiments described herein. in addition, the method described above may be perl’ormed by any of the system ernbodirnents described herein. {9G39} inspection system is used as design data in the esign data space. The retiele is used to print the For example in one enibodinient an image of a reticle generated by a reticle design data on the wafer. ln this manner an image or a reticle generated by a reticle inspection system may be used as a substitute for design data. The image of the reticle used in this embodiment may include any suitable image of the reticle generated in any suitable manner by any reticle inspection system i high magnilication optical or electron beam image of the reticle acquired by a high magnification optical reticle inspection system or an electron beam based reticle inspection system respectively. Alternatively the image of the reticle may be an aerial image of the reticle acquired by an aerial imaging reticle inspection system.

{G931 } data. For example, a reticle image generated by a reticle inspection system or any other suitable lmages derived from a reticle image can also serve as a “pr'o;i;y” for the design imaging system can be used to generate a simulated image illustrating how the retiele image would he printed on a Wafer, which can he used us a “proxy” for the design data. ln one embodiment, a simulated image illustrating how a reticle image would be printed on the wafer is used design data in the design data space. ln this manner, a simulation of how a retiele image. would appear on the wafer surface can also serve as a siihstitute for the design data. The simulated image may be generated in any manner using any suitable method or system lmown in the art. The simulated image may be used as a proxy for the design data in any of the embodiments described herein that use design data to perform one or more steps.

{G932} perform one or more steps, the design data may include any of the design data or design data ln enibodinients descnbed herein in which design data is used at least in part, to proxies described above or any combination thereof. {9G33} enabling better sensitivity and throughput. it may be advantageous to augment inspection tools Design—guided inspection enables l.ltlil2'.?t.ti on of design data into i. rater inspection, with design—guided inspection, thus enabling defect detection despite limitations on speed and {J1 l0 >-A U1 WO 2017/091676 PCT/US2016/063506 optics. The presently disclosed embodiments utilize layers in design data to create derived layer data.

EGQ34} corresponds to the design intent of the lithography niash used to print/nia.nul’acture that layer.

Design data may organize the layout in form of layers, where each layer Previously, the design data information is static. N o methods exist to incorporate derived layer content inside design data.

{G935} disclosure. hi this method 100, a polygon for a specilic chip area is retrieved ltll. The polygon Fig 1 describes a method 190 according to one ernhodirnent of the present may be retrieved 101 using a processor. "l‘h.e processor may comprise a centralized or distributed server. The polygon may he retrieved 101 from an external or internal database, hard drive, or from a user-supplied location. The chip area may he an entire chip or a subset of the chip. For example. the chip area may correspond to a specilic structure on a chip.

{G935} design tile or in a manner, such as a separate file, corresponding to a related design tile. The Design tile nietadata is retrieved 193. The design tile nietadaita may be stored in a design tile metadata may he stored on an internal or external database, hard drive, or from a user- supplied location. The design tile irietadata. may include inforniatiori regarding the chip, tolerances, and other relevant information. Details on the design data process layers are retrieved 105 from the rnetadata. The design data process layers may be directly stored in the inetadata, or the design data process layers may be retrieved 165 hy an automated or manual analysis and review of the irieta.data.

{GO3?} present in the design tile metadata. lf so, input process layers may he retrieved 111 from the The next step in the method ltltl is to deterniine Ill’? whether derived layers are derived layers definition. A derived process layer definition includes a formula containing input process layers and one or more operators. The derived process layer is a custom detinition that can be interpreted hy software. Using this custom metadata. defiriition, software is ahle to determine whether derived layer is present in design data. lf no derived layers are present in the design data or inetadata, the cell indexes of the design data are read 139. Cell hounds are retrieved 113, Cell hounds may he arhitra.ry divisions in the design file or divi.sions in the design file related to specitic or repeated structures in the design file.

{J} l() WO 2017/091676 PCT/US2016/063506 {G@38} ofinterest. The region of interest may correspond to a predeterrnined region on the chip or in the The rnethod 110 checlrs 115 to see whether the cell hounds intersect with a region design tile. The region of interest may he stored in the design tile rnetadata. In other einhodiinents, the region of interest may he provided hy the user. ln other ernhodinients, the region of interest niay he dynaniic-ally created hased on feedhaclr frorn defect discovery tools. if the cell hounds do not intersect with the region of interest, a new cell bound is selected and tested.

{G939} the cell contains layers of interest. The layers of interest may correspond to predeterinined layers lf the cell hound intersects with a region of interest. the inethod ltltl checks ii? if on the chip or in the design tile. The layers of interest may be stored in the design file inetadata. ln other ei'nhodii'nents, the layers of interest may he provided by the user. in other ernhodirnents, the layers of interest niay he d.ynainiea.lly created hased on teedha.cl<: froin defect discovery tools. if the cell hounds do not intersect with layers of interest, a new cell hound is selected and tested.

{G949} data does not fall within a region of interest 12}, anew cell hound is selected and tested. ll‘ the ll’ the cell hound contains layers of interest, the cell data is read 119. lf the cell cell data does contain a region of interest. polygon data for one or more layers is retrieved 123. A process derived layer forniula is retrieved 1235 and applied to the polygon data. The polygon data is returned 127 with the derived layers.

{QG41 3 for storing dyn ainic layer content in a design the for a chip. A flowchart descrihin g rnethod Stltl Another ernhodiinent of the present disclosure can he described as a method Silt} is shown in Fig. 5. The niethod 500 coniprises receiving Slll at a processor a design tile. The design tile as design data corresponding to a plurality of process layers. Esarnples ol’ the design lile includes electronic tiles in GDS or OASIS (Open Artworl< Systein interchange Standard) tile formats. The design file contains layout lIlfO1‘lTaEtll.O.‘0.. Fig. 2 is an exarnple of a visual representation of a design file. A design tile inay organize the layout based on layers. Each layer may correspond to the design intent of the lithography niask used to print or rnanufaeturer that layer.

{G942} than one design layer. in this manner, the design data used in the nietliods described herein may ln one ernhodinient. the design data in the portions inclu.d.es design data for more {J} WO 2017/091676 PCT/US2016/063506 he design data for one or more layers of the design. Using design data for one or more layers of the design in the niethods described herein may be useful in instances such as when the defects are detected using bright field (BF) inspection, which may detect defects on more than one layer, and if the criticality of a. location may depend on what happens on previous or following layers of the design. The method described above may include binning some or all defects of interest into groups with at least similar design data. {seas} data and the context layer or layers for the design data. The database may have suitable Design data may be stored in a database that includes the CAD layout for design configuration known in the art and may include any other data or inforniation described herein. in addition, data in database may be stored in any other suitable data structure. The database may be populated by software using GlZ‘o‘Sll tile and context layerts) as inputs. in general, the sol’tware may be configured. as program instructions that are executable on a processor to generate the database using the GDSH tile and the context layer't_s). Context layerts) may be acquired or generated in any rnanner lrnown in the art and may include any context information or data described herein, ln addition, GDSll_ file may be replaced with any other suitable data stiucture in which design data is stored. recast circuit or EC layout artworlr. it is a binary file format representing planar geometric shapes, text A GDSH file is a database file format which is for data exchange of integrated labels, and other inl’orniati on about the layout in hierarchical forni. The data can be used to reconstruct all or part of the aitworl; to be used in sharing layouts. transferring artwork between different tools, or creating photoinas ks.

E9945} given to K) foundries for lC labrication. Obj ects contained in a GDSH file are grouped by GDSII files are usually the final output product of the IC design cycle and are assigning nunieric attributes to th ein including a “layer nuniber", "datatype" or "texttype". ‘While these attributes were designed to correspond to the "layers of material" used in nianufacturing an integrated circuit, their meaning rapidly became more abstract to refl ect the way that the physical layout is desi geese} represent and express an electronic pattern for an integrated circuit during its design and Another type of design file is GASES. OASlS is a language used by cornputers to 11 {J} l() WO 2017/091676 PCT/US2016/063506 manufacture. The language defines the code required for geometric shapes such as polygons, rectangles and trapezoids. lt defines the type of properties each can have, how they can be organized into cells containing patterns made by these shapes and delines how each can be placed relative to each other. OASlS tries to solve the purported problem of the large size of the GDSH tiles by introducing a complicated types of the geometric shapes (25 types of trapezoids only) to reduce the data size. Also, Variable—length nunieric format (similar to Run- length encoding) for coordinates was iniplemented. Finally, each cell in the OASlS tile can be independently compressed by the gzipnlil {G@4?} needs of seniiconcluctor photoinasl: inariulactiuring equipment such as pattern generators and A constrained version of GASIS, called OASlS.MASK, addresses the unique inspection systems. Each line of the OASIS representation below contains a record number and a record type t"ollowed by a set of Values that deline that record type. A cell can he a collection of placed geometric shapes. lt also can he a collection ofcells; each containing other cells and/or geometric shapes. Each cell must have at least one layer. In this view, each color represents a dit7t“eren.t layer within the cell. An integrated circuit can contain tens of thousands of unique cells and repeated instances of the same cell. {ease} the processor. The geornetric operation formula is configured to perform a geometric operation The method Elli} further comprises receiving 593 a geometric operation formula at on two or more layers of a design file. ln other words, the geometric operation l’ormula may create a combination polygon based on the two or more layers of the design file. The geometric operation formula may perform grow, then shrink, then grow operations to reduce the time of data that is being returned by the design pipeline. This operation may be particularly usefiil in electronic design automation systems. Other geometric operation formulas may include XOR which may be useful to illuminate overlaps in Various layers, AND which may be useful to get data only in overlapping regions and discard the rest, and OR which may he useful to identify common areas between two layers and derive meaning out of the result. goose} layer content. ln other embodiments, the geometric operation formula is created and interpreted ln some ernhodirnents, the geometric operation formula may be associated with at runtime. For example, if the design file has an SRAIX/l outline, the NMQS and Pl‘:/l{lS layers may be separately stored in the design lile as separate layers. ln order to idei'i‘tiiy SRAl‘yl care 12 {J1 l0 WO 2017/091676 PCT/US2016/063506 areas for Nl\/IOS regions, the NMOS layer and can he AND’cl to the Sl‘~’;Al\/l outline. The same approach can be extended to the FDA (Pixel to Design Alignment, a design hased aligninent methodology to improve the defect location accuracy reported by the tool) outline layer as well. ln this example the 0Li"T‘lilNl£_l_.A’YER may be generated 595 by the t"orumula ()R€_Sl-lRlNl{(GR{)W(METALl , l0O nin), l(l(lnni)), where lVlETALl is a layer in the design file, and ltltlnni is the value of which the GROW and Sl-lRlNl~'l operations are performed. ln essence, this provides a. formula driven infrastructure that enables the system to extend design services codes easily for future use cases. ln other embodiments, the geometric operation forniula is associated with a specific chip area, such as a SRAM area, logic area, SRAM and periphery logic area. {ease} haying dynamic layer content. The polygon is formed by applying the geometric operation The niethod Silt} fiirtlier comprises generating 505, using the processor, a polygon formula on two or more of the plurality of process layers. After the polygon is generated 505, the polygon is stored in the design tile and the design tile is stored SW7, for example in an internal or external datahase, ln some emhodiments, the design file may be stored in local rnemory after a predeterniined period of time. {asst} processor, a plurality ofcell indexes in the design tile. Each cell index haying cell bounds and ln one enihodinient, the method 500 further comprises reading 599, using the data corresponding to cell data of the chip. The cell index may he a numerical Value mapped to an area of the design or the chip. The cell hounds may he a physical area of a chip or wafer corresponding to the design tile. The cell hounds may he uniforni throughout the design lile (ie, of the size and shape) or they may he non-uniforrn (iiei, different sizes and/or shapes), {nasal hounds associated. Vldlll, a cell index. The rneth od Slltl may further comprise determining 513, The method 568 may further comprise retrieyin g 511 using the processor, the cell using the processor, whetlier the cell bounds intersect with a region of interest. The method Stlfi may further comprise determining 515, using the processor, whether the cell hounds contain a layer of interest. The region of interest may he an area of the chip or design that is prone to defects. The region of interest may be predetermined by the user or dynamically generated by an inspection system. Likewise, the layer of interest may he a layer of the chip or design that is 13 {J1 l0 >-A U1 WO 2017/091676 PCT/US2016/063506 prone to defects. T he layer of interest may he predetermined by the user or dynamically generated by an inspection system.

EGQ53} data. ifthe cell hounds intersect with a region of interest and contain a layer of interest. in one The method Sill} may further comprise retrieving 517, using the processor, the cell embodiment, the polygon is generated hy applying the geometric operation formula on two or more of the plurality of process layers in the retrieved cell data.

{G954} the processor, one or more ?tt‘Cl'lll6C'tuI'€—SpE3ClliC outlines in the design lile, wherein the polygon ln one einhodiinent, the method 500 may further comprise detecting 519, using is formed hy applying the geornetric operation formula on the one or more architecture-specific outlines. For example, an architecture—speciiic outline may he a trace structure, memory structure, gate structure, or collection ol7inemory and gate structures.

EGQ55} storing dynarnic layer content in a design file. The system may comprise a design tile storage Another embodiment of the present disclosure will he described as a system for device configured to store one or more design files. Each design file may have design data corresponding to a plurality of process layers for a chip. The system may further comprise a geometric operation tormula database conti gored to store one or more geometric operation formulas. The system may further comprise a processor in electronic communication with the design tile storage device and the geometric operation formula database.

{Gfi55} design tile for a specific chip. The processor may also be configured to receive, from the The processor may be configured to receive, from the design iile storage device, a geometric operation lorinula database, a geoinetric operation lorinula. The processor may also he configured to generate a polygon having dynamic layer content hy applying the geometric operation formula on two or more of the plurality of process layers of the design file and update the design tile to include the polygon having dynamic layer content.

{G957} For example, the optical and electron heain output acquisition suhsysteins described herein may ln one einhodinient, a design data acquisition subsystem is an inspection system. he configured as inspection systems. in another einhodiinent, the design data accpiisiti on subsystem is a defect review system. For example, the optical and electron beam output acquisition suhsysterns described herein may be configured defect review systems. ln a further 14 l 4 {J} 0 WO 2017/091676 PCT/US2016/063506 einbodiinent, the design data acquisition subsystem is a inetrology system. For example, the optical and electron beam output acquisition subsystems descri bed herein may be conliigured as metrology systems. ln particular, the embodiments of the output acquisition subsystems described herein and shown in Fig. 1 may be niodified in one or more parameters to provide different imaging capability depending on the application for which they will be used. in one such example, the design data acquisition suhsystein shown in Fig. 1 may be configured to have a higher resolution it it is to be used. for defect review or metrology rather than for inspection. in other words, the embodiments of the design data acquisition subsystem shown in Fig. 1 describe some general and various configurations for an design data acquisition subsystern that can be tailored in a number of manners that will be obvious to one skilled in the art to produce output acquisition suhsysterns having d.ii”lerenct iinaging capabilities that are more or less suitable for different applications. geese} subsystems, defect review output acquisitiori subsystems, and metrology design data acquisition The systems and methods of the present disclosure may utilize output acqtiisitioii subsysteins that are configured for inspection, d.ei°ect review, and nietrology of specimens su.ch as wafers and reticles. For etrample, the embodiments described herein may be configured for using both scanning electron microscopy {SE13/l) and optical images for the purposes ofinasl»: inspection, water inspectiori, and vvafer metrology. ln particular, the ernbodirnents described herein may be installed on a computer node or computer cluster that is a component of or coupled to an design data acquisition subsystern such as a broadband plasma inspector, an electron beam inspector or defect review tool, a mask inspector, a virtual inspector, etc. in this manner, the embodiinents described herein may generate ou.tput that can be used for a vari ety of applications that include, but are not limited to, water inspection, inash inspection, electron beam inspection and review, inetrology, etc. The characteristics of the output acquisition subsysteins shown in Fig. 3 can be moditied as described above based on the specimen for which it will generate actual output. geese} least an energy source and a detector. The energy source is configured to generate energy that is Such a subsystem includes a design data acquisition subsystem that includes at directed to a vvafer. The detector is coritigured to detect energy lroin the wafer’ and to generate output responsive to the detected energy.

{J1 Ex) [.11 WO 2017/091676 PCT/US2016/063506 EGQQG} ln one enihodinient, the energy directed to the wafer includes light, and the energy detected from the wafer includes light. For exainple, in the embodiment of the system shown in Fig. 3, design data acquisition suhsystern it} includes an illumination subsystem confi gured to direct light to wafer 14. The illurnination suhsystein includes at least one light source. For exainnle, as shown in Fig. 3, the illuniinati on suhsystern includes light source id. ln one enihodinient, the illumination suhsystein is configured to direct the light to the water at one or more angles of incidence, which may include one or more ohlique angles and/or one or more normal angles. For example, as shown in Fig. 3, light from light source 16 is directed through optical element 18 and then lens 28 to beam splitter 21, which directs the light to water icl at a nornial angle of incidence. The angle ofincidence may include any suitable angle of incidence, which may Vary depending on, for instance, characteristics of the wafer.

{G961} The illuniination suhsystem may be configured to direct the light to the water at different angles of incidence at diffei'ent times. For example, the design data acquisition suhsystern may he conli gured to alter one or more characteristics of one or more elements of the illumination subsystem such that the light can he directed to the wafer at an angle of incidence that is different than that shown in Fig. 3. ln one such example, the design data acquisition subsystem may be configured to move light source l6, optical element 18, and lens 20 such that the light is directed to the wafer at a different angle ofincidence.

{G962} in some instances, the design data acquisition subsystem may be configured to direct light to the wafer at more than one angle of incidence at the same time. For exarnplec the illurnination suhsystem may include more than one illuniination channel, one of the illurnination channels may include light source 16, optical element 18, and lens Ztl as shown in Fig. 3 and another of the i.lluinination channels (not shown) may include siniilar elements, which may be configured differently or the sanie, or may include at least a light source and possihly one or more other components such as those described further herein. ll such light is directed to the wafer at the same time the other light, one or more characteristics ( g., wavelength, polarization, etc.) of the light directed to the wafer at different angles of incidence may be different such that light resulting from illumination of the wafer at the different angles of incidence can be discriminated from each other at the detectorts). 16 {J1 l0 ix) [A WO 2017/091676 PCT/US2016/063506 recast (cg, source l6 shown in Fig. 3) and light from the light source may be separated into different ln another instance, the illuinination suhsystein may include only one light source optical paths (et based on wavelength, polarization, etc]; by one or more optical elements (not shown) of the illumination sulisystenr. liight in each of the different optical paths may then be directed to the wafer. lvlultiple illumination channels may he configured to direct light to the wafer at the same time or at different times (e. when different illurniriation channels are used to sequentially illuminate the wafer). ln another instance, the same illumination channel may be configured to direct light to the wafer with different characteristics at different times. F or esarnple, in some instances, optical element 18 may be configured as a spectral filter and the properties of the spectral filter can he changed in a variety of different ways ( e. g, by swapping out the spectral filter) such that different wavelengths of light can he directed to the wafer at different times. The illuniination subsystem may have any other suitable configuration lrnown in the art for directing the light having different or the chara,cteris‘tics to the wafer at diffei'ent or the same angles of incidence sequentially or sirnultaneously. genes} source. in this manner, the light generated by the light source and directed to the wafer niay ln one einliodinient, light source 16 may include a hroadhand. plasma (BB?) light include liroadharid light. However, the light source may include any other suitable light source such as a laser. The laser may include any suitable laser knowii in the art and may he conligured to generate light at any suitahle wavelength or wavelengths lznown in the art. ln ad.d.i ti on, the laser may be configured to generate light that is monochromatic or nearly—nionochroniatic. ln this inanner, the laser may he a narrowhand laser. The light source may also include a polychromatic light source that generates light at multiple discrete wavelengths or waveliands, genes} Although lens .20 is shown in Fig. 3 as a single refractive optical element, it is to he understood Light from optical element 18 may he focused to lieam splitter 21 hy lens Ztl. that, in practice, lens 29 may include a number of refractive and/or reflective optical elements that in con’ihinati on focus the light from the optical element to the wafer. The illumination suhsysteni shown in Fig. 3 and described herein may include any other suitable optical elements (not shown). Examples of such optical elenients include, hut are not limited to, polarizing component(s), spectral liltert spatial filter(s), retlective optical elei'neiit(s), E1p0(‘ll;€€:l'(S), heani splitter(s), aperture(s), and the like, which may include any such suitable optical elements l 17 {J1 ll) Ex) [.11 WO 2017/091676 PCT/US2016/063506 in the art. in addition, the system may he configured to alter one or more of the elements of the illumination subsystem based on the type of illumination to he used for output acquisition.

EGQSE} conli gured to cause the light to be scanned over the wafer. For example, the design data The design data acquisition subsystem may also include a scanning subsystem acquisition subsystem may include stage 22 on which wafer 14 is disposed during output acquisition. The scanning subsystem may include any suitable mechanical and/or rohotic assemhly (that includes stage 22) that can he conli gured to move the water such that the light can he scanned over the wafer. In addition, or alterna.tivel.y, the design. data acquisition suhsysteni may he conligured such that one or more optical elenients of the design data aci:iuisition subsystem perform some scanning of the light over the wafer. The light may he scanned ov er the wafer in any suitable fashion.

{QGSTE channels. At least one of the one or more detection channels includes a detector configured to The design data acquisition subsystem further includes one or more detection detect light froni the water due to illumination of the water by the design data acquisition subsystem and to generate output responsive to the detected light. For example, the design data acquisition suhsystein shown in Fig. 3 includes two detection channels, one fornied hy collector 24, element 26, and detector 28 and another fornied hy collector Sh, element 32, and detector 34.

As shown in Fig. 3, the two detection channels are configured to collect and detect light at different angles of collection. In some instances, one detection channel is configured to detect specul arl y rei‘lected light, and the other detection channel is conligiired to detect light that is not specularly rellected (e. scattered, dillracted, etc.) from the wafer. l'lOW€V€l“, two or more of the detection channels may be configured to detect the same type of light ll‘Ofl'l the wafer specularly reflected light). Although Fig. 3 shows an enihodinient of the design data acquisition suhsystem that includes two detection channels, the design data acquisition subsystem may include a different nuinher of detection channels (eg, only one detection channel or two or more detection channels). Although each of the collectors are shown in Fig. 3 as single rel‘ra.ctive optical elements, it is to he understood that each of the collectors may include one or more refractive optical element( s) and/or one or more reflective optical eleinent(s).

{G988} the art. For example, the detectors may include photo—inultiplier tuhes (Flt/iTs), charge coupled The one or more detection channels may include any suitable detectors lrnown in 18 l Ex) [.11 4 {J} 0 WO 2017/091676 PCT/US2016/063506 devices (CCl)s), and time delay integration (Till) cameras. The detectors may also include any other suitable detectors known in the art. The detectors may also include non—irnaging detectors or imaging detectors. ln this manner, if the detectors are non—imaging detectors, each of the detectors may be configured to detect certain characteristics of the scattered light such intensity hut may not be configured to detect such characteristics as a function ofposition within the imaging plane. As such, the output that is generated by each of the detectors included in each of the detection channels of the design data acquisition subsysteni may he signals or data, but not image signals or image data. in such instances, a computer subsystem such as computer suhsysteni 36 of the system may be configured to generate images of the wafer from the nonu imaging output of the detectors. However, in other instances, the detectors may he conii gured imaging detectors that are configured to generate imaging signals or irnage Therefore, the system may be contigui'ed to generate the images described herein in a number of ways.

Efifldhl an design data acquisition suhsysterri that may he included in the systeni embodiments described lt is noted that Fig. 3 is provided herein to generally illustrate a configuration of herein. Obviously, the design data acquisition suhsystein configuration described herein may be altered to optimize the performance of the system as is normally performed when designing a commercial system. in addition, the systems described herein may be implemented using an existing output acquisition system (e. by adding functionality described herein to an existing output acquisition system) such as tools that are commercially ayailahle froin Kl_iA—'l‘encor. For some such systems, the methods descrihed herein may be pi'cyided as optional functionality of the output acquisition system in addition to other functionality of the output acquisition system). Alternatively, the system described herein may he designed “front scratch” to prcyid.e a completely new system.

{GWG} design data acquisition suhsystern in any suitable manner (e. via one or more transmission Computer subsystem 36 of the system may he coupled to the detectors of the media, which may include “wired” and/or “wii'eless” transmission media) such that the computer subsystem can receive the output generated hy the detectors during scanning of the wafer.

Computer subsystem 365 may he configured to perfcrin a number of functions using the output of the detectors described herein and any other functions described further herein. This computer suhsystein may be further con.figui'ed. as described herein. 19 {J1 l0 WO 2017/091676 PCT/US2016/063506 {G@?1} herein) may also he relierred to herein computer system(s). Each of the computer suhsystemtis) This computer subsystem (as well as other computer subsystems described or system(s) described herein may tal image computer, mainframe coinpu.ter system, worlzstation, networlt appliance, Internet appliance, or other device. ln general, the term “computer system” may be broadly defined to encompass any device having, one or more processors, which executes instructions l7rom a memory medium. The computer suhsystent(s) or system(s) may also include any suitable processor hnown in the art such as a parallel processor. hi addition, the computer subsystemts) or system(s) may include a computer platform with high speed processing and software, either as a standalone or a ne‘tworl tears} computer subsystems may he cou.pled. to each other such that images, data, information, ll the system includes more than one computer subsystem, then the diffei'erit instructions, etc. can be sent between the computer subsystems as described further herein. For example, computer subsystem 36 may be coupled to computer suhsy"steni(s) 182 by any suitable transmission media, which may in cl ud.e any suitable wired and/or wireless transmission media hnown in the art. Two or more of such computer suhsystems may also be effectively coupled by a shared computer—readable storage medium (not shown). rears} storing program instructions executable on a computer system for performing a compu.ter~ An additional embodiment relates to a nonutransitory computer~readable medium implemented method for determining overlay error hetween different patterned. features of a design printed on a water in a multi—patterning step process. One such embodiment is shown in Fig. 4. in particular, as shown in Fig. 4, non—transitory computer~readable medium 180% includes program instructions llllllz executable on coinpu.ter system 1894. The computer~impleinented method may include any step(s) of any methodts) described herein. rears} may be stored on computer—readahle medium 189%. The computer-readable medium may be a Prograin instructions 1802 iinplementiiig methods such as those described herein storage medium such as a magnetic or optical dislg, a magnetic tape, or any other suitable non- transitory computer—readahle medium known in the art.

{J} WO 2017/091676 PCT/US2016/063506 tears} procedureubased techniques, coniponent-‘cased techniques, and/or ohiect—oriented techniques, The program instructions may be implemented in any of Various ways, including among cth For example, the program iristructioris may he irnplemented using ActiyeX controls, C++ objects, Jayafleans, Microsoft Foundation Classes (“MFG”), (Streaming SEMD Extension) or other technologies or methodologies, as desired. tests} described herein.

Computer system 1894 may be configured according to any of the enrrhodiinents {Gfl?7} partircular ernhodirnents, it will he understood that other embodiments of the present disclosure Although the present disclosure has been described with respect to one or more may be made without departing from the spirit and scope of the present disclosure. Hence, the present disclosure is deemed limited only by the appended claims and the reasonable iriterpi'etation thereof. 21

Claims (1)

1. WO 2017/091676 PCT/US2016/063506 What is clainied is: l. A method for storing dynaniic layer content in a design file for a chip coniprising; receiving, at a processor, a design file having design data corresponding to a plurality of process layers; 5 receiving, at the processor, a geometric operation fornnila; generating, using the processor, a polygon having dynainic layer content that is fornied by applying the geometric operation formula on two or more of the plurality of process layers; and storing in the design file, using the processor, the polygon having dynainic layer content. 10 2. The method of claini l, wherein the geonietric operation forniiila is associated with a specific chip area. 3. The rnethod of claim l, further cornprising: reading, using the processor, a plurality of cell indexes in the design file, each cell index having cell bounds and data corresponding to cell data of the chip, >-A U1 retrieving, using the processor, the cell hounds associated with a cell index; deterniining, using the processor, whether the cell hounds intersect with a region of interest; determining, using the processor, whether the cell hounds contain a layer of interest; and retrieving, using the processor, the cell data if the cell hounds intersect with a region of interest and contain a lay er of interest; 20 wherein the polygon is generated hy applyirig the geometric operation fornnila. on two or more of the plurality of process layers in the retrieved cell data. 4. The inethod of claini l, wherein the geonietric operation forniula is an OR operation. 5. The inethod of claini l, wherein the geonietric operation forniula is an AND operation. 6. The inethod of claini l, wherein the geonietric operation forniula is a GROW operation. ix.) U1 *4 T . The inethod of claini l, wherein the geonietric operation forniula is a K operation. 8. The inethod of claini l, further coniprising: 22 WO 2017/091676 PCT/US2016/063506 detecting, using the processor, one or more architecture—specitic outlines in the design file, wherein the polygon is forinecl by applying the geometric operation forniula on the one or more archi tecture—speci tic outlines. 9, A system for storing dynaniic layer content in a design tile comprising: 5 a design tile storage device configured to store one or more design tiles, each design tile having design data corresponding to a plurality of process layers for a chip; a geonietric operation l'iO1‘Il’ltJ.l2t database corifi gored to store one or more geometric operatti on l’ormula.s; a processor in electronic connnunication with the design file storage device and the l() geometric operation forniula database, the processor configured to: receive, from the design tile storage device, a design tile for a specific chip, receive, from the geometric operation formula database, a geometric operation formula; generate a polygon having dynarnic layer content by applying the geometric operation forinula on two or more of the plurality of process layers of the design tile, and l5 update the desi tile to include the polygon having dynamic layer content. la’). The system of claim 9, wherein the geometric operation formula is associated with a specific chip structure. ll. The system of claim 9, wherein each design file has a plurality of cell indexes, eac cell index having cell hounds and cell design data, and wherein the processor is fiirther contigui'ed to: 20 retrieve the cell hounds associated with a cell index; determine whether the cell hounds intersect with a region of interest; determine whether the cell hounds contain a layer ofinterest; and retrieve the cell design data it‘ the cell hounds intersect with a region of interest and contain a layer of interest; 25 wherein the polygon is generated by applying the geoinetnc operation formula on two or more of the plurality of process layers in the retrieved cell design data. l2, The system of claim 9, wherein the geometric operation f()I1'Tl1ll£llS an OR operation. l3, The system of claim 9, wherein the geometric operation l’on'mila is an AND operation. 23 ll) 20 l\) {J} WO 2017/091676 PCT/US2016/063506 lit. The system of claim 9, wherein the geometric operation formula is a GROW operation. l5. The system of claim 9, wherein the geometric operation formula is a Slllllllllsl operation. l6. The system of claim 9, wherein the processor is further configured to: detect one or more architecture—specilic outlines in the design file, wherein the polygon is generated hy applying the geornetric operation forrnula. on the one or more arcliitecture~specitlc outlines. l7. The system of claim wherein the geometric operation formula corresponds to the specific chi p. l8. The system of claim 9, wherein the geometric operation formula corresponds to one or more process layers on the cliip. l9. A rion~transient computer readable inediurn containing prograrn instructions for causing a computer to perform the method of: receiving, at the computer, a design file haying design data corresponding to a plurality of process layers; receiving, at the computer, a. geonietric operation formula, generating, using the computer, a polygon haying dynamic layer content that is formed hy applying the geometric operation formula on two or more of the plurality of process layers; and storing in the design tile, using the computer, the polygon haying dynamic layer content. 20. The non—transient computer readable merliuin of claim l9, wherein the program instructions further cause the cornputer to perforin the method of; reading, using the computer, a plurality of cell indexes in the design tile, each cell index liaying cell bounds and data corresponding to cell data. of the chip, retrieving, using the computer, the cell hounds associated with a cell index; determining, using the computer, whether the cell hounds intersect with a region ofinterest, determining, using the computer, whether the cell hounds contain a layer of interest; and retrieving, using the computer, the cell data if the cell hounds intersect with a region of interest and contain a lay er of interest; 24 WO 2017/091676 PCT/US2016/063506 wherein the polygon is generated by applying the geeinemc operation formula; on two or more efthe piuraiity of process layers in the retrieved cell data. 25