IL154515A0 - System and method for automation of asic synthesis flow - Google Patents

System and method for automation of asic synthesis flow

Info

Publication number
IL154515A0
IL154515A0 IL15451503A IL15451503A IL154515A0 IL 154515 A0 IL154515 A0 IL 154515A0 IL 15451503 A IL15451503 A IL 15451503A IL 15451503 A IL15451503 A IL 15451503A IL 154515 A0 IL154515 A0 IL 154515A0
Authority
IL
Israel
Prior art keywords
automation
synthesis flow
asic
asic synthesis
flow
Prior art date
Application number
IL15451503A
Original Assignee
Asicserve Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asicserve Ltd filed Critical Asicserve Ltd
Publication of IL154515A0 publication Critical patent/IL154515A0/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
    • G06F16/25—Integrating or interfacing systems involving database management systems
    • G06F16/258—Data format conversion from or to a database
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Databases & Information Systems (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Data Mining & Analysis (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
IL15451503A 2002-03-07 2003-02-18 System and method for automation of asic synthesis flow IL154515A0 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/091,393 US20030172045A1 (en) 2002-03-07 2002-03-07 System and method for automation of ASIC synthesis flow

Publications (1)

Publication Number Publication Date
IL154515A0 true IL154515A0 (en) 2003-09-17

Family

ID=29547986

Family Applications (1)

Application Number Title Priority Date Filing Date
IL15451503A IL154515A0 (en) 2002-03-07 2003-02-18 System and method for automation of asic synthesis flow

Country Status (2)

Country Link
US (1) US20030172045A1 (en)
IL (1) IL154515A0 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7111269B2 (en) * 2003-10-23 2006-09-19 Lsi Logic Corporation Comparison of two hierarchical netlist to generate change orders for updating an integrated circuit layout
US8443335B2 (en) * 2009-12-09 2013-05-14 Agnisys, Inc. Apparatus and method for circuit design
US9864583B2 (en) 2014-11-14 2018-01-09 Cavium, Inc. Algorithm to derive logic expression to select execution blocks for programmable network devices
CN105677960A (en) * 2016-01-04 2016-06-15 中国兵器工业集团第二一四研究所苏州研发中心 Implementing method for Auto-DC automation integrated design
US10460060B2 (en) 2017-11-27 2019-10-29 Mellanox Technologies, Ltd. Checking equivalence between changes made in a circuit definition language and changes in post-synthesis nets
US10599802B2 (en) * 2018-06-18 2020-03-24 Mellanox Technologies, Ltd. Methods for automatic engineering change order (ECO) bug fixing in integrated circuit design

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6185728B1 (en) * 1996-01-31 2001-02-06 Inprise Corporation Development system with methods for type-safe delegation of object events to event handlers of other objects
US5903475A (en) * 1996-07-18 1999-05-11 Lsi Logic Corporation System simulation for testing integrated circuit models
US5963454A (en) * 1996-09-25 1999-10-05 Vlsi Technology, Inc. Method and apparatus for efficiently implementing complex function blocks in integrated circuit designs
US6374205B1 (en) * 1998-02-13 2002-04-16 Kabushiki Kaisha Toshiba Method of reducing circuit data, method of simulating circuit, and medium for storing circuit data reduction program
US6425116B1 (en) * 2000-03-30 2002-07-23 Koninklijke Philips Electronics N.V. Automated design of digital signal processing integrated circuit
US6968346B2 (en) * 2001-04-23 2005-11-22 International Business Machines Corporation XML-based system and method for collaborative web-based design and verification of system-on-a-chip

Also Published As

Publication number Publication date
US20030172045A1 (en) 2003-09-11

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