IL139674A - Extending the range of computational fields of integers and width of serial input operands in modular arithmetic public key cryptographic co-processors designed for elliptic curve and rsa type computations - Google Patents
Extending the range of computational fields of integers and width of serial input operands in modular arithmetic public key cryptographic co-processors designed for elliptic curve and rsa type computationsInfo
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- IL139674A IL139674A IL13967400A IL13967400A IL139674A IL 139674 A IL139674 A IL 139674A IL 13967400 A IL13967400 A IL 13967400A IL 13967400 A IL13967400 A IL 13967400A IL 139674 A IL139674 A IL 139674A
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Claims (61)
139674/2 CLAIMS \^ 1) A microelectronic apparatus for performing ® multiplication and squaring in both polynomial based GF(29) and GF(p) field arithmetic, squaring and reduction using a serial fed radix 2L multiplier, 5, with k character multiplicand segments, A , and a k character © accumulator wherein reduction to a limited congruence is performed "on the fly", in a systolic manner, with A\, a multiplicand, times B, a multiplier, over a modulus, N, and a result being at most 2k + 1 characters long, including the k first emitting disregarded zero characters, which are not saved, where k characters have no less bits than the modulus, the apparatus comprising; a first (B), and second (N) main memory register means, each register operative to hold at least n bit long operands, respectively operative to store a multiplier value designated B, and a modulus, denoted N, wherein the modulus is smaller than 2n; a digital logic sensing detector, YQ, operative to anticipate "on the fly" when a modulus value is to be © added to the value in the © adder accumulator device such that all first k characters emitting from the device are forced to zero; a modular multiplying device for at least k character input multiplicands, with only one, at least k characters long © adder, © summation device operative to accept k character multiplicands, the ® multiplication device operative to switch into the © accumulator device, in turn, multiplicand values, and in rum to receive multiplier values from a B register, and an "on the fly" simultaneously generated anticipated value as a multiplier which is operative to force k first emitting zero output characters in the first phase, wherein at each effective machine cycle at least one designated multiplicand is © added into the © accumulation device; the multiplicand values to be switched in turn into the © accumulation device consisting of one or two of the following three multiplicands, the first multiplicand being an all-zero string value, a second value, being the multiplicand A and a third value, the No segment of the modulus; supenrap 4 52 U/13 2000 4:04- PM 139674/2 an apparatus to anticipate the /bit k character serial input YQ multiplier values; the multiplier values which are input in turn into the multiplying device in the first phase being first the B operand, and concurrently, the second multiplier value consisting of the YQ, "on the fly" anticipated k character string, to force first emitting zeroes in the output; an © accumulation device, operative to output values simultaneously as multiplicands are © added into the Θ accumulation device; an output transfer mechanism, in the second phase operative to output a final modular ® multiplication result from the © accumulation device.
2. An apparatus as in claim 1 wherein © summations into the © accumulation device are activated by each new serially loaded higher order multiplier characters.
3. An apparatus as in claims 1 and 2, wherein the multiplier characters; are operative to cause no Θ summation into the © accumulation device if both the input B character and the corresponding input YQ character are zeroes; are operative to © add in only the ; multiplicand if the input B character is a one and the corresponding Yo character is a zero; are operative to © add in only the N, modulus, if the B character is a zero, and the corresponding YQ character is a one; and are operative to © add in the © summation of the modulus, N, with the multiplicand A{ if both the B input character and the corresponding YQ character are ones.
4. An apparatus as in claim 1, operative to preload multiplicand values A; and N, into two designated preload buffers, and to © summate these values into a third multiplicand preload buffer, obviating the necessity of © adding in each multiplicand value separately.
5. An apparatus as in claim 1, wherein the multiplier values are serial single character in input and the output of the © accumulation device is serial single supenmp 4 53 11/13/2000 4:04 PM 139674/2 character output, wherein the YQ detect device is operative to anticipate only one character in a clocked turn.
6. An apparatus as in claim 1, wherein the Θ accumulation device performs modulo 2, XOR addition/subtraction, wherein all carry bits in addition and subtraction components are disregarded, thereby precluding provisions for overflow and further limiting convergence in computations.
7. A ® multiplication apparatus as in claim 1 wherein all carry inputs are disabled to zero, denoted, =0, typically operative to perform polynomial based multiplication.
8. An apparatus as in claim 1 wherein an i equal to zero acting on an element in a circuit equation computing in GF(29), the if designates omitted circuitry and all adders and subtractors, designated Θ have been reduced to XOR, modulo 2 addition/subtraction elements.
9. An apparatus as in claim 1 wherein k first emitting zeroes will egress from the device controlled by the following four quantities in anticipating the next in turn 7o character: i the /bit S0M bits of the result of the /bit by /bit mod 2L ® multiplication of the right-hand character of the A; register times the Bd character of the B Stream, A0-BD mod 2L ii the first emitting carry out character from the Θ accumulation device, if(CO0); iii the /bit SOAT character from the second from the right character emitting cell of the Θ accumulation device, SO\ \ iv the / bit Jo value, which is the negative multiplicative inverse of the right-hand character in the No modulus multiplicand register. supenmp 4 54 11/13/2000 4:04 PM 139674/2 wherein values, A -Bd mod 2l, !f(COo), and SO\ are © added character to character together and "on the fly" multiplied by the Jo character to output a valid Y zero-forcing anticipatory character to force an /bit egressing string of zeroes.
10. An apparatus as in claim 1, wherein ® multiplication on polynomial based operands is performed in a reverse mode, multiplying from right hand MS characters to left hand LS characters, operative to perform modular reduced ® multiplication without Montgomery type parasitic functions.
1 1. An apparatus as in claim 1 where the preload buffers are serially fed and where multiplicand values are preloaded into the preload buffers on the fly from a multiplicity of memory devices.
12. An apparatus as in claim 1, wherein a previous value, emitting from an additional n bit register, S, is ® summated into the output value of the ® accumulation device via an /bit ® adder circuit such that first emitting output characters are zeroes when the 70 detector is operative to detect the necessity of ® adding moduli to the ® summation in the ® accumulation device, wherein the Yo detector is operative to detect utilizing the next in turn © added characters A -Bd mod 2l, -/(CO0), SO Sd and ύ"(( >ζ), the composite of © added characters to be finite field ® multiplied on the fly by the /bit Jo value, where Θ defines the addition and ® defines the multiplication as befits the finite field used in the process.
13. An apparatus as in claim 1, wherein for /= 1 , Jo is implicitly 1, and the J0 ® multiplication is implicit, without additional hardware.
14. An apparatus as in claim 1 wherein a comparator is operative to sense a finite field output from the ® modular multiplication device, working in GF(p), where the first right hand emitting k zero characters are disregarded, where the output is larger than the modulus, N, thereby operative to control a modular reduction whence said value is output from the memory register to which the output stream from the multiplier device is destined, and thereby precluding allotting a second memory storage device for the smaller product values. supemap 4 55 11/13/?000 4:04 PM 139674/2
15. A device as in claim 1 wherein for ® modular multiplication in the GF(2<?), the apparatus is operative to multiply without an externally precomputed more than /bit zero-forcing factor.
16. A method according to claim 1 operative to compute a Jo constant by resetting either the A operand value or the B operand value to zero and setting the partial result value, So, to 1.
17. A microelectronic method and apparatus for performing interleaved finite field ® modular multiplication of integers A and B operative to generate an output stream of A times B modulus N wherein n the number of characters in the modulus operand register is larger than k, wherein the ® multiplication process is performed in iterations, wherein at each interleaved iteration with operands input into a ® multiplying device, consisting of N, the modulus, B, a multiplier, a previously computed partial result, 5, and a k character string segment of A, a multiplicand, the segments progressing from the A0 string segment to the Am.\ string segment, wherein each iterative result is Θ summated into a next in turn S, temporary result, in turn, wherein first emitting characters of iterative results are zeroes, the apparatus comprising: first (5), second (5) and third (N) main memory registers, each register capable of storing and outputting operands, respectively operative to store a multiplier value, a partial result value and a modulus, also denoted N; a modular multiplying device operative to Θ summate into the Θ accumulation device, in turn one or two of a plurality of multiplicand values, in turn, during the phases of the iterative ® multiplication process, and in turn to receive as multipliers, in turn, inputs from a first value B register, second, from an "on the fly" anticipating value, YQ, as a multiplier to force first emitting right-hand zero output characters in each iteration, and third values from the modulus, N, register; supermap 4 56 11/13 2000 4:04 PM 139674/2 the multiplicand parallel registers operative at least to receive in turn, values from the A, B, and N register sources, and in turn, also a multiplicand zero forcing y0, value; a first emitting zero forcing Yo detect device operative to generate a binary string operative to be a multiplier during the first phase and operative to be a multiplicand in the second phase; multiplicand values to be switched into the accumulation device for the first phase consisting of a first zero value, a second value, A\, which is a k character string segment of a multiplicand, A, and a third value No, being the first emitting k characters of the modulus, N; a temporary result value, 5, resulting from a previous iteration, operative to be summated with the value emanating from the accumulation device, to generate a partial result for the next in turn iteration; multiplicand values to be input, in turn, into the accumulation device for the second phase being, a first zero value, a second A\ operand, remaining in place from the first phase, and a third YQ value having been anticipated in the first phase; multiplier values input into the multiplying device in the first phase being a first emitting string, ¾ being the first emitting string segment of the B operand, concurrently multiplying with the second multiplier value consisting of the anticipated Y0 string which is simultaneously loaded character by character as it is generated into a preload multiplicand buffer for the second phase; the two multiplier values input into the apparatus during the second phase being the left hand n - k character values from the B operand, designated B, and the left hand n - k characters of the N modulus, designated N, respectively; and a multiplying flush out device operative in the last phase to transfer the left hand segment of a result value remaining in the accumulation device into a result register.
18. An apparatus as in claim 17, wherein multiplication on polynomial based operands is performed in a reverse mode, multiplying from MS characters _penna 4 57 11/13/20004:04 PM 139674/2 to LS characters, operative to perform modular reduction without Montgomery type parasitic functions.
19. An apparatus operative to anticipate the K0 value using first emitting values of the multiplicand, and present inputs of the B multiplier, carry out values from the accumulation device, summation values from the accumulation device, the present values from the previously computed partial result, and carry out values from the adder which summates the result from the accumulation device with the previous partial result.
20. An apparatus as in claim 19 wherein k first emitting zeroes will egress from the device controlled by the following six quantities in anticipating the next in turn YQ character: i the /bit 5Out bits of the result of the /bit by /bit mod 2L multiplication of the right-hand character of the A\ register times the BD character of the B Stream, A0-5d mod 2L ii the first emitting carry out character from the accumulation device, ^(COo); iii the /bit Sout character from the second from the right-hand character emitting cell of the accumulation device, iv the next in turn character value from the S stream, Sd, v the / bit carry out character from the Z output full adder, ( Oz); vi the /bit J0 value, which is the negative multiplicative inverse of the right-hand character in the No modulus multiplicand register; wherein values, A0-BD mod 2L, ^{COQ), SO] , Sd are added character to character together and "on the fly" multiplied by the Jo character to output a supermap 4 58 11/13 2000 4:04 PM 139674/2 valid YQ zero-forcing anticipatory character to force an / bit egressing character string of zeroes.
21. An apparatus as in claim 17 comprised of at least one sensor operative to compare the output result to N, the modulus, the mechanism operative to actuate a second subtractor on the output of the result register, thereby to output a modular reduced value which is limited congruent to the output result value precluding the necessity to allot a second memory storage for a smaller result.
22. An apparatus as in claim 17 where a value which is a summation of two multiplicands is loaded into a preload character buffer with at least a k characters memory means register concurrently whilst one of the values is loaded into a preload buffer.
23. An apparatus with only one accumulation device, and an anticipating zero forcing mechanism operative to perform a series of interleaved modular multiplications and squarings concurrently performing the equivalent of three natural integer multiplication operations, such that a result is an exponentiation.
24. An apparatus as in claim 17 where next in turn used multiplicands are preloaded into preload register buffer means on the fly.
25. An apparatus as in claim 17 where a value which is a summation of two multiplicands is summated into at least a k character register concurrently whilst one of the values is loaded into its preload buffer.
26. An apparatus as in claim 17 wherein apparatus buffers and registers are operative to be loaded with values from external memory sources and said buffers and registers are operative to be unloaded into the external memory source during computations, such that the maximum size of the operands is dependent on available memory means.
27. An apparatus as in claim 17 wherein memory register means are typically serial single character in/serial single character out, parallel at least k characters in/parallel at least k characters out, serial single character in/parallel at least k characters out, and parallel k characters in/serial single character out. superraap 4. · 59 11/13/2000 4:04 PM 139674/2
28. An apparatus as in claim 17 wherein the final phase of a multiplication type iteration, the multiplier inputs are zero characters operative to flush out the left hand segment of the carry save accumulator memory.
29. An apparatus as in claim 17 where next in turn used multiplicands are preloaded into preload memory buffers on the fly.
30. An apparatus as in claim 17 where multiplicand values are preloaded into the preload buffers on the fly from central storage memory means.
31. A method according to claim 17 comprising computing /0 = l o for = 1 by resetting both A and B to zero and setting 50 = 1. supenmp 4 60 11/13/20004:04 PM 139,674/3
32. A method for performing a modular arithmetic multiplication, A- B (mod N), of an integer multiplier, denoted A, with an integer multiplicand, denoted B, modulo an integer modulus, denoted N, using base r integer arithmetic and without performing an integer division operation, wherein at least one of A, B and N is a large integer, comprising: selecting a segment length, denoted k, wherein a segment is a k-character integer, and wherein a character is an integer between 0 and r-1 ; representing each of A, B and N in base r as a sequence of at least one segment; and performing the following operations at most m times: multiplying two k-character integers in base r summing two k-character integers in base r, and adjusting a k-character base r integer so as to force its least significant character to be zero.
33. A method according to claim 32 wherein said multiplying two k-character integers includes multiplying one of the segments of A and one of the segments of B.
34. A method according to claim 32 wherein said multiplying two k-character integers includes multiplying a k-character integer by a pre-computed constant Jo = -No"1 (mod rk), wherein No denotes the least significant segment of N.
35. A method according to claim 32 wherein said summing uses carry sum addition.
36. A method according to claim 32 wherein said adjusting a k-character integer operates by adding an integral multiple of N to the k-character integer.
37. A method for performing a modular arithmetic exponentiation, AE (mod N), 139,674/3 of an integer, denoted A, raised to an integer power, denoted E, modulo an integer modulus, denoted N, using base r integer arithmetic and without performing an integer division operation, wherein at least one of A, E and N is a large integer, comprising: selecting a segment length, denoted k, wherein a segment is a k-character integer, and wherein a character is an integer between 0 and r-1; representing each of A, E and N in base r as a sequence of at least one segment; and multiplying two k-character integers in base r; summing two k-character integers in base r; and adjusting a k-character base r integer so as to force its least significant character to be zero.
38. A method according to claim 37 wherein said adjusting a k-character integer operates by adding an integral multiple of N to the k-character integer.
39. A method for public key encryption comprising: performing a modular arithmetic multiplication; A- B (mod N), of an integer multiplier, denoted A, with an integer multiplicand, denoted B, modulo an integer modulus, denoted N, using base r integer arithmetic and without performing an integer division operation, wherein at least one of A, B and N is a large integer, comprising: selecting a segment length, denoted k, wherein a segment is a k-character integer, and wherein a character is an integer between 0 and r-1 ; representing each of A, B and N in base r as a sequence of at least one segment; and performing the following operations at most m times: multiplying two k-character integers in base r; summing two k-character integers in base r; and adjusting a k-character base r integer so as to force its least significant character to be zero. 139,674/3
40. A method according to claim 39 wherein said adjusting a k-character integer operates by adding an integral multiple of N to the k-character integer.
41. A microelectronic circuit for performing a modular arithmetic multiplication. A-B (mod N), of an integer multiplier, denoted A, with an integer multiplicand, denoted B, modulo an integer modulus, denoted N, using base r integer arithmetic and without performing an integer division operation, wherein at least one of A, B and N is a large integer, comprising: memory registers storing representations of each of A, B and N in base r as a sequence of at least one segment wherein a segment is a k-character integer, and wherein a character is an integer between 0 and r-1, and wherein k is a pre-selected segment length; a multiplier multiplying two k-character integers in base r; an accumulator summing two k-character integers in base r; and a logical unit adjusting a k-character base r integer so as to force its least significant character to be zero.
42. A microelectronics circuit according to claim 41 wherein said multiplier multiplies one of the segments of A and one of the segments of B.
43. A microelectronics circuit according to claim 41 wherein said multiplying two k-character integers includes multiplying a k-character integer by a pre-computed constant Jo = -No"1 (mod rk), wherein No denotes the least significant segment of N.
44. A microelectronics circuit according to claim 41 wherein said accumulator performs carry sum addition.
45. A microelectronics circuit according to claim 41 wherein said logical unit adjusts a k-character integer by adding an integral multiple of N to the k-character integer.
46. A microelectronics circuit for performing a modular arithmetic exponentiation, AE(mod N), 139,674/3 of an integer, denoted A, raised to an integer power, denoted E, modulo an integer modulus, denoted N, using base r integer arithmetic and without performing an integer division operation, wherein at least one of A, E and N is a large integer, comprising: memory registers storing representations of each of A, E and N in base r as a sequence of at least one segment, wherein a segment is a k-character integer, and wherein a character is an integer between 0 and r-1, and wherein k is a pre-selected segment length; a multiplier multiplying two k-character integers in base r; an accumulator summing two k-character integers in base r; and a logical unit adjusting a k-character base r integer so as to force its least significant character to be zero.
47. A microelectronics circuit according to claim 46 wherein said logical unit adjusts a k-character integer by adding an integral multiple of N to the k-character integer.
48. A smart card comprising: a microelectronics circuit imprinted on the smart card for performing a modular arithmetic multiplication, A- B (mod N), of an integer multiplier, denoted A, with an integer multiplicand, denoted B, modulo an integer modulus, denoted N, using base r integer arithmetic and without performing an integer division operation, wherein at least one of A, B and N is a large integer, comprising: memory registers storing representations of each of A, B and N in base r as a sequence of at least one segment, wherein a segment is a k-character integer, and wherein a character is an integer between 0 and r-1, and wherein k is a pre-selected segment length; a multiplier multiplying two k-character integers in base r; an accumulator summing two k-character integers in base r; and a logical unit adjusting a k-character base r integer so as to force its least significant character to be zero. 139,674/3
49. A smart card according to claim 48 wherein said logical unit adjusts a k- character integer by adding an integral multiple of N to the k-character integer.
50. A public key encryption system comprising: a processor for performing a modular arithmetic multiplication, A- B (mod N), of an integer multiplier, denoted A, with an integer multiplicand, denoted B, modulo an integer modulus, denoted N, using base r integer arithmetic and without performing an integer division operation, wherein at least one of A, B and N is a large integer, comprising: memory registers storing representations of each of A, B and N in base r as a sequence of at least one segment, wherein a segment is a k-character integer, and wherein a character is an integer between 0 and r-1, and wherein k is a pre-selected segment length; a multiplier multiplying two k-character integers in base r; an accumulator summing two k-character integers in base r; and a logical unit adjusting a k-character base r integer so as to force its least significant character to be zero.
51. A public key encryption system according to claim 49 wherein said logical unit adjusts a k-character integer by adding an integral multiple of N to the k-character integer. 139674/1
52. A microelectronic apparatus for performing modular multiplication, squaring and reduction, the apparatus multiplying a multiplicand A by a multiplier B over a modulus N, wherein B is a serial fed radix 2^ multiplier comprising no more than k character multiplier segments, A comprises no more than k character multiplicand segments, and N has no more than k characters, each character having 1 bits, the apparatus comprising: a first (B) register operative to store the multiplier B; a modular multiplication device accepting multiplicands having no more than k characters, the modular multiplication device including a single accumulation device at least k characters long and operative to repeatedly receive a multiplicand and simultaneously output a character; a digital logic sensing detector operative to anticipate that a non-zero character would be about to be output from the single accumulation device and to determine a number of times, YQ, that the modulus N should be added into the single accumulation device so as to force the non-zero character to zero, the modular multiplication device operative, during a first phase, to switch into the single accumulation device, in turn, multiplicand values, and to receive, character by character, the contents of the B register and the YQ value from the digital logic sensing detector, thereby to force up to k first output characters which are zero, the multiplicand values switched in turn into the accumulation device comprising less than 3 of the following three multiplicands: (a) an all-zero string value; (b) a portion of the multiplicand A; and (c) at least a portion of the modulus N; and an output transfer mechanism, operative in a last phase to unload at least a portion of a final modular multiplication result from the accumulation device. 139,674/2 ,
53. Apparatus according to claim 1 for performing interleaved modular multiplication and reduction in a plurality of interleaved iterations, wherein the YQ value used in the first phase is saved, and wherein said portion of the modulus N comprises a k-character least significant portion thereof, the apparatus also comprising a second (S) register operative to store a temporary result S from an iteration i for use during a subsequent iteration i+1 and a third (N) register operative to store the modulus N, wherein n, the number of characters in the third (N) register, is larger than k; the modular multiplication device being operative, in a first phase, to multiply a plurality of slices of A during the plurality of interleaved iterations respectively, by B, the modular multiplication device being operative, during a second phase between the first and last phases, to switch into the single accumulation device, in turn, multiplicand values', and to receive multiplier values from the B and N registers, the multiplicand values switched in turn into the accumulation device comprising less than 3 of the following three multiplicands: (a) an all-zero string value; (b) a portion of the multiplicand A; and (c) the YQ value as saved from the first phase; the apparatus also comprising a serial addition device operative, during each iteration, to summate the temporary result value S in the second (S) register with the character output by the accumulation device, thereby to generate n-k least significant characters of a new temporary result, which characters are stored in the second (S) register, for the next in turn iteration.
54. Apparatus according to claim 52 or claim 53 wherein all addition, accumulation and multiplication operations are switcha-ble to be performed either with carries or without carries, over GF(p) or over GF(2<3) . 139,674/2
55. Apparatus according' to claim 52 or claim 53 which employs YQ as the next character of a polynomial based modular reducing quotient deterministically.
56. An apparatus as in claim 52 or claim 53 wherein the digital logic sensing detector is operative to receive the following four inputs : i. the product of the least significant character in the A register multiplied by a current value from the B register, in modulus 2^; ii . the first emitted carry out character from the accumulation device; iii. the contents of the second from the right character in the accumulation device; iv. the negative multiplicative inverse of the right- hand character in the N register.
57. An apparatus as in claim 53 wherein the digital logic sensing detector is operative to receive the following six inputs: i. the product of the least significant character in the A register multiplied by a current value from the B register, in modulus 2^ ; ii. the first emitted carry out character from the accumulation device; iii. the contents of the second from the right character in the accumulation device; iv. the negative multiplicative inverse of the right-hand character in the N register. v. the next in turn character in the S register; and vi . the carry out character from the serial addition device . 139674/1
58. A method for performing modular multiplication, squaring and reduction, including multiplying a multiplicand A by a multiplier B over a modulus N, wherein B is a serial fed radix 21 multiplier comprising no more than k character multiplier segments, A comprises no more than k character multiplicand segments, and N has no more than k characters, each character having 1 bits, the method comprising: storing a multiplier B in a first (B) register; providing a modular multiplication device accepting multiplicands having no more than k characters, the modular multiplication device including a single accumulation device at least k characters long and operative to repeatedly receive a multiplicand and simultaneously output a character; anticipating that a non-zero character would be about to be output from the single accumulation device and determining a number of times, YQ, that the modulus N should be added into the single accumulation device so as to force the non-zero character to zero, during a first phase, switching into the single accumulation device, in turn, multiplicand values, and receiving, character by character, the contents of the B register and the YQ value from the digital logic sensing detector, thereby to force up to k first output characters which are zero, the multiplicand values switched in turn into the accumulation device comprising less than 3 of the following three multiplicands: (a) an all-zero string value; (b) a portion of the multiplicand A; and (c) at least a portion of the modulus N; and in a last phase, unloading a final modular multiplication result from the accumulation device. 139674/1
59. A method according to claim 58 for performing interleaved modular multiplication and reduction in a plurality of interleaved iterations, wherein the YQ value used in the first phase is saved, and wherein said portion of the modulus N comprises a k- character least significant portion thereof, the method also comprising: providing a second (S) register operative to store a temporary result S from an iteration i for use during a subsequent iteration i+1 and a third (N) register operative to store the modulus N, wherein n, the number of characters in the third (N) register, is larger than k; the modular multiplication device being operative, in the first phase, to multiply a plurality of slices of A during the plurality of interleaved iterations respectively, by B, the modular multiplication device being operative, during a second phase between the first and last phases, to switch into the single accumulation device, in turn, multiplicand values, and to receive multiplier values from the B and N registers, the multiplicand values switched in turn into the accumulation device comprising less than 3 of the following three multiplicands: (a) an all-zero string value; (b) a portion of the multiplicand A; and (c) the YQ value as saved from the first phase , the method also comprising summating, during each iteration, the temporary result value S in the second (S) register with the character output by the accumulation device, thereby to generate a new temporary result, for the next in turn iteration .
60. A method according to claim 58 or claim 59 wherein all addition, accumulation and multiplication operations are switcha-ble to be performed either with carries or without carries, over GF(p) or over GF(2(3). 139674/1
61. A method according to claim 58 or claim 59 which deter-ministically employs YQ as the next character of a polynomial based modular reducing quotient.
Priority Applications (10)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IL13967400A IL139674A (en) | 2000-11-14 | 2000-11-14 | Extending the range of computational fields of integers and width of serial input operands in modular arithmetic public key cryptographic co-processors designed for elliptic curve and rsa type computations |
| KR1020027015396A KR100848412B1 (en) | 2000-05-15 | 2001-05-14 | Extending the range of computational fields of integers |
| DE60139401T DE60139401D1 (en) | 2000-05-15 | 2001-05-14 | ENLARGEMENT OF THE AREA OF COMPUTER BODIES OF ALL NUMBERS |
| US09/854,853 US7111166B2 (en) | 2000-05-15 | 2001-05-14 | Extending the range of computational fields of integers |
| PCT/IL2001/000425 WO2001089129A2 (en) | 2000-05-15 | 2001-05-14 | Extending the range of computational fields of integers |
| CNB018095992A CN1265280C (en) | 2000-05-15 | 2001-05-14 | Extending the range of computational fields of integers |
| JP2001585437A JP4955182B2 (en) | 2000-05-15 | 2001-05-14 | Integer calculation field range extension |
| EP01932038A EP1299797B1 (en) | 2000-05-15 | 2001-05-14 | Extending the range of computational fields of integers |
| AU58712/01A AU5871201A (en) | 2000-05-15 | 2001-05-14 | Extending the range of computational fields of integers |
| US11/497,496 US7904719B2 (en) | 2000-05-15 | 2006-08-01 | Extending the range of computational fields of integers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IL13967400A IL139674A (en) | 2000-11-14 | 2000-11-14 | Extending the range of computational fields of integers and width of serial input operands in modular arithmetic public key cryptographic co-processors designed for elliptic curve and rsa type computations |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| IL139674A true IL139674A (en) | 2009-12-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IL13967400A IL139674A (en) | 2000-05-15 | 2000-11-14 | Extending the range of computational fields of integers and width of serial input operands in modular arithmetic public key cryptographic co-processors designed for elliptic curve and rsa type computations |
Country Status (1)
| Country | Link |
|---|---|
| IL (1) | IL139674A (en) |
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2000
- 2000-11-14 IL IL13967400A patent/IL139674A/en not_active IP Right Cessation
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