IL126735A - צימצום סדר חלקי סטטי - Google Patents
צימצום סדר חלקי סטטיInfo
- Publication number
- IL126735A IL126735A IL12673597A IL12673598A IL126735A IL 126735 A IL126735 A IL 126735A IL 12673597 A IL12673597 A IL 12673597A IL 12673598 A IL12673598 A IL 12673598A IL 126735 A IL126735 A IL 126735A
- Authority
- IL
- Israel
- Prior art keywords
- state
- transitions
- states
- graph
- enabled
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Prevention of errors by analysis, debugging or testing of software
- G06F11/3604—Analysis of software for verifying properties of programs
- G06F11/3608—Analysis of software for verifying properties of programs using formal methods, e.g. model checking, abstract interpretation
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3323—Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Quality & Reliability (AREA)
- Software Systems (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Stored Programmes (AREA)
- Devices For Executing Special Programs (AREA)
- Debugging And Monitoring (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US6408097P | 1997-11-03 | 1997-11-03 | |
| US09/172,460 US6295515B1 (en) | 1997-11-03 | 1998-10-14 | Static partial order reduction |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| IL126735A0 IL126735A0 (en) | 1999-08-17 |
| IL126735A true IL126735A (he) | 2002-08-14 |
Family
ID=26744121
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IL12673597A IL126735A (he) | 1997-11-03 | 1998-10-23 | צימצום סדר חלקי סטטי |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6295515B1 (he) |
| EP (1) | EP0913781A3 (he) |
| JP (1) | JP2000207428A (he) |
| KR (1) | KR100335518B1 (he) |
| CA (1) | CA2250797A1 (he) |
| IL (1) | IL126735A (he) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7703077B2 (en) | 2002-04-30 | 2010-04-20 | Microsoft Corporation | Programming model to detect deadlocks in concurrent programs |
| US6889371B1 (en) * | 2002-06-04 | 2005-05-03 | Cadence Design Systems, Inc. | Method and apparatus for propagating a function |
| US8009726B2 (en) * | 2003-08-14 | 2011-08-30 | Broadcom Corporation | Carrier grouping in multi-carrier systems |
| US7526750B2 (en) * | 2003-10-15 | 2009-04-28 | Microsoft Corporation | Object-based systematic state space exploration of software |
| US7797669B1 (en) | 2004-02-13 | 2010-09-14 | Microsoft Corporation | Analysis of distributed software systems via specification substitution |
| US8266600B2 (en) * | 2005-03-28 | 2012-09-11 | Nec Laboratories America, Inc. | Model checking of multi threaded software |
| US20070005527A1 (en) * | 2005-06-06 | 2007-01-04 | Honeywell International, Inc. | Model reduction system and method for component lifing |
| US20070143742A1 (en) * | 2005-12-20 | 2007-06-21 | Nec Laboratories America | Symbolic model checking of concurrent programs using partial orders and on-the-fly transactions |
| US9063778B2 (en) * | 2008-01-09 | 2015-06-23 | Microsoft Technology Licensing, Llc | Fair stateless model checking |
| US20090222249A1 (en) * | 2008-03-03 | 2009-09-03 | Nec Laboratories America, Inc. | Modular verification of web services using efficient symbolic encoding and summarization |
| US8244516B2 (en) * | 2008-06-30 | 2012-08-14 | International Business Machines Corporation | Formal verification of models using concurrent model-reduction and model-checking |
| KR20100084036A (ko) * | 2009-01-15 | 2010-07-23 | 삼성전자주식회사 | 소프트웨어의 에러 검출 장치 및 방법 |
| US8839248B2 (en) * | 2010-05-28 | 2014-09-16 | International Business Machines Corporation | Synthesis of memory barriers |
| GB2547220A (en) * | 2016-02-10 | 2017-08-16 | Testplant Europe Ltd | Method of, and apparatus for, testing computer hardware and software |
| GB2547222A (en) * | 2016-02-10 | 2017-08-16 | Testplant Europe Ltd | Method of, and apparatus for, testing computer hardware and software |
| US10839124B1 (en) * | 2019-06-26 | 2020-11-17 | Amazon Technologies, Inc. | Interactive compilation of software to a hardware language to satisfy formal verification constraints |
| CN115185616B (zh) * | 2022-09-14 | 2022-12-13 | 深圳依时货拉拉科技有限公司 | 业务规则引擎装置及业务规则引擎的处理方法 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5163016A (en) * | 1990-03-06 | 1992-11-10 | At&T Bell Laboratories | Analytical development and verification of control-intensive systems |
| US5483470A (en) * | 1990-03-06 | 1996-01-09 | At&T Corp. | Timing verification by successive approximation |
| CA2147536A1 (en) * | 1994-06-01 | 1995-12-02 | Gerard Johan Holzmann | On-the-fly model checking with partial-order state space reduction |
| US5901073A (en) * | 1997-06-06 | 1999-05-04 | Lucent Technologies Inc. | Method for detecting errors in models through restriction |
-
1998
- 1998-10-14 US US09/172,460 patent/US6295515B1/en not_active Expired - Lifetime
- 1998-10-21 CA CA002250797A patent/CA2250797A1/en not_active Abandoned
- 1998-10-23 IL IL12673597A patent/IL126735A/he not_active IP Right Cessation
- 1998-10-27 EP EP98308793A patent/EP0913781A3/en not_active Withdrawn
- 1998-11-02 KR KR1019980046754A patent/KR100335518B1/ko not_active Expired - Fee Related
- 1998-11-04 JP JP10313128A patent/JP2000207428A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| EP0913781A2 (en) | 1999-05-06 |
| CA2250797A1 (en) | 1999-05-03 |
| US6295515B1 (en) | 2001-09-25 |
| IL126735A0 (en) | 1999-08-17 |
| EP0913781A3 (en) | 2001-02-21 |
| JP2000207428A (ja) | 2000-07-28 |
| KR100335518B1 (ko) | 2002-10-19 |
| KR19990066803A (ko) | 1999-08-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Clarke et al. | State space reduction using partial order techniques | |
| Kurshan et al. | Static partial order reduction | |
| US6295515B1 (en) | Static partial order reduction | |
| Peled | Combining partial order reductions with on-the-fly model-checking | |
| Buccafurri et al. | Enhancing model checking in verification by AI techniques | |
| Peled | Combining partial order reductions with on-the-fly model-checking | |
| Gueta et al. | Cartesian partial-order reduction | |
| Edelkamp et al. | Directed explicit-state model checking in the validation of communication protocols | |
| Holzmann et al. | The state of SPIN | |
| Hatcliff et al. | A formal study of slicing for multi-threaded programs with JVM concurrency primitives | |
| Iosif | Exploiting heap symmetries in explicit-state model checking of software | |
| Edelkamp et al. | Survey on directed model checking | |
| Bozga et al. | Using static analysis to improve automatic test generation | |
| Penczek et al. | Abstractions and partial order reductions for checking branching properties of time Petri nets | |
| Kurshan et al. | Combining software and hardware verification techniques | |
| Bošnački et al. | Partial-order reduction for general state exploring algorithms | |
| US6178394B1 (en) | Protocol checking for concurrent systems | |
| Fernandez et al. | State space reduction based on live variables analysis | |
| Du et al. | Local model checking and protocol analysis | |
| Fleischhack et al. | Computing a finite prefix of a time Petri net | |
| Iosif | Symmetry reductions for model checking of concurrent dynamic software | |
| Abdulla et al. | Forward reachability analysis of timed Petri nets | |
| Peled et al. | Relaxed visibility enhances partial order reduction | |
| Bošnački et al. | Partial-order reduction for general state exploring algorithms | |
| Letichevsky et al. | Semantics of message sequence charts |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FF | Patent granted | ||
| RH1 | Patent not in force |