IL123652A - Vocoder system for use in wireless telecommunication system - Google Patents

Abstract

A digital processor, comprising: a first input for receiving a downlink data frame comprising compressed downlink bearer data and control data; a second input for receiving non-compressed uplink bearer data; signal processing circuitry configured for generating non-compressed downlink bearer data by stripping said control data from said downlink data frame and decompressing said compressed downlink bearer data, and generating an uplink data frame by compressing said non-compressed uplink bearer data to generate compressed uplink bearer data and appending status data to said compressed uplink bearer data; a first output for transmitting said non- compressed downlink bearer data; and a second output for transmitting said uplink data frame. 83 כ" ז בסיון התשס" א - May 20, 2001

Description

r p iroiy Vocoder system for use in wireless telecommunications system Omnipoint Corporation C.110512 SPECIFICATION IMPROVED TRANSCEIVER ARCHITECTURES AND VOCODER INTERFACES FOR USE IN WIRELESS TELECOMMUNICATIONS SYSTEMS Field of the Invention The present invention relates to wireless telecommunications systems and, more particularly, to transceiver architectures and vocoder interfaces used within such systems.

Background of the Invention Recently, substantial attention has been directed to wireless telecommunications systems including, for example, cellular telecommunications systems and wireless local loop systems. Such systems generally include a plurality of remote units, for example, mobile radio units or customer premises radio units, and one or more base station (BS) units that are capable of communicating in a wireless fashion with the remote units and have the ability to establish and maintain communication links with a public service telephone network (PSTN) .

In some embodiments, the base station unit may communicate with the public service telephone network (PSTN) via a base station controller (BSC) , a transcoder unit (TCU) , and/or a mobile switching center (MSC) .

At a basic level, for voice data to be transmitted from a remote unit to a base station and from thereon to the public service telephone network, it is necessary to provide in the mobile unit or customer premises radio unit a signal processing system for converting analog voice signals to digital signals, compressing those signals and providing the compressed voice data to a radio transceiver. Similarly, it is necessary to provide a radio transceiver and signal processing system in the base station (or other network subsystem hardware, e,.g., a base station controller) , such that a radio frequency transmission may be converted into a compressed digital signal and thereafter decompressed for transmission over the public service telephone network (PSTN) .

It will be noted that the present invention is not directed to the algorithms used within signal processing systems to compress and decompress data, as such algorithms are considered to be well known in the art, and are described, for example, in ITU standards G.723 and G.729, each of which is hereby-incorporated by reference. . Rather, the present invention is directed to transceiver architectures and vocoder interfaces used within such systems and, in addition, to transceiver architectures and vocoder interfaces that may accommodate the use of virtually any known compression or decompression algorithm.

Summary of the Invention The present invention is directed to an improved signal processing system for use in wireless telecommunication systems and to improved data interface schemes for use within such systems .

In one innovative aspect, the present invention is directed to a wireless telecommunications transceiver comprising a digital signal processing circuit (or vocoder) , a control circuit coupled to the digital signal processing circuit, a radio interface circuit coupled to the control circuit, a dual port random access memory circuit coupled to the control circuit, a digital radio ASIC coupled to the radio interface circuit, and a microprocessor circuit coupled to the dual port random access memory, wherein the digital signal processing circuit compresses a pulse code modulated (PCM) signal having a first rate to a nominal, reduced rate or conversely expands a nominal, reduced rate voice data signal to a pulse code modulated format at the first rate, and wherein synchroniza ion signals, control and status are transferred in-band between the digital signal processing circuit and the control circuit.

In one preferred form, the rate of the pulse code modulated signal may be 64 Kbps, and the nominal, reduced rate may be 7.2 Kbps. In addition, forward error correction (FEC) coding may be applied to the compressed audio data signal to bring the aggregate data rate of the nominal, reduced frequency signal to 9.6 Kbps .

In other innovative embodiments, the digital signal processing circuit may be configured in several distinct compression modes. For example, the digital signal processing circuit may be configured to compress a 64 Kbps PCM signal using any of a number of preselected compression algorithms to a reduced, nominal rate and, conversely, to expand compressed data via one of several preselected expansion algorithms to a 64 Kbps PCM data format. Such compression algorithms may include, for example, Adaptive Differential Pulse Code Modulation (ADPCM) at a rate of 32 Kbps or 40 Kbps, and/or Personal Communication System (PCS) encoding at a rate of 8 Kbps or less (as described in the above-referenced ITU standards) .

In still other innovative embodiments, both synchronization and control/status information may be transferred "in-band" over a back haul line between the digital signal processing circuit (or vocoder) and the control circuit. Thus, in one preferred form data packets comprising a plurality of sync bytes, control or status bytes, and compressed data may be transferred between the digital signal processing circuit and the control circuit, irrespective of where the digital signal processing circuit resides in the overall telecommunications system (i.e., in a base station or some other network subsystem hardware such as a base station controller) . In exemplary preferred embodiments, the data packets may comprise two (2) bytes of sync information followed by ten (10) to fourteen (14) bytes of control/status information and twenty-four (24) bytes of compressed voice (or bearer) data.

Accordingly, it is an object of the present invention to provide an improved transceiver architecture for use in wireless telecommunications systems.

It is also an object of the present invention to provide an improved digital processing circuit (or vocoder) interface architecture for use in wireless telecommunications systems.

It is still another object of the present invention to provide improved data processing methodologies and improved data interface schemes for use in wireless telecommunications systems.

Brief Description of the Drawings Fig. 1 is a block diagram of an exemplary wireless communication network that is coupled to a public service telephone network (PSTN) .

Fig. 2 is a block diagram of an exemplary end-to-end voice path in an exemplary link between respective remote and base stations of a preferred wireless communication network.

Fig. 3 is a block representation of a preferred voice frame according to a preferred remote station and base station serial interface .

Fig. 4 is a block diagram of t*he voice path in a preferred remote station.

Fig. 5 is a block diagram of the voice path through a preferred base station and connected base station controller (or transcoder unit) , respectively, linked by a digital backhaul facility.

Fig. 6 is a block diagram of a first preferred transceiver system for use within a remote station.

Fig. 7 is a block diagram of a second preferred transceiver system for use in a base station and/or other network subsystem hardware .

Fig. 8 is a block diagram illustrating the functions performed by a digital signal processor circuit in accordance with a preferred form of the present invention.

Figs. 9(a) and 9(b) illustrate preferred data frames utilized in a digital signal processor/control circuit interface in accordance with a preferred form of the present invention.

Fig. 10 is a timing diagram for an interface between a digital signal processing circuit and control circuit in accordance with a preferred form of the present invention.

Fig. 11 is a timing diagram for an interface between a digital signal processing circuit and CODEC in accordance with a preferred form of the present invention.

Detailed Description of Preferred Embodiments Referring to Fig. 1, an exemplary communication network 10 includes a plurality of base stations 12, which may include one or more intelligent base stations Ϊ5, wherein each base station 12 and intelligent base station 15 is located within a respective geographic cell defined by cell boundaries 13. A plurality of independent (activated) remote stations 14 are distributed throughout the network 10, with multiple remote stations 14 typically located in a particular geographic cell at any given instant. The remote stations 14 may be mobile handsets or fixed customer premises radio units. L "While the inventions are described with reference to a voice application, the inventions are equally applicable to data applications.

The base stations 12, the intelligent base station 15 and the remote stations 14 each preferably comprise a radio transmitter and receiver, and preferably communicate with one another using a combination of time division multiple access ("TDMA" ), frequency division multiple access ("FDMA"), and code division multiple access ("CDMA") transmission techniques, respectively, preferably by employing a spread spectrum encoding format. For example, TDMA is preferably used to separate users within each geographic cell location. To provide greater area of coverage, or to provide greater capacity for densely populated regions, multiple or "sectorized" cells may be deployed using FDMA, thus separating cells by frequency. Further, to permit multi -cell deployments in a given region, CDMA may be used for each "RF link," (i.e., each over-the-air radio frequency signal link) , in order to reduce co-channel interference between nearby cells using the same RF carrier frequency. Spread spectrum may advantageously improve system response to RF channel impairments. Both FDD and TDD may be employed with any of these multiple access techniques.

In particular, the respective base stations 12 and intelligent base station 15 are used to perform the requisite over-the-air radio transmission and reception to remote stations 14 located within its cell area, and contain the equipment needed to communicate with the respective remote stations. In this regard, a base station 12 supports the over-the-air, terrestrial, and signaling links, respectively, necessary for fully linking a remote station 14 to an overlay network 20, such as, e.g., a public service telephone network ("PSTN") through personal communications switching network infrastructure 19 via interface 17. A base station 12 is connected, via back haul lines 18, to a respective base station controller ("BSC") 16, which preferably controls the two-way transmissions of a plurality of base stations 12 in order to more efficiently provide certain operations such as, e.g., call handoffs between base stations, bearer data encoding and decoding1, ' as well as general OAM&P ("operations, administration, maintenance & provisioning") support functions. An intelligent base station' 15 is intended herein to describe a base station which incorporates the features of both a standard base station 12 and a base station controller 16, respectively, in a single unit. The respective base station controllers 16 and intelligent base stations 15, in turn, are connected to the overlay network 20 via further back haul lines 21. In a typical preferred embodiment, an overlay network 20 will be connected to a multitude of base stations 12, either by way of a (smaller) number of base station controllers 16 or directly, where intelligent base stations 15 are employed. The respective back haul lines 18 and 21 are preferably dedicated (e.g., private or leased public), two-way DSO, DS1 or DS3 level facilities, depending on the particular traffic load requirements of the specific portion of the communication network 10.

To communicate with multiple remote stations 14 in its respective geographic cell, each base station 12 and intelligent base station 15 preferably employs over-the-air loop comprising a number of individual air channels, or "time slots", wherein each time slot may be used by a remote station 14 to communicate with the respective base station 12 and intelligent base station 15. In accordance with a preferred communication protocol an FDD protocol such as that embodied in the GSM standards may be employed. In accordance with another preferred communication protocol, a time division duplexing ("TDD") transmission mode technique is preferably employed, whereby both downlink -- i.e., in the base station to remote station transmission direction --and uplink -- i.e., in the remote station to base station transmission direction -- transmissions are carried over a common communication frequency path by employing time intervals for each respective signal transmission within a given time slot.

For example, in an exemplary preferred network embodiment employing a TDMA/TDD frame and time slot structure based on a 20 millisecond (ms) over-the-air loop and employing 2.5 Mega "chip" per second (Mcps) transmission rate, the 20 ms over-the-air loop is equally divided between 16 full duplex channels, with each resulting time slot channel being capable of supporting 9.6 Kbps full duplex digital data transmission between the respective base and remote stations. The first portion of each time slot channel is preferably allocated for a remote station frame transmission, and the second portion is preferably allocated for a base station frame transmission, respectively. After each respective base or remote frame transmission, a small portion of the time slot is preferably allocated to allow sufficient guard time for the transmitted signal to propagate back and forth to the respective receiver, e.g., based on the projected maximum geographic cell radius. In other words, even if there were perfect synchronization between , respective base and remote station transmission intervals, a guard time is still preferred to minimize the possibility of received and transmitted signals overlapping in time due to the varying transmission distances and atmospheric conditions within the geographic cell location.

Preferably, any time slot in over-the-air loop of a given base station 12 or intelligent base station 15 that is not already seized by a remote station 14 may contain a general poll command message transmitted by the respective base station 12 or intelligent base station 15 in that time slot's base station transmit interval. To acquire a time slot, a remote station 14 responds to a received general poll message in a remote station transmit interval. Upon receiving the response, the respective base station 12 or intelligent base station 15 may send a specific poll message in the next appearance of the same time slot in the over-the-air loop, which preferably includes a time slot (or time slots) assignment for communication between the remote station 14 and the base station 12 or intelligent base station 15, which may or may not be the same time slot used to transmit the general poll command message.

Referring to Fig. 2, in a manner described and disclosed in y.S. Patent Application Serial No. 08/749,105, Attorney Docket No. 211/238, filed on Novembet 14, 1996, and owned by the assignee of the present application, which is fully incorporated by reference herein, a synchronized communication path 22 between a respective remote station 14 and a respective base station 12 is preferably acquired and maintained via an over-the-air (OTA) time slot 24 of the over the air loop of the respective base station 12. In particular, the transmission timing of the respective base station 12 is synchronized to the overlay network 20, and the respective transmission timing of the remote station 14 is synchronized to the base station 12, respectively, so that periodic voice frames may thereafter be transmitted in each direction over the acquired time slot during the respective base and remote station transmit intervals. A general description of a voice path through the communication link 22 follows, where, for purposes of uniformity, transmission in the remote station-to-base station direction is referred to herein as "uplink" transmission, and transmission in the base station-to-remote station direction is referred to as "downlink" transmission.

In the uplink direction the remote station 14 transmits an analog (voice) signal 26, which is preferably converted by a CODEC circuit 28 into an uplink PCM data stream 30, preferably at a basic digital telephony rate of 64 Kbps. The uplink PCM data stream 30 is input into a remote station vocoder 32, which preferably encodes the PCM data in accordance with a selected voice compression algorithm, and then transmits the encoded PCM data in a series of respective uplink voice frames over a full duplex bus 38 to a remote station radio interface circuit 40, wherein a single voice frame is transmitted from the radio interface circuit 40 to the radio 42 during each remote station transmit interval of the respective acquired OTA time slot 24.

^ Likewise, in the downlink direction, respective downlink ' voice frames are transmitted from the remote station radio 42 to the radio interface circuit 40 during each base station transmit interval of the respective acquired OTA time slot 24. The 5 encoded data is then transferred from the radio interface circuit 40 to the vocoder 32 via bus 38. The respective downlink voice frames are decoded by the vocoder 32 into a downlink PCM data stream 34, preferably having the same transmission rate as the outgoing PCM data stream 30 -- i.e., 64 Kbps. The downlink PCM 10 data stream 34 is then converted into an analog (voice) signal 36 by the CODEC 28, which is received by the operator (not shown) .

More particularly, referring to both Fig. 2 and Fig. 3, the respective uplink and downlink voice frames transmitted over bus 15 38 are configured in accordance with a preferred 14.4 Kbps to 16 Kbps serial interface defined for transmission between the vocoder 32 and radio interface circuit 40, respectively. In accordance with this preferred serial interface, each voice frame 39 begins with a two byte sync pattern 41, which is preferably 20 selected so as to not be likely to represent bearer data, such as, e.g., preferably C3 hex (11000011) and A5 hex (10100101). The sync pattern 41 is followed by twenty-four bytes of bearer information 43 -- i.e., for a bearer data transmission rate of 9.6 Kbps in a preferred network employing a 20 msec base station 25 polling loop equally divided between 16 full duplex OTA channels. The bearer information bytes 43 are followed by ten to fourteen bytes of (non-compressed) control and status bytes 45, which are used for sending overhead and system level information between the respective remote station vocoder 32 and radio interface 30 circuit 40.

In a preferred embodiment, the bearer information 43 includes both encoded voice and error correction data in accordance with the selected algorithm employed by the vocoder 32. In alternate preferred embodiments, the bearer information 35 bytes 43 transmitted between the vocoder 32 and radio interface circuit 40 only include encoded voice, with the error correction information added to uplink voice frames or deleted from downlink ^ voice frames, respectively, at the remote station radio interface ™ circuit 40. In either case, however, the preferred serial interface includes a twenty- four byte bearer information field 43 in each voice frame 39 transmitted in either direction between 5 the respective vocoder 32 and radio interface circuit 40. In an alternative preferred embodiment the control/status information may precede the bearer information.

In the uplink direction, the sync pattern bytes 41 and control and status bytes 45, respectively, are preferably 10 stripped from each voice frame at the remote station radio interface circuit 40, with the twenty-four bytes of bearer data 43 transmitted over OTA slot 24 by a remote station radio 42 during the respective remote station transmit 'interval. Likewise, in the downlink direction, a respective twenty- four 15 bytes of bearer data (also designated as "43 ) is preferably received by the remote station radio 42 during each base station transmit interval. The received ( downlink) bearer data bytes 43 are forwarded to the remote station radio interface circuit 40, which preferably appends the two byte sync pattern 41 in 20 front of, and adds ten control and/or status data bytes 45 behind, respectively, the received bearer data bytes 43, to thereby form a complete downlink voice frame 39 in accordance with the defined serial interface.

At the base station end of the communication link 22, a base 25 station radio 44 receives the twenty-four bytes of uplink bearer data 43 transmitted from the remote station 14 over the OTA channel 24 during the respective remote station transmit intervals, and forwards the data to a base station radio interface circuit 46. The two byte sync pattern 41 is added in 30 front of, and ten control and/or status data bytes 45 are appended behind, respectively, the received uplink bearer data bytes 43 from the remote station 14, to thereby reform a complete uplink voice frame.

The uplink voice frames 39 are transmitted over a duplex bus 35 48 from the base station radio interface circuit 46 to a Tl interface module 50, which relays the respective voice frames 39 over a backhaul facility 18 to a corresponding Tl module 51 located at a respective base station controller (BSC) 16 or other network subsystem. From the BSC Tl module 51, the uplink voice frames 39 are preferably forwarded over a BSC duplex bus 52 to an assigned vocoder 54, which is one of several vocoders located at the BSC 16. The respective uplink voice frames 39 are decoded by the vocoder 54 into a (non-compressed) PCM data stream 58 having the same transmission rate as the remote station PCM data stream 30 -- i.e., preferably at 64 Kbps. The PCM data stream 58 is then preferably transmitted to a respective BSC line module 56 for further routing, e.g., over backhaul facility 21 to the overlay network 20. *· ' In the downlink direction, a downlink PCM data stream 60, which carries downlink bearer information intended for the respective remote station 14 via communication link 22, is transmitted from the BSC line module 56 to the respective vocoder 54. The vocoder 54 encodes the downlink PCM data from signal 60 in accordance with a selected voice compression algorithm and outputs the encoded data in a series of respective downlink voice frames 39, which are transmitted over duplex bus 52 to the BSC Tl module 51. The BSC Tl module 51 relays the downlink voice frames 39 to the respective base station Tl module 50, via the backhaul facility 18. From the base station Tl facility 50, the downlink data frames 39 are forwarded over bus 48 to the base station radio interface 46, which strips off the respective sync pattern bytes 41 and control and status bytes 45, with the twenty-four bytes of bearer data 43 of each downlink frame transmitted over OTA slot 24 during the respective base station transmit interval. The control and status bytes 45 are monitored by the protocol processor and appropriate control traffic messages are sent as part of the protocol (e.g. DTMF) .

To initially acquire and thereafter maintain vocoder synchronization, preferably after a synchronized OTA channel 24 has been acquired, the respective remote and base station vocoders 32 and 54 will each send respective uplink and downlink voice frames 39 during the respective remote and base station transmit intervals of the acquired time slot. Both vocoders 32 and 54 scan the respective incoming data, to detect the sync pattern 41. Upon detecting the sync pattern bytes 41, the respective vocoder 32 or 54 processes the ensuing thirty-four bytes of serial data as the initial bearer and control information, respectively, of a respective new incoming voice frame 39.

More particularly, referring to Fig. 4, the remote station vocoder 32 includes a first (non-encoded) data interface buffer 62, a digital signal processor ("DSP") 64 and a second (encoded) data interface buffer 66, respectively. Buffer 62 stores PCM data to be encoded from data stream 30 and recently developed PCM data to transmit as data stream 34,cbuffer 66 stores bearer data received from the radio interface circuit 40 to be decoded and encoded data to be transmitted to the radio interface circuit 40, and the DSP 64 performs the actual encoding and decoding, respectively.

Upon initially detecting the sync pattern 41, the remote station vocoder 32 resets respective counters (not shown) associated with the buffers 62 and 66, and begins a new voice frame cycle. In the "encode" direction, a frame's worth (the actual number of bytes or bits, in the frame will vary depending on the compression ratio by the vocoder) of (non-compressed) data from PCM data stream 30 will be acquired in buffer 62, a frame's worth (again the actual number of bytes or bits, in the frame will vary depending on the compression ratio by the vocoder) of (non-compressed) PCM data previously stored in buffer 62 will be received and encoded by DSP 64 into twenty-four bytes of bearer data, and twenty-four bytes of previously encoded bearer data is delivered from the buffer 66 to the remote station radio interface 40, respectively, along with the newly inserted sync pattern 41 and status bytes 45. In the "decode direction," the next serial clock count will deliver the first bit of bearer data of the respective incoming voice frame 39 into buffer 66. Once the bearer data bytes 43 are completely received into buffer 66, it is decoded by the DSP 64 and then transmitted serially as downlink PCM signal 34 to the CODEC 28 from buffer 62.

After the initial voice frame 39 is processed, the vocoder 32 looks for the sync pattern 41 to appear again, i.e., immediately following the initial frame 39 at the next base station transmit interval of the acquired time slot 24. If so, vocoder synchronization is established at the remote station 14 end of communication path 22. This process is repeated at each successive time slot interval, until the sync pattern 41 is not detected in its expected frame sequence location, indicating that a synchronization problem has occurred. When this occurs, the vocoder 32 returns to scanning the incoming data for the sync pattern 41 to appear at any time. The remote station vocoder 32 preferably mutes its non-compressed output while scanning for the sync pattern 41, or whenever a synchronization error is detected, e.g., by voiding the decoded downlink data rather than delivering it to the CODEC 28. The remote station radio interface 40 also preferably mutes its downlink voice frame transmissions to the vocoder 32 via a control bit whenever a synchronization change is required. To mask possible cases where the synch pattern 41 might occur randomly in the middle of a voice frame 39 synchronization changes are not made unless three consecutive frames indicate that the synchronization is not correct.

Referring to Fig. 5, the vocoder 54 at the BSC 16 includes a first (non-encoded) data interface buffer 68 connected to the line modules 56, a plurality of DSPs 70 and a second (encoded) data interface buffer 72 connected to the BSC Tl module 51, respectively. Buffer 68 stores PCM data to be encoded from data stream 60 and recently decoded PCM data to transmit as data stream 58, buffer 72 stores bearer data received from the base station radio interface circuit 46 to be decoded and recently encoded data to be transmitted to the radio interface circuit 46, and a selected DSP from the plurality of DSPs 70 performs the actual encoding and decoding, respectively, of the voice path data associated with the communication path 22.

Upon initially detecting the sync pattern 41, the selected DSP 70 resets respective counters (not shown) associated with buffers 68 and 72, and begins a (base station) new voice frame cycle. In the encode direction, a frame's worth (the actual number of bytes or bits, in the frame will vary depending on the compression ratio by the vocoder) of (non-compressed) data from PCM data stream 60 will be acquired in buffer 68, a frame's worth (the actual number of bytes or bits, in the frame will vary depending on the compression ratio by the vocoder) of (non-compressed) PCM data previously stored in buffer 68 will be received and encoded by the respective DSP 70 into twenty-four bytes of bearer data, and twenty-four bytes of previously encoded bearer data is delivered from the buffer 72 to the Tl module 51, respectively, along with the newly inserted sync pattern 41 and status bytes 45. In the decode direction, preferably the next serial clock count will deliver the first bit of bearer data of the respective incoming voice frame*"39 into buffer 72. Once the bearer data bytes 43 are completely received into buffer 72, the bearer data is decoded by the DSP 70 stored in buffer 68 and transmitted serially as downlink PCM signal 58 to the line module 56. Because the vocoder 54 is preferably located remotely from the respective base station 12, i.e., over the backhaul Tl facility 18, an extra delay of up to one over the air loop cycle, e.g., 20 msec is preferred for the transmission of the voice frames 39 in each direction between the base station radio interface 46 and the respective vocoder DSP 70.

Thus, methods and network architectures for the acquisition and maintenance of synchronization between vocoders on both ends of an established communication link in a remote communication network have been disclosed. For example, in a network employing a 5 Mcps transmission rate, with a 20 ms over the air loop is equally divided between 32 full duplex channels, each resulting time slot channel is capable of supporting 8 Kbps full duplex transmission between the respective base and remote stations. In this case, a bearer information field 43 of twenty bytes per voice frame 39 is preferably employed instead of twenty-four bytes .

Transceiver System Architecture Turning now to Fig. 6, a wireless transceiver system 100 in accordance with the present invention may include a coder/decoder circuit (CODEC) 112, a digital signal processing circuit (DSP) or vocoder circuit 114, a flash memory 115 coupled to the digital signal processing circuit 114, a fast serial random access memory (SRAM) coupled to the digital signal processing circuit 114, a control circuit 116, a radio interface circuit 118, a digital radio ASIC 120, a microprocessor 126, a dual port random access memory (DPRAM) coupled between the control circuit 116 and the microprocessor 126, a flash memory 127 coupled to the microprocessor 126, and a fast SRAM 129 coupled to the microprocessor 126.

The CODEC circuit 112 converts analog voice signals received, for example, from a microphone transducer or line module (not shown) to a digital format and delivers the digitally formatted signal to the digital signal processing circuit 114. The CODEC 112 also converts digital signals received from the digital signal processing circuit 114 to analog signals and transfers those signals to, for example, an audio transducer or line module.

The various functions performed by the digital signal processing circuit 114 are described in detail below. However, at a general level, the digital signal processing circuit 114 functions to compress and reformat digital data received from the CODEC 112 and deliver compressed reformatted data packets to the control circuit 116. The digital signal processing circuit 114 also functions to decompress and reformat digital data packets received from the control circuit 116 and deliver the decompressed reformatted data to the CODEC 112.

The control circuit 116 and radio interface circuit 118, which may be implemented separately or as a single ASIC, together provide frame and channel timing to implement the above-described TDMA/TDD or TDMA/FDD radio-control protocol. In addition, the control circuit 116 and radio interface circuit 118 control synchronization and channel tracking with an associated base station. The controller and radio interface circuits 116 and 118 also provide data framing and error detection functions.

The logic of the digital radio ASIC 120 implements those digital transmit and receive functions that are required to maintain communication between a remote transceiver unit and, for example, a base station unit. Moreover, the logic of the digital 123652/2 radio ASIC 120, in a spread spectrum environment, performs a despreading function in the receive direction along with demodulation and data extraction of received radio frequency (RF) signals.

In an encoding direction, data in a 64 Kbps PCM format is provided to the digital signal processor 114 via a serial DSP/CODEC interface 102. The architecture of the DSP/CODEC interface 102 includes a serial data uplink and a serial data downlink. The uplink and downlink transmit non-compressed bearer data between the CODEC 112 and the vocoder or digital signal processing circuit 114. The digital signal processing circuit 114 upon the filling of an uncompressed data buffer, begins its encoding operation and compresses the received data to a nominal, reduced rate of, for example, 7.2 Kbps. In a preferred form, forward error correction (FEC) data may be added to the reduce rate signal, increasing the rate thereof to 9.6 Kbps. The compressed data and FEC data is- sometimes referred to herein as bearer data. After a packet of compressed bearer data is generated by the digital signal processing circuit 114, the digital signal processing circuit 114 will add two (2) bytes of sync and ten (10) to fourteen (14) bytes of status information to the data packet and, in doing so, complete a data frame for transmission across a serial DSP/CNTL interface 106 to the control circuit 116. The architecture of the DSP/CNTL interface 106 includes a serial data uplink and a serial data downlink between the vocoder or digital signal processing circuit 114 and the control circuit 116. The uplink incorporates data frames including synchronization bytes, status bytes, and compressed bearer data byte. The downlink incorporates data frames including synchronization bytes, control bytes, arid compressed bearer data bytes. The control circuit 116, in turn, will strip the status and sync bytes from the data frame, and pass the packet of compressed bearer data to the radio interface circuit 118 6a for spreading in accordance with a spread spectrum spreading function, such as that described above. Then a spread chip stream will be transferred from the radio interface circuit 118 to the digital radio ASIC 120 and, from there, to a RF/IF transceiver 121 for broadcasting.

In the decoding direction, RF signals are received by the RF/IF transceiver 121 and provided to the digital radio ASIC 120. The digital radio ASIC 120, in turn, performs despreading, demodulation and data extraction functions upon the received RF signal, and provides the extracted compressed data together with sync information to the radio interface circuit 118 over a parallel receiver bus. The control circuit 116 and radio interface circuit 118 then, in combination with the microprocessor 126, configure frames of data, including two (2) bytes of sync, ten (10) to fourteen (14) bytes of control 17 information, and twenty-four (24) bytes of bearer data, for transmission to the digital signal processing circuit 114, such that the frames may be transferred to the digital signal processing circuit 114 across the serial DSP/CNTL interface 106. Finally, the digital signal processing circuit 114 will strip the sync and control bytes off of the received frame, load the received compressed bearer data packet into a compressed data buffer, and commence its decoding operation. Decoded PCM data is then transferred from the digital signal processing circuit 114 to the CODEC 112 across the serial DSP/CODEC interface 102 at a rate of 64 Kbps.

Turning now also to Fig. 7, a transceiver system 101 in accordance with the present invention may also be implemented using a parallel interface bus 134. In such an embodiment, compressed data packets are not transferred directly across a serial interface between the digital signal processing circuit 114 and control circuit 116. Rather, compressed data packets are transferred between the radio interface circuit 118, control circuit 116 and serial-to-parallel converter circuit 130 in parallel, while compressed data packets are transferred between the digital signal processing circuit 114 and serial-to-parallel converter 130 across a serial interface as described above.

Those skilled in the art will appreciate that, while the i transceiver architecture illustrated in Fig. 6 is preferably used in remote units (mobile handsets or " customer premises radio units) , and while the transceiver architecture illustrated in Fig. 7 is preferably used in base station (BS) units, the respective architectures are not limited to such uses and, indeed, are interchangeable.

Digital Signal Processing Circuit The digital signal processing circuit 114 may comprise a TI TMS320C5X DSP chip or equivalent device, and may be programmed to implement the functions described below. The TM320C5x DSP preferably operates at a maximum nominal frequency of 20.0 MHz with a divide by one option. The signal processing circuit 114 also preferably has a maximum performance of 20 MIPS at this clock rate. 18 The digital signal processing circuit 114 is preferably-capable of loading DSP applications from a byte-wide external EPROM or FLASH memory. The default DSP application (i.e. the PCS sub-rate speech coder/decoder described below) also preferably contains a bootloader function to lead the appropriate algorithm(s) into fast internal and external RAM and execute them.

In a preferred form, the digital signal processing circuit 114 may have four compression modes selectable via host command. The compression modes may include, for example, Personal Communications System (PCS) encoding at 7.2 Kbps; Adaptive Differential Pulse Code Modulation (ADPCM) at 32 Kbps; Adaptive Pulse Code Modulation (ADPCM) at 40 Kbps; and uLaw Pulse Code Modulation (PCM) at 64 Kbps. Moreover, the digital signal processing circuit 114 may receive compressed, formatted and synchronized data frames from the control circuit 116 and upon receipt of those frames generate, for example, 64 Kbps PCM voice data to the CODEC 112 using the PCS expansion algorithm, one of the two ADPCM expansion algorithms or the basic uLaw PCM algorithm. In addition, the digital signal processing circuit 114 may receive, for example, 64 Kbps PCM data from the CODEC 112 and compress that PCM data signaling using an algorithm selected by the control circuit 116 (i.e., a 64 Kbps uLaw PCM, 32 Kbps or 40 Kbps ADPCM, or PCS compression algorithm) . In a preferred form, the same compression mode is used for both encoding and decoding operations.

Data passed to and received from the digital signal processing circuit 114 may be synchronized and controlled by the control circuit 116 and preferably conforms to the framing structures defined below. External control inputs may be provided to instruct the digital signal processing circuit 114 to implement muting or soft decay (interpolation) of a voice output during periods of degraded channel conditions and where unacceptably high error rates are present (i.e., during blockage or hand-off conditions) . Status outputs may be provided to indicate performance characteristics of the digital signal 19 processing circuit 114 and/or forward error correction (FEC) count, if desired.

Depending upon the design criteria for a given wireless telecommunication system, the digital signal processing circuit 114 may also perform one or more of the following functions: (a) external frame synchronization between the control circuit 116 and the digital signal processing circuit 114 via in-band serial data; (b) interpolating and muting functions to provide limited audio degradation in the presence of errors; L ' (c) near end echo cancellation to minimize the effect of near end echoes; (d) microphone muting capabilities; (e) error correction coding to support reliable voice communication across the communication link when operated in a PCS mode; (f) dual tone multi-frequency (DT F) /call progress tone generation and detection; (g) programmable level setting for receive, transmit and sidetone loop voice paths; (h) parallel algorithm loading; (i) loop feedback testing; (j) voice activity detection/comfort noise generation; (k) echo suppression and tone disable detection (for fax and data modems) ; (1) voice/data encryption or decryption; (m) fax and data modem relay and related data applications.

Several of these functions are discussed below.

External Frame Synchronization The digital signal processing circuit 114, when operating in any of its compression modes, preferably accepts synchronization input from the control circuit 116. Preferably, the digital signal processing circuit 114 accepts the 20 synchronization signal via synchronization words in the serial control interface. However, the digital signal processing circuit 114 may accept the synchronization signal via an external, edge sensitive interrupt. The control circuit 116, depending upon its configuration, will provide one or the other of the synchronizing events.

Upon detecting a synchronization event, the digital signal processing circuit 114 preferably resets a compressed buffer pointer and an uncompressed buffer pointer to the beginning of their respective buffers (not shown) in order to receive a new frame of data. The next byte of dat'a" across the serial interface will be the first byte of data in the new compressed frame. After receiving a complete compressed frame, a decoder of the digital signal processing circuit 114 will execute immediately and begin to output the first byte of uncompressed speech to the CODEC 112. After an idle period required to finish filling the uncompressed data buffer, an encoder of the digital signal processing circuit 114 will execute immediately and begin to output the compressed data to the control circuit 116. The idle period and the encoder operation is preferably completed before the first byte of the next compressed frame is received from the control circuit 116. The amount of idle time required is preferably equal to 20 ms - decode time - encode time -miscellaneous delay times.

In a preferred form, a serial sync word capability is provided as described above. Moreover, the digital signal processing circuit 114 searches a serial data control stream for the sync word pattern. Once found, the digital signal processing circuit 114 will check the sync words as the first two bytes in every frame to ensure that synchronization is maintained. If the sync words are ever received in error, then the digital signal processing circuit 114 preferably attempts to re-synchronize and preferably mutes its speech output to the CODEC 112 until synchronization is re-established. 21 Interpolation Function The digital signal processing circuit 114, when operating in any of its compression modes, preferably provides an interpolation function to soften the effect of errors within the serial data stream. A cyclic redundancy check (CRC) error control register bit is preferably used to indicate to the digital signal processing circuit 114 that a previous frame of data was received in error by the control circuit 116. If a forward error correction (FEC) function of the digital signal processing circuit 114 is disabled, the digital signal processing circuit 114 will output a predicted 'voice pattern to the CODEC 112 instead of the data received from the control circuit 116. If the forward error correction (FEC) function is enabled, the FEC algorithm will preferably determine whether or not to interpolate the frame as described below with regard to the forward error correction/bit permutation function of the digital signal processing circuit 114.

In either mode, the digital signal processing circuit 114 is preferably capable of receiving up to five (5) consecutive bad frames and outputting a linearly attenuated version of a predicted voice pattern for each consecutive error. When the number of consecutive bad frames exceeds a threshold of, for example, five (5) , the digital signal processing circuit 114 preferably mutes its output to the CODEC 112. The reception of a single good frame, indicated by the clearing of the CRC error bit in the control register or the FEC and CRC check passing, immediately resets the digital signal processing circuit 114 out of interpolation mode (including any mute conditions created by the interpolation function) and the good frame of voice data is decoded and sent to the CODEC 112.

Preferably, only decoded data is affected by the interpolation function mode. Encoded data is preferably sent uninterrupted to the control circuit 116 side of the digital signal processing circuit 114.

Muting Function The digital signal processing circuit 114, when operating in any of its compression modes, preferably provides a muting function to generate silence when voice data is not being transferred by the control circuit 116. A muting control register bit forces the digital signal processing circuit 114 coder to output silence to the CODEC 112 instead of data received from the control circuit 116. The reception of a single voice frame, indicated by a clearing of the muting control bit in the control register, resets the digital signal processing circuit 114 out of muting mode and the received frame of voice data may then be decoded and sent to the CODEC 112. Preferably, only decoded data is effected by the muting function.

Echo Cancellation An echo canceler may be provided in accordance with ITU recommendation G.165, which specification is believed to be well known in the art and is hereby incorporated by reference. In a preferred embodiment, the maximum delay in the echo canceler path is 8 msec, however, the length of the delay is dependent upon the overall system architecture. The echo canceler preferably contains a double talk detector designed to prevent excessive reduction in cancellation while at the same time providing sufficient sensitivity and speed to prevent divergence during double talk.

Microphone Muting Function The digital signal processing circuit 114, when operating in any of its compression modes, preferably provides a microphone muting function to generate silence in the encoding direction when it is desired to mute voice transmission by the control circuit 116. A MIC-MUTE control register bit forces the speech coder of the digital signal processing circuit 114 to output silence to the control circuit 116 rather than data received from the CODEC 112 for a desired mute period. The microphone mute function, once initiated, is applied to each voice data frame sent to the control circuit 116. The reception of a single voice 23 frame with clearing of the MIC-MUTE bit in the control register immediately resets the digital signal processing circuit 114 coder out of microphone mute mode and any following frames of encoded voice data may then be sent to the control circuit 116. Preferably, only encoded data is affected by this mode.

Forward Error Correction/Bit Permutation Where a PCS sub-rate encoder/decoder algorithm is utilized by the digital signal processing circuit 114, Forward Error Correction (FEC) is preferably provided to enhance the performance of the PCS algorithm in^the presence of errors. The FEC function preferably utilizes 48 bits per frame (2.4 Kbps) to protect the 84 most perceptually significant bits within a frame.

The FEC is preferably implemented using four (21,31) BCH codes. The remaining 8 bits are preferably used for a CRC check on the 63 most perceptually significant bits.

The FEC algorithm preferably implements the following functions : 1. Polling of a control register to determine if the FEC error bit is set; (a) if the FEC error bit is set then the FEC decoder of the digital signal processing circuit 114 is enabled. When FEC is enabled, the interpolation bit described above is ignored and the interpolation function is controlled based upon the outcome of the FEC decoder; (b) in the event that the FEC error bit is disabled, the 192 bits are preferably returned to their original positions to undo any permutation, and no further processing is required; 2. Correction, where possible, of any errors in the 84 FEC code protected bits; 3. Following such correction, validation of the 63 most perceptually significant bits using an 8 bit CRC where, if the CRC fails, determination is made that a perceptually significant problem exists within the frame and the interpolation bit is set; 24 4. Insertion of the results of the CRC check into a FECF bit in a preselected status register; 5. Application of a 31 point finite impulse response (FIR) filter on a frame by frame basis to the CRC result from the above step such that if an uncorrected frame error rate exceeds 19 percent (6 counts out of 31) a muting bit is set, and remains set until the frame error rate falls below 13 percent (4 counts) ; and 6. Maintenance of 16 bit count registers for both the frame CRC error bit and the FECF bit, and incrementing the registers whenever a corresponding bit is set in a receive frame.

In addition to the FEC function, bit permutation is preferably performed by the digital signal processor encode operation to randomly distribute the 192 bits within a frame. This bit permutation function increases over-air voice quality by decreasing the probability that more than one bit in any field (i.e., pitch gain) will be corrupted by a single over-air error. Preferably, to give the FEC code the ability to handle burst errors, each bit within a code is separated from the other bits within the same code by at least 12 bits. The bit permutation function is preferably always enabled.

DTMF/Called Progress Tone Generation and Detection The digital signal processing circuit 114 preferably has the ability to generate and detect up to 31 tones including twelve dual tone multifrequency signals as defined in EIA/IS-19, which specification is believed to be well known in the art and is hereby incorporated by reference. Other tones preferably generated and/or detected include a 1 KHz test tone and call progress tones such as dial tone, busy signal and ringback tones. Dual tone multifrequency (DTMF) and call progress tones are preferably generated and detected to and from the CODEC 112 interface as shown in Fig. 8. The tone generation/detection is preferably maintained under host control via a plurality of registers (not shown) .

Programmable Level Control As shown in Fig. 8, the digital signal processing circuit 114 may include a first mixer 140, a transmission signal level control circuit 142, an encoding circuit 144, a PCM loop back circuit 146, a tone detection/tone generation circuit 148, a decoding circuit 150, a reception signal level control circuit 152, a second mixer 154, an echo canceler 156, a sidetone gain control circuit 158, and a control (CNTL) loop back circuit 160. The PCM sidetone path loops PCM data received from the CODEC 112 back to the CODEC 112, and the CNTL sidetone path loops encoded compressed data packets back1" to the CODEC 112. The mixer 140, transmission level control circuit 142, and encoding circuit 144 provide a transmission path for PCM data received from the CODEC 112, such that compressed encoded data having a nominal frequency of, for example, 8 Kbps, may be output to the control circuit 116. The decoding circuit 150, reception level control circuit 152, and mixer 154 provide a reception path, such that encoded data received from the control circuit 116 may be decoded and output as PCM data to the CODEC 112. A reception level control algorithm preferably also controls the gain level of decoded PCM data and/or dual tone multifrequency/call progress tones sent to the CODEC 112. Appropriate level settings for the transmission gain circuit 142 reception gain circuit 152 and sidetone gain circuit 158 are input to the digital signal processing circuit 114 from the control circuit 116 or microprocessor 126.

Control Circuit Interface The interface between the digital signal processing circuit 114 and the control circuit 116 is preferably based on synchronous bidirectional serial data transfer. However, a parallel interface may also be employed. The data transfer is synchronized by timing signals received from the control circuit 116, and compressed voice data is clocked in and out of the digital signal processing circuit 114 at a rate of 9.6 Kbps, 38.4 Kbps, 48.0 Kbps or 76.8 Kbps, depending on the selected mode of operation of the digital signal processing circuit 114 (i.e., 26 PCS, 32 Kbps or 40 Kbps ADPCM, or PCM respectively) . Extra bandwidth in the various modes (i.e., 38.4 Kbps or 32 Kbps ADPCM) is available for forward error correction (FEC) .

The frame size for data transmitted between the digital signal processing circuit 114 and control circuit 116 preferably matches that utilized by the wireless telecommunications transceiver system within which the digital signal processing circuit 114 operates. For example, where a PCS system utilizes a 20 msec superframe size, the frame size for data transferred between the digital signal processing circuit 114 and the control circuit 116 will preferably be 20 msec. The data rate is preferably guaranteed over each 20 msec period. Thus, for PCS, 24 bytes of compressed voice data will be transmitted or received by the digital signal processing circuit 114 every 20 msec; for 32 Kbps ADPCM signaling, 96 bytes of compressed voice data will be transmitted and/or received by the digital signal processing circuit 114 every 20 msec; for 40 Kbps ADPCM, 120 bytes of compressed voice data will be transmitted and/or received by the digital signal processing circuit 114 every 20 msec; and for PCM signaling, 192 bytes of compressed voice data may be transmitted and received by the digital signal processing circuit 114 every 20 msec.

Within the 20 msec data frame, however, data is preferably transferred to and from the digital signal processing circuit 114 in packets as it is received and sent by the control circuit 116.

As shown in Fig. 9(a), each packet of data preferably consists of two (2) sync bytes followed by ten (10) to fourteen (14) bytes of control/status information and twenty-four (24) bytes of voice data (or bearer data) . The ten (10) to fourteen (14) bytes following the voice in the receive direction shall be control information from the control circuit 116, and the ten (10) to fourteen (14) bytes following the voice data in the transmit direction are preferably status information from the digital signal processing circuit 114.

In an alternative embodiment shown in Fig. 9(b), the two (2) bytes of sync information may be followed by twenty-four (24) bytes of voice data (or bearer data) and ten (10) to fourteen (14) bytes of control/status information.

In a preferred form, sync signals are sent by the control circuit 116 to the digital signal processing circuit 114 to synchronize the control circuit 116 with the digital signal processing circuit 114, to indicate the first valid data bit of a new frame, and to reset the speech coder buffer pointers of the digital signal processing circuit 114 to the beginning of their respective buffers (not shown) .

Referring now to Fig. 10, the interface between the digital signal processing circuit 114 and the control circuit 116 preferably includes the following signals: TDX - Serial Transmit Data Output, clocked by the rising edge of the TCLK signal; TDR - Serial Receive Data Input, sampled by the falling edge of the TCLK signal; TCLK - a single clock input signal to be used for both the receive (TCLKR) and transmit (TCLKX) data, and having a rate preferably equal to 2.048 MHz; and TFS - a frame synchronization pulse input, used for both receive (TFSR) and transmit (TFSX) data, wherein FS is an active high pulse which is 1 period of TCLK in duration, . wherein the FS rate is preferably 8.0 KHz (nominal), and where 8 bits of data are preferably transferred after each FS.

In a preferred embodiment, an internal interrupt may be-generated after each byte or data (8 TCLK transitions) or word of data (16 TCLK transitions) which will cause the digital signal processing circuit 114 to read a byte of data just received and load the transmit shift register with the next byte of data to be transmitted. In addition, when the control circuit 116 is synchronized and is transferring voice data to the digital signal processing circuit 114, the rate of sync is preferably 50 Hz (every 20 msec) . 28 Protocol and Data Definition In a preferred form, each 20 msec frame may be made up of one, four, five or eight packets (two (2) sync bytes, twenty-four (24) bytes of compressed voice/FEC bearer data and ten (10) to fourteen (14) bytes of control/status data) depending upon which compression mode is selected. Where applicable, the control function (i.e., muting and interpolation) is applied to the previous 24 bytes of compressed voice in a packet, rather than for an entire 20 msec frame.

It will be appreciated by those skilled in the art that many different data framing structures may be supported by the digital signal processing circuit 114 of the present invention and that those described herein are merely exemplary. Presently preferred data framing structures include Pulse Code Modulation (PCM) pass-through, ADPCM and PCS. For PCM, the voice bit stream will be identical to that defined in the ITU G711 standard, which is believed to be well-known in the art, and is hereby incorporated by reference. For ADPCM, the voice bit streams are preferably identical to those defined in the ITU G726 standard, which is also well-known in the art and incorporated herein by reference. Finally, for PCS compression, the most significant bits within the serial data stream are protected by a variety of error correction codes, as is well-known in the art.

The number of speech frames per PCS superframe may be defined as follows. Where a PCS data structure is employed, the PCS frame is preferably 192 bits in length and conveys 20 msec of speech. The frame preferably corresponds to the Time Division Multiple Access (TDMA) slot size of the digital radio ASIC 120. Further, each PCS superframe may include two speech frames per user (one for transmit and one for receive) .

Where a 32 Kbps ADPCM frame structure is employed, the ADPCM frame size is preferably 125 μse (8 KHz) and the overall number of bits in each frame is four. The frame size for the control circuit 116 and the digital radio ASIC 120 (the TDMA slot size) is preferably 192 bits, and each PCS superframe (20 msec) preferably includes eight 192 bit speech frames per user (four for transmit and four for receive) . 29 Where a 40 Kbps ADPCM frame structure is employed, the ADPC frame size is preferably 125 ^sec (eight KHz) and the overall number of bits in each frame is preferably five. The frame size of the control circuit 116 and digital radio ASIC 120 (TDMA slot size) is preferably 192 bits, and each PCS superframe (20 msec) preferably includes ten 192 bit speech frames per user (five for transmit and five for receive) .

Where a 64 Kbps PCM frame structure is employed, the PCM frame size is preferably 125 ^usec (eight KHz) and the overall number of bits in each frame is eight. The frame size of the control circuit 116 and digital radio ASIC 120 (TDMA slot size) is preferably 192 bits, and each PCS superframe (20 msec) preferably includes sixteen 192 bit speech frames per user (eight for transmit and eight for receive) .

CODEC Interface The digital signal processing circuit 114 is coupled to CODEC 112 via a synchronous bi-directional serial interface. The data transfer is synchronized by timing signals received from the control circuit 116. The same clock and frame synchronization signals are used for transmit and receive functions.

In a preferred form, the frame rate is 8.0 KHz nominal, with 8 bits per word for an overall full-duplex data rate of 64 Kbps. The data to and from the CODEC 112 is preferably uLaw encoded. As illustrated in Fig. 11, the CODEC interface preferably includes the following signals: DX - serial transmit data output, clocked by the rising edge of the CLK signal; D - serial receive data input, sampled by the falling edge of the CLK signal; CLK - a clock input use for both receive (CLKR) and transmit (CLKX) data, wherein the clock rate is preferably 2.048 MHz (nominal), and wherein an internal interrupt is generated after each byte of data (eight (8) CLK transitions) causing the digital signal processing circuit 114 to read a byte of data 30 just received and load the transmit shift register with the next byte of data to be transmitted; and FS - frame synchronization pulse (TXM = 0) , used for both receive (FSR) and transmit (FSX) data, wherein FS is an active high pulse which is 1. of CL in duration, and wherein eight bits of data are transferred after each FS.

Further, in a preferred form, the CODEC interface is synchronized every 20 msec by the sync words from the control circuit 116.

Control Status Register Locations Each speech frame of compressed voice and/or forward error correction (FEC) data transferred across the interface between the digital signal processing circuit 114 and control circuit 116 is preferably preceded by two (2) sync bytes and ten (10) to fourteen (14) bytes of control or status information depending upon the direction of data flow. However, as indicated above, the bearer data may also be followed by the status and control bytes.

The tables set forth below provide an indication of relative locations of the control and status registers within each data packet .

TABLE 1 Compressed Voice Interface (CNTL to DSP, i.e. Rx Voice + Control) Byte 0 Sync Word #1 Control Sync Register #1 - 7 Byte 1 Sync Word #2 Control Sync Register #2 Byte 2 Data Format Control Register #1 Byte 3 Voice Control Control Register #2 Byte 4 Tone Control Control Register #3 Byte 5 Rx Level Control Control Register #4 Byte 6 Tx/Sidetone Level Control Control Register #4 Bytes 7-14 Spare Fill 31 Bytes 15-38 Compressed Voice and FEC Bearer Data (24 bytes) Byte 39 Duplicate of Control Control Register #6 Register #2 TABLE 2 Compressed Voice Interface (DSP to CNTL, i.e. Tx Voice + Status) Byte 0 Sync Byte #1 Status #1 Byte 1 Sync Byte #2 Status #2 Byte 2 Data Format Status Byte 3 Voice Status Status Byte 4 Tone Status Status Byte 5 Rx Level Status Status Byte 6 Tx/Sidetone Level Status Status Byte 7-14 Spare Fill Byte 15-38 Compressed Voice and FEC Bearer (24 bytes) Byte 39 Duplicate of Status Status Register #2 Control /Status Sync Register Definition The following is a bit definition of the synchronization bytes defined for both voice and data service operating modes. In both modes these words are generated by the control circuit 116 and sent to the DSP application as serial control bytes. The DSP application (voice or data) echoes these sync words as serial status bytes whenever the application is synchronized. 32 Sync Byte #1 (Control Sync Register #1) Synchronization Byte #1. Synchronization Bytes are provided in both control and status data streams to allow for CNTL/DSP application synchronization in system implementations where an external SYNC interrupt is not available. A unique pattern is preferably assigned to the Sync Byte registers and is detected by the DSP application. Sync Byte #2 = A5 hex.

Voice Mode Control Register Definition The following is a bit definition of all the control bytes defined for the voice mode.

Data Format (Control Register #1) DATA/VOICE: Voice or Data Mode selection bit. The DSP application shall read this bit and invoke the proper application. 1 - Data information is present. See Section 3.4.6.1 for bit definitions 0 - Voice information is present 33 M0DE2 , ODE1, MODE0 : Mode bits select which speech compression algorithm to use . 0,0,0 - PCS Sub-Rate Speech Coder 0,0,1 - 1,1,1 - Reserved Voice Control (Control Register #2) FECE: Forward Error Correction enable bit. 1 - FEC enabled (Normal operation) 0 - Disable FEC (CRCE controls Interpolate operation) CRCE: CRC Error Bit. Indicates that the current 24 bytes of voice to the decoder were received in error by the control circuit 116. The Interpolation algorithm should be applied to this voice if the FEC operation is disabled. 1 - Interpolate for the current 24 bytes of voice if FECE=0. Ignore if FECE=1 0 - Normal Operation MUTE: Mute the output to the CODEC 112 for the current 24 bytes of voice. 1 - Mute 0 - Normal Operation MIC MUTE: Mute the output to the control circuit 116 starting with the next frame. 1 - Mute 0 - Normal operation LPE: Loopback Enable Bit. Indicates that one of two loopback paths shall be enabled. 1 - Indicates that the loopback path shall occur. 0 - Normal operation LPM: Loopback Mode Bit. Indicates which type of loopback shall occur. 1 - Indicates that the loopback shall occur on the CODEC (PCM) interface. 0 - Indicates that the loopback shall occur on the DSP/CNTL interface.

ECE: Echo canceler enable bit 1 - Enable echo canceler (Normal operation) 0 - Disable echo canceler Tone Control (Control Register #3) TEST TONE ENABLE Test tone enable bit. This bit shall force the speech coder to disregard the incoming PCM data and instead insert a 1 KHz tone into the compressed output buffer. 1 - Generate test tone 0 - Normal operation 35 TONE VALID Tone generator enable bit . 1 - Generate tone selected by DTMF4 : 0 0 - Normal operation VOICE ENABLE Voice decoder output enable bit . 1 - Tone generator will add its output to the voice decoder output . 0 - Tone generator output will replace the voice decoder output (default) .

DTMF4-0: DTMF/Call Progress tone generation command. If TONE VALID = 1, generate the selected tone(s) starting with the next frame.

D4 D3 D2 Dl DO TONE (Freq. in Hz) 0 0 0 0 0 NONE (normal operation) 0 0 0 0 1 DTMF 1 (697+1209) 0 0 0 1 0 DTMF 2 (697+1336) 0 0 0 1 1 DTMF 3 (697+1477) 0 0 1 0 0 DTMF 4 (770+1209) 0 0 1 0 1 DTMF 5 (770+1336) 0 0 1 1 0 DTMF 6 (770+1477) 0 0 1 1 1 DTMF 7 (852+1209) 0 1 0 • to 0 DTMF 8 (852+1336) 0 1 0 0 1 DTMF 9 (852+1477) 0 1 0 1 0 DTMF * (941+1336) 0 1 0 1 1 DTMF 0 (941+1336) 0 1 1 0 1 DTMF A (697+1633) 0 1 1 1 0 DTMF B (770+1633) 0 1 1 1 1 DTMF C (852+1633) 1 0 0 0 0 DTMF D (941+1633) 1 0 0 0 1 DIAL TONE (350+440) 1 0 0 1 0 CALL INTERRUPT (440) 36 Receive Level (Control Register #4) Receive Level Control. Apply the following gain setting to decoded data being sent to the CODEC 112. 0000 = Mute output 0001 = -21 dB 0010 = -18 dB 0011 = -15 dB 0100 = -12 dB 0101 = -9 dB 0110 = -6 dB 0111 = -3 dB 1000 = 0 dB 37 1001 +3 dB 1010 +6 dB 1010 +9 dB 1011 +12 dB 1100 +18 dB 1111 +21 dB Transmit Level Control . Apply the gain setting to encoded data being sent to the control circuit 116. 000 = 0 dB 001 = +1 dB 010 = +2 dB 011 = +3 dB 100 = +4 dB 101 = +5 dB 110 = +6 dB 111 = +7 dB Sidetone Level Control. Apply the attenuation setting to 64 PCM data being looped from CODEC input to CODEC output . 000 = Infinite attenuation 001 = -26.5 dB 010 = -23.5 dB 011 = -20.5 dB 100 = -17.5 dB 101 = -14.5 dB 110 = 11.5 dB 111 = 8.5 dB Voice Mode Status Register Definition The following is a bit definition of all the status bytes defined for the voice mode.

Voice Format (Status Register #1) DATA/VOICE: Voice or Data Mode selection bit. 1 - Data information was processed. 0 - Voice information was processed.

MODE2 , MODE1, ODEO : Mode bits indicate which speech compression algorithm is in use. 0,0,0 - PCS Sub-Rate Speech Coder 0,0,1 - 1,1,1 - Reserved Voice Control (Status Register #2) Status of FEC enable bit. 1 - FEC enabled (Normal operation) 0 - Disable FEC (CRCE controls Interpolate operation) FEC Failure Bit. This bit indicates if the FEC was unable to correct the perceptually significant bits in the last received frame . 1 - FEC failed. The last frame had uncorrected perceptually significant bits. 0 - FEC succeeded. The last frame had error free perceptually significant bits.

Status of C C Error Bit. 1 - Last received OTA frame contained a CRC error. 0 - Last received OTA frame contained no CRC errors .

Status of the Mute bit . 1 - Muted 0 - Normal operation Status of the Microphone Mute bit. 1 - Muted 0 - Normal Operation Status of the Loopback Enable Bit . 1 - Indicates that a loopback path is enabled 0 - Indicates that a loopback path is not enabled Status of the Loopback Enable Mode Bit. This bit is only valid if LPE = 1. 1 - Indicates that loopback is occurring on the CODEC (PCM) interface. 0 - Indicates that loopback is occurring on the DSP/CNTL interface.

Status of the Echo Canceler Enable Bit 1 - Echo canceler is enabled 0 - Echo canceler is disabled Tone Control (Status Register #3) TEST TONE ENABLE Status of the Test Tone Enable bit. 1 - Incoming PCM data is being replaced by the test tone 0 - Normal operation DETECT VALID Tone Detected bit. This bit indicates if a valid tone was detected by the tone detector. 1 - Valid tone is being detected and DTMF4 : 0 indicate which tone. 0 - Valid tone is not being detected and DTMF4.-0 echo thQir control settings.

DTMF4-0 DTMF tone detection status. If DETECT VALID = 1, DTMF4 : 0 indicate the tone detected. If DETECT VALID = 0, then DTMF4 : 0 echo their control settings. Refer to Section 3.4.3.3 for a description of the valid tones .

Receive Level (Status Register #4) D7 D6 D5 D4 D3 D2 Dl DO Unused Unused Unused Unused RX3 RX2 RX1 RXO RX3-0: Receive Level Status. Indicates the gain setting of the decoded PCM data that was sent to the CODEC 112. 0000 — Mute output 0001 = -21 dB 0010 = -18 dB 0011 = -15 dB 0100 = -12 dB 0101 = -9 dB 0110 = -6 dB 0111 = -3 dB 1000 = 0 dB (default setting) 1001 = +3 dB 1010 = +6 dB 1011 = +9 dB 1100 = +15 dB 1101 = +18 dB 1111 +21 dB 1 Transmit/Sidetone Level (Status Register #5) TX2-0: Transmit Level Status. Indicates the gain setting of the encoded data being sent to the control circuit 116. 000 = 0 dB 001 = +1 dB 010 = +2 dB 011 = +3 dB 100 = +4 dB 101 = +5 dB 110 = +6 dB 111 = +7 dB ST2-0 Sidetone Level Status. Indicates the attenuation setting applied to the 64K PCM data being looped from CODEC input to CODEC output. 000 = Infinite attenuation 001 = -26.5 dB 010 = -23.5 dB 011 = -20.5 dB 100 = -17.5 dB 101 = -14.5 dB 110 = -11.5 dB 111 = -8.5 dB Data Services Mode Data Format Each frame of encoded data/FEC across the DSP/CNTL interface is preceded by two (2) sync bytes and ten (10) to fourteen (14) bytes of control or status information depending on the direction of data flow. The following tables indicate the relative locations of the control and status registers within each packet.

TABLE 3 Encoded Data Interface (CNTL to DSP, i.e. Rx Data + Control) 43 Byte 0 Sync Byte #1 Control Sync Register #1 Byte 1 Sync Byte #2 Control Sync Register #2 Byte 2 Data Format Control Register #1 Byte 3 Data Control Control Register #2 Byte 4 Spare Control Register #3 Byte 5 Spare Control Register #4 Byte 6 Spare Control Register #5 Byte 7 Spare Control Register #6 Bytes 8-31 Encoded Data and FEC Bearer Data (24 bytes) TABLE 4 Encoded Data Interface (DSP to CNTL, i.e. Tx Data + Status) Byte 0 Sync Byte #1 Control Sync Register #1 Byte 1 Sync Byte #2 Control Sync Register #2 Byte 2 Data Format Status Register #1 Byte 3 Data Status Status Register #2 Byte 4 Spare Status Register #3 Byte 5 Spare Status Register #4 Byte 6 Spare Status Register #5 Byte 7 Spare Status Register #6 Bytes 8-31 Encoded Data and FEC Bearer Data (24 bytes) Data Services Mode Control Register Definition The following is a bit definition of all the control bytes defined for the data services mode. 44 Data Format (Control Register DATA/VOICE: Voice or Data Mode selection bit. The DSP application shall read this bit and invoke the proper application. 1 - Data information is present. 0 - Voice information is present.

C2-C5: Data Rate control bits.

C6 : Data Services Mode 1 - Non-Transparent 0 - Transparent C7: Idle Status 1 - Note an Idle data frame 0 - Idle data frame Data Control (Control Register #2) D7 D6 D5 D4 D3 D2 Dl DO 45 FECE : Forward Error Correction enable bit. 1 - Enable FEC when decoding received data (Normal operation) 0 - Disable FEC when decoding received data CRCE: CRC Error Bit. Indicates that the current 24 bytes of data was received in error by the control circuit 116 1 - The current data frame contains a CRC error 0 - The current data frame contains no CRC errors LPE: Loopback Enable Bit . Indicates that one of two loopback paths shall be enabled. 1 - Indicates that the loopback path shall be enabled 0 - Normal operation LPM: Loopback Mode Bit . Indicate which type of loopback shall occur. 1 - Indicates that the loopback shall occur on the CODEC (PCM) interface. 0 - Indicates that the loopback shall occur on the DSP/CNTL interface.

Data Services Mode Status Register Definition The following is a bit . definition of all the status bytes defined for the data services mode.

Format (Status Register #1) 46 DATA/VOICE: Voice or Data selection bit. 1 - Data information was processed. 0 - Voice information was processed. C2-C5: Data Rate status bits.

C6 : Echo of Data Services Mode bit . 1 - Non-Transparent data was processed 0 - Transparent data was processed C7: Idle Status 1 Note an Idle data frame 0 - Idle data frame Data Status (Status Register #2) FECE: Echo of the FEC enable bit. 1 - FEC was used to decode the received data (Normal operation) 0 - FEC was not used to decode the received data FECF: FEC Failure Bit. This bit indicates if the FEC was unable to correct the errors in the last received data frame . 1 - FEC failed. 0 - FEC succeeded.

CRCE: Echo of the CRC Error Bit. Indicates that the last 24 bytes of data was received in error by the control circuit 116. 1 - The previous data frame contained a CRC error 0 - The previous data frame contained no CRC errors LPE : Echo of the Loopback Enable Bit. Indicates that one of two loopback paths is enabled. 1 - Indicates that the loopback path is enabled 0 - Normal operation LP : Echo of the Loopback Mode Bit. Indicates which type of loopback is occurring. 1 - Indicates that the loopback is occurring on the CODEC (PCM) interface. 0 - Indicates that the loopback is occurring on the DSP/CNTL interface.

While the invention is susceptible to various modifications and alternative forms, specific examples thereof have been shown 48 in the drawings and are herein described in detail . It should be understood, however, that the invention is not to be limited to the particular forms or methods disclosed, but to the contrary, the invention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the appended claims.

Claims (20)

- 49 - 123652/2 Claims :

1. A transceiver, comprising: a vocoder circuit; a control circuit; a first interface architecture having a serial data uplink and a serial data downlink between said vocoder circuit and said control circuit; wherein said serial data uplink incorporates frames of uplink data, each frame comprising a synchronization byte, a status byte, and a compressed bearer data byte; and wherein said serial data downlink incorporates frames of downlink data, each frame comprising a synchronization byte, a control byte, and a compressed bearer data byte .

2. The transceiver of claim 1, wherein: said first interface architecture further comprises a clock signal input having a predetermined rate; said serial data uplink is clocked by a rising edge of said clock signal; and said serial data downlink is clocked by a falling edge of said clock signal.

3. The transceiver of claim 1, wherein: each of said frames of downlink data comprises two synchronization bytes, fourteen status bytes and twenty-four bytes of compressed bearer data; and each of said frames of uplink data comprises two synchronization bytes, fourteen control bytes and twenty-four bytes of compressed bearer data.

4. The transceiver of claim 1, wherein said serial data uplink and said serial data downlink have a nominal rate of between 7.2 and 16.0 Kbps. - 50 - 123652/2

5. The transceiver of claim 1, wherein said serial data uplink and said serial data downlink are bidirectional.

6. The transceiver of claim 1, wherein said serial data uplink and said serial data downlink are parallel.

7. The transceiver of claim 1, wherein said status byte in said serial data uplink and said control byte in said serial data downlink are non-compressed.

8. The transceiver of claim 1, wherein said first interface architecture further comprises a backhaul line.

9. The transceiver of claim 1, further comprising: a CODEC circuit; a second interface architecture coupled between said CODEC circuit and said vocoder circuit, said second interface architecture comprising a second serial data uplink and a second serial data downlink; and wherein said second serial data uplink and said second serial data downlink comprise non-compressed bearer data.

10. The transceiver of claim 1, further comprising: a memory coupled to said control circuit; a microprocessor circuit coupled to said memory; a radio interface circuit coupled to said control circuit; and a digital radio ASIC coupled to said radio interface circuit .

11. The transceiver of claim 1, wherein said control circuit is configured to generate said control byte and said vocoder circuit is configured to generate said status byte . -51- 123652/1

12. A digital processor, comprising: a first input for receiving a downlink data frame comprising compressed downlink bearer data and control data; a second input for receiving non-compressed uplink bearer data; signal processing circuitry configured for generating non-compressed downlink bearer data by stripping said control data from said downlink data frame and decompressing said compressed downlink bearer data, and generating an uplink data frame by compressing said non-compressed uplink bearer data to generate compressed uplink bearer data and appending status data to said compressed uplink bearer data; a first output for transmitting said non-compressed downlink bearer data; and a second output for transmitting said uplink data frame .

13. The digital processor of claim 12, wherein said signal processing circuitry comprises a TI TMS320C5X DSP chip.

14. The digital processor of claim 12, wherein said signal processing circuitry operates in various compression modes.

15. The digital processor of claim 12, wherein: said compressed downlink bearer data and said compressed uplink bearer data each comprises pulse code modulated data at a rate of between 7.2 and 9.6 bps; and said non-compressed bearer downlink data and said non-compressed uplink bearer data each comprises pulse code modulated data at a rate of 64 Kbps.

16. The digital processor of claim 12, wherein said compressed downlink bearer data and said compressed uplink bearer data each comprises FEC data. - 52 - 123652/1

17. The digital processor of claim 12, wherein: said control data comprises data format, voice control, tone control, receive control and transmit/sidetone level control data; and said status data comprises data format, voice status, tone status, receive level status, and transmit/sidetone level status data.

18. A method for operating a vocoder circuit in a transceiver, comprising the steps of: receiving compressed downlink bearer data; generating a downlink data frame in said transceiver by appending synchronization data and control data to said compressed downlink bearer data; and generating non-compressed downlink bearer data in said vocoder circuit by stripping said synchronization data and said control data from said downlink data frame and decompressing said compressed downlink bearer data.

19. The method of claim 18, further comprising the steps of: receiving non-compressed uplink bearer data; generating an uplink data frame in said vocoder circuit by compressing said non-compressed uplink bearer data and appending synchronization data and status data to said compressed uplink bearer data; generating compressed uplink bearer data in said transceiver by stripping said synchronization data and status data from said uplink data frame; and transmitting said compressed uplink bearer data.

20. The method of claim 18, wherein said compressed downlink bearer data is pulse code modulated data. For the Applicants RBNHOLD COHN AND PARTNERS By j