IL116353A - Multiprocessing computer system - Google Patents

Multiprocessing computer system

Info

Publication number
IL116353A
IL116353A IL11635395A IL11635395A IL116353A IL 116353 A IL116353 A IL 116353A IL 11635395 A IL11635395 A IL 11635395A IL 11635395 A IL11635395 A IL 11635395A IL 116353 A IL116353 A IL 116353A
Authority
IL
Israel
Prior art keywords
computer system
multiprocessing computer
multiprocessing
computer
Prior art date
Application number
IL11635395A
Other languages
English (en)
Other versions
IL116353A0 (en
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of IL116353A0 publication Critical patent/IL116353A0/xx
Publication of IL116353A publication Critical patent/IL116353A/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30083—Power or thermal control instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Microcomputers (AREA)
  • Power Sources (AREA)
IL11635395A 1994-12-23 1995-12-12 Multiprocessing computer system IL116353A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/363,735 US5530932A (en) 1994-12-23 1994-12-23 Cache coherent multiprocessing computer system with reduced power operating features

Publications (2)

Publication Number Publication Date
IL116353A0 IL116353A0 (en) 1996-03-31
IL116353A true IL116353A (en) 1999-03-12

Family

ID=23431494

Family Applications (1)

Application Number Title Priority Date Filing Date
IL11635395A IL116353A (en) 1994-12-23 1995-12-12 Multiprocessing computer system

Country Status (10)

Country Link
US (1) US5530932A (https=)
EP (1) EP0799444B1 (https=)
KR (1) KR987001105A (https=)
CN (1) CN1145869C (https=)
AU (1) AU4962196A (https=)
BR (1) BR9510532A (https=)
IL (1) IL116353A (https=)
RU (1) RU2171490C2 (https=)
TW (1) TW293105B (https=)
WO (1) WO1996032671A1 (https=)

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US6014751A (en) * 1997-05-05 2000-01-11 Intel Corporation Method and apparatus for maintaining cache coherency in an integrated circuit operating in a low power state
US6085330A (en) * 1998-04-07 2000-07-04 Advanced Micro Devices, Inc. Control circuit for switching a processor between multiple low power states to allow cache snoops
US6105141A (en) * 1998-06-04 2000-08-15 Apple Computer, Inc. Method and apparatus for power management of an external cache of a computer system
US6347379B1 (en) * 1998-09-25 2002-02-12 Intel Corporation Reducing power consumption of an electronic device
US6438622B1 (en) 1998-11-17 2002-08-20 Intel Corporation Multiprocessor system including a docking system
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US7424576B2 (en) * 2001-05-02 2008-09-09 Intel Corporation Parallel cachelets
US6976181B2 (en) * 2001-12-20 2005-12-13 Intel Corporation Method and apparatus for enabling a low power mode for a processor
US7165135B1 (en) * 2002-04-18 2007-01-16 Advanced Micro Devices, Inc. Method and apparatus for controlling interrupts in a secure execution mode-capable processor
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US7685365B2 (en) * 2004-09-30 2010-03-23 Intel Corporation Transactional memory execution utilizing virtual memory
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DE602005026421D1 (de) * 2004-10-15 2011-03-31 Sony Computer Entertainment Inc Verfahren und vorrichtungen zur unterstützung mehrerer konfigurationen in einem mehrprozessorsystem
EP1812859B1 (de) * 2004-10-25 2009-01-07 Robert Bosch Gmbh Verfahren und vorrichtung zur modusumschaltung und zum signalvergleich bei einem rechnersystem mit wenigstens zwei verarbeitungseinheiten
ATE421120T1 (de) * 2004-10-25 2009-01-15 Bosch Gmbh Robert Verfahren und vorrichtung zur modusumschaltung und zum signalvergleich bei einem rechnersystem mit wenigstens zwei verarbeitungseinheiten
US7502948B2 (en) 2004-12-30 2009-03-10 Intel Corporation Method, system, and apparatus for selecting a maximum operation point based on number of active cores and performance level of each of the active cores
RU2290706C1 (ru) * 2005-05-14 2006-12-27 Научно-исследовательский институт системных исследований Российской Академии Наук Устройство чтения из кэш-памяти
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US7870337B2 (en) * 2007-11-28 2011-01-11 International Business Machines Corporation Power-aware line intervention for a multiprocessor snoop coherency protocol
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US8010822B2 (en) 2008-03-28 2011-08-30 Microsoft Corporation Power-aware thread scheduling and dynamic use of processors
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US9588881B2 (en) 2011-05-16 2017-03-07 Cypress Semiconductor Corporation Stack processor using a ferroelectric random access memory (F-RAM) for code space and a portion of the stack memory space having an instruction set optimized to minimize processor stack accesses
US9910823B2 (en) * 2011-05-16 2018-03-06 Cypress Semiconductor Corporation Stack processor using a ferroelectric random access memory (F-RAM) having an instruction set optimized to minimize memory fetch
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CN104345861B (zh) * 2013-08-07 2017-05-24 联想(北京)有限公司 一种数据处理方法和装置及电子设备
CN104657286B (zh) * 2013-11-19 2019-05-10 中兴通讯股份有限公司 一种分级存储方法及装置
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Also Published As

Publication number Publication date
BR9510532A (pt) 1998-07-14
AU4962196A (en) 1996-10-30
TW293105B (https=) 1996-12-11
EP0799444A1 (en) 1997-10-08
US5530932A (en) 1996-06-25
RU2171490C2 (ru) 2001-07-27
HK1003667A1 (en) 1998-11-06
EP0799444A4 (en) 1998-03-25
WO1996032671A1 (en) 1996-10-17
KR987001105A (ko) 1998-04-30
CN1171159A (zh) 1998-01-21
CN1145869C (zh) 2004-04-14
IL116353A0 (en) 1996-03-31
EP0799444B1 (en) 2003-12-03

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