IL110657A - Network switch - Google Patents

Network switch

Info

Publication number
IL110657A
IL110657A IL110657A IL11065794A IL110657A IL 110657 A IL110657 A IL 110657A IL 110657 A IL110657 A IL 110657A IL 11065794 A IL11065794 A IL 11065794A IL 110657 A IL110657 A IL 110657A
Authority
IL
Israel
Prior art keywords
input
output
fifo
channels
buffer
Prior art date
Application number
IL110657A
Other versions
IL110657A0 (en
Inventor
Elon Littwitz
Gavriel Ben-David
Haim Kurtz
Original Assignee
Ornet Data Communication Techn
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ornet Data Communication Techn filed Critical Ornet Data Communication Techn
Priority to IL110657A priority Critical patent/IL110657A/en
Publication of IL110657A0 publication Critical patent/IL110657A0/en
Priority to EP95930157A priority patent/EP0775346A4/en
Priority to PCT/US1995/010256 priority patent/WO1996005558A1/en
Priority to AU33639/95A priority patent/AU3363995A/en
Publication of IL110657A publication Critical patent/IL110657A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

Abstract

A network switch comprising: a two-way buffer (22) at least having one input and one output first in, first out (FIFO) buffer (23, 25) per channel large enough to store one frame portion; an internal bus (24) which receives said frame portions from said input FIFOs, wherein said internal bus has a timing sequence having a plurality of timing periods of which one timing period is allocated to each input FIFO; a storage buffer (26) comprising a multiplicity of storage FIFOs; and a switch controller (28) comprising: means for temporarily assigning each storage FIFO to collect frame portions from timing periods corresponding to one conversation, of the length of a frame, between one of a plurality of input channels and at least one of a plurality of output channels, wherein not all of said output channels are active at the same time; and means for transferring the oldest frame portions of each active output channels to its corresponding output FIFO of said two- way buffer for later transfer out to its active output channel, whereby the network switch is connectable (via 20) to said plurality of channels, each of which operates as an input and an output channel.
IL110657A 1994-08-14 1994-08-14 Network switch IL110657A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IL110657A IL110657A (en) 1994-08-14 1994-08-14 Network switch
EP95930157A EP0775346A4 (en) 1994-08-14 1995-08-11 A network switch
PCT/US1995/010256 WO1996005558A1 (en) 1994-08-14 1995-08-11 A network switch
AU33639/95A AU3363995A (en) 1994-08-14 1995-08-11 A network switch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IL110657A IL110657A (en) 1994-08-14 1994-08-14 Network switch

Publications (2)

Publication Number Publication Date
IL110657A0 IL110657A0 (en) 1994-11-11
IL110657A true IL110657A (en) 1997-07-13

Family

ID=11066456

Family Applications (1)

Application Number Title Priority Date Filing Date
IL110657A IL110657A (en) 1994-08-14 1994-08-14 Network switch

Country Status (4)

Country Link
EP (1) EP0775346A4 (en)
AU (1) AU3363995A (en)
IL (1) IL110657A (en)
WO (1) WO1996005558A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5802333A (en) * 1997-01-22 1998-09-01 Hewlett-Packard Company Network inter-product stacking mechanism in which stacked products appear to the network as a single device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4788679A (en) * 1986-09-02 1988-11-29 Nippon Telegraph And Telephone Corporation Packet switch with variable data transfer rate links
DE3788649T2 (en) * 1987-10-20 1994-06-23 Ibm Fast modular switching facility for through-traffic and packet-switched traffic.
US5274631A (en) * 1991-03-11 1993-12-28 Kalpana, Inc. Computer network switching system
US5168492A (en) * 1991-04-11 1992-12-01 Northern Telecom Limited Rotating-access ATM-STM packet switch
EP0531599B1 (en) * 1991-09-13 1998-07-22 International Business Machines Corporation Configurable gigabit/s switch adapter
US5241536A (en) * 1991-10-03 1993-08-31 Northern Telecom Limited Broadband input buffered atm switch
US5291482A (en) * 1992-07-24 1994-03-01 At&T Bell Laboratories High bandwidth packet switch

Also Published As

Publication number Publication date
AU3363995A (en) 1996-03-07
EP0775346A4 (en) 1999-09-22
IL110657A0 (en) 1994-11-11
WO1996005558A1 (en) 1996-02-22
EP0775346A1 (en) 1997-05-28

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Legal Events

Date Code Title Description
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KB Patent renewed
MM9K Patent not in force due to non-payment of renewal fees