IL102904A - Configurable imaging processor - Google Patents

Description

102904/2 CONFIGURABLE IMAGING PROCESSOR STATE OF ISRAEL- MINISTRY OF DEFENCE •ρηΌΐπ TWO -!wivy nmn Inventor: Israel Herscovich C: 13509 13509isr.her 1-9021 19aug92 FIELD OF THE INVENTION The present invention relates to imaging processors generally and to configurable imaging processors in particular.

BACKGROUND OF THE INVENTION Configurable image processors are known in the art. One such configurable processor is the Video Signal Processor (VSP) manufactured by Silicon and Software Systems of Dublin, Ireland. The VSP consists of video line delays and high speed binary template matchers. The processor can be configured, through programming to process the image with up to eight separate template windows and it can work on part of the image or on the entire image.

Another configurable imaging processor is the L 64250 Histogram/Hough Transform Processor, manufactured by LSI Logic Corporation of Milipitas, California of the USA. The L 64250 is an imaging processor which performs histograms and/or modified Hough transforms on images. The user can use the L64250 to implement one or more algorithms utilizing histograms and/or modified Hough transforms. The L 64250 operates with a dynamic range of a maximum of nine bits.

Israel Patent Publication 67268 to Hughes Aircraft Company describes an imaging processor which calculates histograms, processes them to create a mapping between an input image and an output image which maintains the gross statistics of the input image and filters the input image based on the calculated mapping.

U.S. Patent ^ , 365.30^ to Ruhman et al describes a method and apparatus for on-line data enhancement. The apparatus is a circuit which implements histogram transformation according to a desired output histogram distribution. 13509isr.her 1-9021 19aug92 FIELD OF THE INVENTION The present invention relates to imaging pi generally and to configurable imaging processors in partic.

BACKGROUND OF THE INVENTION Configurable image processors are known in the art. such configurable processor is the Video Signal Processor (\ manufactured by Silicon and Software Systems of Dublin, Irelai The VSP consists of video line delays and high speed bina. template matchers. The processor can be configured, throug. programming to process the image with up to eight separate template windows and it can work on part of the image or on the entire image.

Another configurable imaging processor is the L64250 Histogram/Hough Transform Processor, manufactured by LSI Logic Corporation of Milipitas, California of the USA. The L64250 is an imaging processor which performs histograms and/or modified Hough transforms on images. The user can use the L64250 to implement one or more algorithms utilizing histograms and/or modified Hough transforms. The L64250 operates with a dynamic range of a maximum of nine bits.

Israel Patent Publication 67268 to Hughes Aircraft Company describes an imaging processor which calculates histograms, processes them to create a mapping between an input image and an output image which maintains the gross statistics of the input image and filters the input image based on the calculated mapping .

U.S. Patent 4,365,30^ t Ruhman et al describes a method and apparatus for on-line data enhancement. The apparatus is a circuit which implements histogram transformation according to a desired output histogram distribution. 1 SUMMARY OF THE INVENTION It is an object of the present invention to provide a high dynamic range, configurable imaging processor.

It is a further object of the present invention to provide an imaging processor performing dynamic range monitoring of images using an adaptive gap removal process on histograms.

It is a further object of the present invention to provide an imaging processor with a Built-in-Test unit for performing tests on single functional elements of the processor as well as on groups of functional elements of the processor during the blank periods in the video signal, so that the testing generally does not disturb the image on the screen.

Another object of the present invention is to enable the hardware to degrade gracefully in the presence of errors.

There is therefore provided, in accordance with a preferred embodiment of the present invention, apparatus for processing a video signal operating in conjunction with memory external to the apparatus. The apparatus includes a) a histogram creator capable of performing a multiplicity of types of histograms to be stored in the external memory from an input signal, wherein each type of histogram has its own memory requirement thereby providing an operator with a tradeoff between amount of external, memory to be utilized and type of histogram to be produced and b) a configurer which configures the histogram creator, in accordance with the selected tradeoff, to perform one of the multiplicity of histograms.

Additionally, in accordance with a preferred embodiment of the present invention, the configurer comprises a multiplicity of configurable selectors which can be updated, during operation, in accordance with an input configuration signal.

Further, in accordance with a preferred embodiment of the present invention, the multiplicity of histograms includes at least one of: standard histograms, a histogram whose number of pixels at any intensity level does not exceed a selected threshold level, thereby providing a histogram for an input signal 2 having a large number of pixels, and a histogram wherein each point on the absissca of the histogram represents a consecutive group of intensity levels, thereby providing a histogram for an input signal having a wide dynamic range.

Still further, in accordance with a preferred embodiment of the present invention, the apparatus of the present invention includes microprocessor apparatus for processing the histogram. It can also include lookup table (LUT) apparatus for receiving a LUT from the microprocessor and for processing the video signal with the LUT.

There is also provided, in accordance with a further embodiment of the present invention, apparatus for processing a video signal having blank periods. The apparatus includes a) a multiplicity of video processing units, b) a built-in- testor (BIT) having associated therewith a multiplicity of test signals, each corresponding to at least one processing unit, whereby during one of the blank periods, the BIT provides at least one of the test signals to its at least one corresponding processing unit and receives an output signal from the corresponding processing unit responsive to the at least one test signal and c) a BIT processor capable of indicating proper functioning of the at least one corresponding processing unit based on analysis of the output signal.

Additionally, in accordance with the further embodiment of the present invention, the BIT testor comprises a controller operative to measure an amount of time the at least one corresponding processing unit processes the at least one test signal.

Moreover, in accordance with a preferred embodiment of the present invention, the BIT processor includes a configurer connected to the multiplicity of processing units whereby the configurer reconfigures the connections of the multiplicity of processing units to bypass a processing unit identified by the BIT processor identifies as improperly functioning.

There is provided, in accordance with an alternative embodiment of the present invention, apparatus for processing a video signal comprising a) a histogram creator which produces a 3 multiplicity of thresholded histograms of an input signal, each histogram produced with a different threshold value, b) a percentage loss calculator responsive to each of the thresholded histograms, c) a loss level maintainer which selects a threshold level corresponding to a desired percentage loss wherein a thresholded histogram having the selected threshold level has gaps therein, d) a gap remover responsive to the selected threshold histograms for creating gap removed histograms, e) a LUT creator responsive to the gap removed histograms for creating a LUT and f) a LUT mapper for mapping the video signal in accordance with the LUT.

Additionally, in accordance with the alternative embodiment of the present invention, the apparatus includes a dynamic range monitor repeatedly operating the histogram creator, the percentage loss calculator and the loss level maintainer to change the threshold level as the video signal changes, thereby to maintain the desired percentage loss.

There is still further provided, in accordance with the present invention, an imaging processor including a) a multiplicity of processing units, b) a configurer connected to each of the processing units and c) a microprocessor, whereby the microprocessor performs some processing operations and the processing units perform other processing operations and the microprocessor provides parameters to the processing units and selectably connects the processing units to each other via the configurer.

There is also provided, in accordance with the present invention, an imaging processor including a) a multiplicity of processing units formed on a single integrated circuit chip, b) external memory, and c) microprocessor, whereby the processing units store output in the external memory, the size of the microprocessor and the size of the external memory are selectable, the microprocessor and the external memory are connectable to the single integrated circuit chip, and whereby the microprocessor is operable to selectably configure the multiplicity of processing uni ts .

There is still also provided, in accordance with an 4 alternative embodiment of the present invention, a method for dynamic range monitoring of video signals including therein grey levels. The method includes the steps of a) selecting a multiplicity of threshold levels and producing therefrom a multiplicity of thresholded histograms of a single image of a video signal, each with a different one of the multiplicity of threshold levels, b) calculating from each thresholded histogram a percentage loss level or the number of remaining grey levels, d) selecting a threshold level corresponding to a desired percentage loss level or a desired number of remaining grey levels, wherein the thresholded histogram having the desired loss level has gaps therein, e) removing the gaps from the thresholded histogram and producing therefrom a gap removed histogram, f) creating a LUT corresponding to the gap removed histogram and g) mapping the video signal with the LUT.

Finally, in accordance with the present invention, the methods also include the step of continuously repeating the steps of selecting, calculating and selecting thereby to maintain the desired percentage loss level or the desired number of remaining grey levels as the quality of the video signal changes. 5 BRIEF DESCRIPTION OF THE DRAWINGS AND ANNEXES The present invention will be understood and appreciated from the following detailed description, taken in conjunction with the drawings and annexes in which: Fig. 1 is a block diagram illustration of a configurable imaging processor constructed and operative in accordance with a preferred embodiment of the present invention; Fig. 2 is a block diagram illustration of a preprocessor forming part of the imaging processor of Fig. 1; Fig. 3 is a block diagram illustration of a histogram generator forming part of the imaging processor of Fig. 1; Fig. 4 is a block diagram illustration of a LookUp Table (LUT) generator forming part of the imaging processor of Fig. 1; Fig. 5 is a block diagram illustration of a postprocessor forming part of the imaging processor of Fig. 1; Fig. 6 is a block diagram illustration of a configuration element forming part of the imaging processor of Fig. 1; Fig. 7 is a block diagram illustration of a built-in-test unit forming part of the imaging processor of Fig. 1; 6 Fig. 8 is a block diagram illustration of an adaptive gap removed histogram unit utilizing the elements of the imaging processor of Fig. 1; Fig. 9A is a graphical illustration of a histogram and a threshold level, useful in understanding the operation of the gap removed histogram filter of Fig. 8; Fig. 9B is a graphical illustration of a percent loss of signal calculation based on reduced threshold levels on the histogram of Fig. 9A; Fig. 9C is a graphical illustration of a thresholded histogram having gaps therein; Fig. 9D is a graphical illustration of a gap removed histogram of the histogram of Fig. 9C; Fig. 10 is a block diagram of an Application Specific Integrated Circuit (ASIC) implementing the imaging processor of Fig. 1; Annex A is a pseudo code description of the operation of the imaging processor of Fig. 1; and Annex B is source code for implementing the adaptive gap removed histogram unit of Fig. 8. 7 DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT Reference is now made to Fig. 1 which illustrates, in block diagram format, a configurable imaging processor 10, constructed and operative in accordance with a preferred embodiment of the present invention.

The imaging processor 10 typically comprises a preprocessor 12, for receiving an N bit video signal representing an image 14 and for filtering the N bit video signal, as desired, to produce an N+r bit signal. N is typically 12, r is typically 4 and the image 14 is usually an analog video signal which is converted via an analog- to-digi al converter 16 to produce the N bit digital video signal.

Optionally, a pre-conditioner 17, such as a direct current (DC) restorer (DCR) , can be utilized prior to the preprocessor for pre-conditioning the signal to restore the DC of the video signal. In the optional embodiment, the output of the pre-conditioner is an N+q bit signal and the output of the preprocessor is an N + q + r bit signal, where q is typically 2. For the purposes of the remaining discussion, we will say that the output of the preprocessor has J bits, where J is either N+q or N+q+r.

The imaging processor 10 also comprises a histogram generator 18 for generating a histogram of the J bit signal, a Lookup Table (LUT) processor 20 for processing the J bit signal using a LUT mapping is based on the shape of the histogram, and a post-processor 22 for operating on the J bit signal and on the output of the LUT processor 20 and for producing therefrom a reduced dynamic range, m bit signal, where m is typically 8.

The histogram generator 18 and the LUT processor 20 both typically operate with external memory, in the form of buffers 21 and 23, respectively. If necessary, buffer 23 can comprise two buffers for performing double buffering.

The output of the imaging processor 10, the m bit signal, is typically provided to a display device 24, such as a monitor, or to another image processor 26 for further processing. An example image processor 26 is a vision system, having limited 8 precision, for performing image analysis.

The imaging processor 10 further comprises a Built-in-Test (BIT) unit 27 for testing the operation of the imaging processor 1G, both before and during operation. The BIT unit 27 tests each element of the imaging processor 10 individually and in combination, thereby to detect faults in the operation of the processor 10.

The imaging processor 10 is controlled by a microprocessor 28, such as a 1286 processor manufactured by Intel of the U.S.A. , which communicates with the imaging processor 10 via a microprocessor interface 30· The microprocessor interface 30 is, in turn, connected to five interfaces 32, 3 36, 37 and 39 which respectively connect to the BIT unit 27, the histogram generator l8, the LUT processor 20, buffer 21 and buffer 23 via an internal bus. The internal bus is not shown for the purposes of clarity. However, the internal bus connections are illustrated with the signals A, B and C.

Through the interfaces 30 " 37· which typically comprise buffers and processing circuitry, the microprocessor 28 provides control signals to the imaging processor 10, receives data from the histogram generator 18 and from the BIT unit 27 and provides data to the LUT processor 20.

Specifically, the microprocessor interface 30 receives all control signals from the microprocessor 28 and directs them to the appropriate interface. The appropriate interface 32 - 39 then encodes the control information and sends it to its corresponding processing unit via the internal bus. Output from a processing unit is sent, via the internal bus to the appropriate interface which, in turn, decodes the signal and sends it to the microprocessor 28 via the microprocessor interface 30.

In accordance with the present invention, the BIT interface 32 operates to ensure that the BIT unit 27 only operates during a blank period of the input video signal.

In accordance with a preferred embodiment of the present invention, the microprocessor interface 30 is also connected to a configuration unit 38 for configuring the elements of 9 the processor 10 into a desired connection thereby to perform a desired image processing operation.

The configuration unit 38 receives configuration information from the microprocessor 28 and provides it to the relevant ones of the pre-processor 12 , the histogram generator 18 , the LUT processor 20 , the post-processor 22 and/or the BIT 27 . For example, if pre-processing is not desired, the configuration unit 38 indicates to the pre-processor not to operate.

The configuration unit 38 also receives processing parameters from the microprocessor 28 and provides them to the appropriate processing unit.

Pseudo code of the operation of the imaging processor 10 is provided in Annex A.

Reference is now made to Figs. 2 - 7 which respectively detail the pre-processor 12 , the histogram generator 18 , the LUT processor 20 , the post-processor 22 , the configuration unit 38 and the BIT 27 .

As shown in Fig. 2 , the pre-processor 12 comprises a signal source switch 40 for selecting, upon control of the microprocessor 28 via a CONFIG parameter received from configuration unit 38 , the signal to be processed. The signal can be either the N (or N+q) bit video signal or data from the BIT unit 27 for testing the operation of the pre-processor 12 .

The selected signal is provided to a filtering unit 42 which comprises a high pass filter (HPF) 44 and a boost 46. The high pass filter 44 reduces any low frequency components in the selected signal and the boost 46 amplifies the output of the high pass filter 44 (i.e. separates the signal into its AC (high frequencies) and DC (low frequencies) components) and adds the amplified high passed signal to the original signal, thereby adding contrast to the signal.

The high pass filter 44 and the boost 46 typically are built of high precision elements and typically operate with two's complement logic thereby to operate on an input video signal having any number of bits per datapoint. The LUT processor 20 and the post processor 22 typically also utilize two's complement 10 logic .

The parameters (coefficients) of the high pass filter 44 and of the boost 46 can be user-defined, or they can be fixed. If they are user-defined, their values are provided to units 44 and 46 from the configuration unit 38.

The filtering unit 42 additionally comprises an output signal selector 48 which selects, under control of the microprocessor 28 via a second CONFIG parameter from the configuration unit 38, which of the high pass filter 44 or the high pass filter 44 and the boost 46, or neither, is operative. Thus, the output signal from the pre-processor 12 is either the signal from the signal source switch 40 (i.e. a signal that has not undergone any filtering) , the output of the high pass filter 44 or the output of the boost 46.

Thus, the pre-processor 12 performs one of three operations, high pass filtering, boosted high pass filtering, or it does not modify the input video signal. The output of the preprocessor 12 is called herein "an enhanced video signal", even if the pre-processor does not modify the input video signal. Regardless of the selected output signal, the pre-processor 12 also provides the AC and DC signals, produced by the boost 46, for use by other components.

As shown in Fig. 3. the histogram generator 18 comprises a signal source switch 50 for selecting, upon control of the microprocessor 28 via the configuration unit 38, the signal to be processed. The signal can be the enhanced video signal from the pre-processor 12, an output signal from the post-processor 22 or no signal, in which case, the histogram generator l8 does not operate.

The output of the signal source switch 50 is provided to an address generator 52 for generating an address in buffer 21 as a function of the intensity of each pixel of the signal. The buffer interface 37 then accesses the data stored at the address ADR of buffer 21 and provides it to a histogram unit . Buffer 21 is typically formed of a Random Access Memory (RAM), typically of a size determined by a desired tradeoff between performance 11 and price.

Histogram unit 54 typically operates on the value provided it and returns the modified value to the RAM interface 37, to be placed into buffer 21 at the selected address.

The histogram generator 18 can perform a plurality of types of histograms, such as standard, regional and saturation histograms .

A standard histogram (see Fig. 9A) is a graph of the number Hi of pixels in an image having a given intensity level I vs. the entirety of intensity levels I possible. For a standard histogram therefore, upon receiving an incoming pixel of the input signal, the histogram unit 54 increments by one the value received from address i of buffer 21 corresponding to the intensity level of the incoming pixel.

For large dynamic range images, there are many possible intensity levels, for each one of which an address in buffer 21 must be provided. For example, for an image having 12 bits per pixel, there are 2^ or 16384 possible intensity levels, thereby requiring that buffer 21 have at least 16384 addresses. The system designer will often choose to operate with a lower dynamic range rather than to require so much memory.

Furthermore, each address typically has a limit to the size of the value Hi stored within it. For an addresses storing eight bits of data, which is the standard size, H^ can have only 256 different values. If Hi begins at 0 and is incrememen ted to 255, the 256th pixel having the intensity level will change Hi back to 0. Since images are typically of 512 x 512 pixels, Hi is likely to exceed the value 256.

As is known in the art, the "wraparound" described hereinabove can be avoided by providing buffer 21 with a larger address space in which to store each value , thereby providing a larger range for the value . However, extra memory is required to implement this solution. ' The wraparound can also be avoided by providing histogram unit 54 with a threshold value T above which Hi is not incremented. The threshold T can be either a value determined 12 analytically or predetermined by the system designer or it can be the maximum size can attain, denoted in Fig. 3 as the parameter RAMSIZE.

The above described method can be utilized to reduce the size of buffer 21, however, it will be noted that the resultant histogram is generally not as accurate as a standard histogram .

A histogram with a reduced dynamic range is a region histogram. It can be produced by defining that each point on the abscissa represents a consecutive group of intensity levels and therefore, the number of points, or intensity levels, of the region histogram is less than for a standard histogram.

As is known in the art, a consecutive group of intensity levels is a group having the same most signficant bits. Therefore, to produce a region histogram, the address generator 52 typically ignores, as desired, one or more of the least significant bits of each incoming intensity level. The number of bits to be ignored is provided by the parameter HISTADR.

Since the region histogram should be placed in consecutive addresses of buffer 21, the parameter HISTADR is also used to define the relationship between each region histogram address ir and each standard histogram address i.

Alternatively, the address generator 52 can ignore some of the most significant bits. This produces a limiter histogram and is also selected via the HISTADR parameter.

It will be noted that, although the region histogram utilizes fewer addresses than the standard histogram, the resultant region histogram is generally less accurate than the standard his togram .

It will be appreciated that the configuration parameters for the histogram generator' 18 enable the system designer to select the proper histogram operation for the images he receives and for the price and accuracy in histogram generation that he desires. The following design parameters affect the type of histogram to be performed: 1) size of buffer 21, 2) wordsize of each address in buffer 21, 3) speed and wordsize of the micro- 13 processor 28, 4) extent of dynamic range to be utilized, and 5) imaging processor 10 can operate on images with large dynamic ranges with a minimum of memory. Furthermore, because the memory (buffers 21 and 23) is placed externally to imaging processor 1G, the amount of memory utilized is flexible and is determined by the characteristics and desired tradeoffs of the application for which the imaging processor 10 is utilized.

It will be appreciated that the imaging processor 10 of the present invention can selectively operate on images with a large dynamic range or with images of a small dynamic range. The only restriction is the size of the buffers 21 and 23 chosen.

The histogram, stored in buffer 21, is typically transferred, after generation and via the histogram interface 3^ , to microprocessor 28 for processing and for creation of a histogram-based LUT for mapping the input image. The specific method of creating the LUT mapper depends on the specific application. An example method is provided in the following thesis which is incorporated herein by reference: "Dynamic Range Repacking of Infra-Red Systems" by Menachem Dvir, submitted to the Senate of the Technion - Israel Institute of Technology in August 1 89.

It will be appreciated that the microprocessor 28 has to be of the type which can read the high precision histogram data stored in the buffer 21 and can create a high precision LUT within the time constraints of the imaging processor 10. The time constraints are defined as follows: the histogram must be produced, the LUT calculated and placed into the buffer 23 all within an integral number of input images of the video signal. 14 The LUT created by the microprocessor 28 is transferred to the LUT processor 20 , via LUT interface 36 . and stored in buffer 23 , as shown in Fig. 4 .

The LUT processor 20 comprises a signal source switch 60 for selecting, upon control of the microprocessor 28 via a third CONFIG parameter received from configuration unit 38 , the signal to be processed. The signal can be the enhanced video signal from the pre-processor 12 , post-processed video signal from the post-processor 22 or no signal, in which case, the LUT processor 20 does not operate.

The signal from the signal source switch 60 is provided to a LUT address generator 62 for converting the J bit LUT input signal into an X bit signal where X depends on the size of the buffers 23 as provided by the INTERNAL DATASIZE parameter. X is typically less than N+r or N+q+r. The LUT address generator 62 enables the LUT to operate using buffers 23 with a lower precision than is provided in the LUT input signal.

In accordance with standard LUT operations, the LUT address generator 62 generates an address in buffer 23 based on the value of each pixel in the input signal. The LUT address generator 62 then addresses the buffer 23 , via RAM interface 39 . to retrieve the LUT data stored at the generated address. The retrieved data, which is the mapped value of the input pixel, is then provided as the value of the output signal for that pixel.

If desired, buffer 23 can comprise two RAM units 23 a and 23b and double buffering can be performed. If double buffering is to be performed, a DOUBLE BUFFER parameter, which is provided to RAM interface 39 . is set to indicate double buffering .

In this mode, the RAM interface 39 connects one of the buffers 23 , for example buffer 23 a , to the LUT address generator 62 and the other, in this example buffer 23b , to the microprocessor 28 , via the microprocessor interface 30 · The LUT address generator 62 then operates with buffer 23a while the microprocessor 28 generates a next LUT to be placed into buffer 23b . Once microprocessor 28 finishes placed the next LUT into buffer 23b 15 (typically at the end of an image of the video signal), the RAM interface 39 connects buffer 23b to the LUT address generator 62 and buffer 23 a to the microprocessor 28.

The post-processor 22, as shown in Fig. 5 . comprises a signal source switch 70 for selecting, upon control of the microprocessor 28 via a fourth CONFIG parameter received from configuration unit 38 . the signal to be processed. The signal can be either the enhanced video signal from the pre-processor or the output of the LUT processor 20.

The post-processor 22 typically compresses the dynamic range of its input signal for display on display device 24 or for further processing. The post-processor 22 compresses the dynamic range utilizing one of many possible methods, only one of which is described hereinbelow. The remainder are provided in the subroutine WEBBER in the pseudo code of Annex A.

The post-processor comprises a second high pass filter (HPF2) for providing the fine details of the AC and DC signals form the pre-processor 12, a summer 74 for summing the fine details output from the high pass filter 2 with the input signal to be processed and a saturation logic unit 7 for reducing the dynamic range of the output of the summer to within a desired range as noted in the parameter OUTPUT DATASIZE, received from the configuration unit 38 .

The HPF2 72 typically determines the fine details by calculating various combinations of limits of the AC and DC signals .

If the output signal from the LUT processor 20 is provided as input to the post-processor 22, then the HPF2 72 provides the fine details of the enhanced video signal and the summer 74 adds the fine details to the output LUT signal.

The post-processor 22 additionally comprises an output selector 78 for selecting the desired output, which can be either the output of the saturation logic 76 or the output from selector 70 , in which case, the post-processor 22 does not necessarily process the input signal.

Fig. 6 illustrates the configuration unit 38 and shows 16 it to comprise a multiplicity of selectors 80 addressing a bank of registers 82. The selectors receive configuration and parameter data from the microprocessor 28 and place the data in the correct locations in the bank of registers 82. The data stored in the bank of registers includes the following parameters described hereinabove: DOUBLE BUFFER, RAMSIZE, INPUT and OUTPUT DATASIZE, THRESHOLD (T) and HISTADR.

In addition, the configuration information includes the CONFIG parameters, providing the imaging processor 10 with the selected path along which the input signal is to flow. As described hereinabove, the CONFIG parameters select the source of the input signal to each processing unit 12, 18, 20 and 22 as well as the outputs therefrom.

Fig. 7 illustrates the BIT unit 27 which is operative to test one, more or all of units 12, 18, 20 and 22 (labelled "unit under test" 90) . in accordance with the current configuration and TEST parameters provided to it by the. configuration unit 38.

The BIT unit 27 comprises an input first-in-first-out (IFIFO) buffer 92 for receiving an input test signal from the microprocessor 28 via the BIT interface 32 and for providing the input test signal to the pre-processor 12, as indicated by the letter C and an output FIFO (0FIF0) buffer 94 for receiving, from after the post-processor 22 as indicated by the letter C, the output of the unit under test 90 after operating on the test signal. The BIT unit 27 additionally comprises a controller 6 for controlling the operation of and synchronization between the IFIFO 92 and the 0FIF0 9^· Whenever the microprocessor 28 begins a built-in test, it places the input test signal into the IFIFO 92 and it indicates to the configuration unit 38 that a BIT is to be performed on a selected unit under test 90.

During the next available blank period, the configuration unit 38 configures the signal source switches 40, 50, 60 and 70 and the output selectors 48 and 78 to bypass those units which are not to be tested and to set the type of input signal the unit 17 under test 90 is to receive.

.The controller 96 indicates to the IFIFO 92 to provide the test signal to the pre-processor 12 from, where it is directed, via the configured units, to the selected unit under test 90. The controller 6 also notes the time at which the test signal is provided .

Subsequently, the unit under test 90 then operates on the data from the IFIFO 92, providing the output, via the configured units to after the post-processor 22 and from there, to the 0FIF0 94. The controller 96 notes the time the data is received by the 0FIF0 94.

At any appropriate time thereafter, the microprocessor 28 samples the signal in the 0FIF0 9^ and requests the timing information from the controller 96. The output signal is then compared to a typical output, stored within the microprocessor 28, from the unit under test 90. As is known in the art, a failure is declared only if the output signal is not similar enough (by some selected measure) to the stored typical output.

If the unit under test 90 fails, the microprocessor 28 can then bypass the improperly working unit 90 by sending, during the next blank period, a new configuration to the configuration unit 38.

It will be appreciated that because the BIT unit 27 typically operates during the blank periods, the operation of the BIT unit 27 does not affect the regular operation of the imaging processor 10.

It will further be appreciated that the combination of the BIT unit 27 and the microprocessor controlled configurability enables the imaging processor 10 to degrade gracefully in the presence of failures of one or more of the units 12, 18, 20 and 22.

Specifically, the BIT unit 27 typically tests all of units 12 - 22 in one test. If a failure is detected, then each unit is tested individually. Each unit which has failed is bypassed as follows: if either of units 18 or 20 fails, its signal source switch is set to off (i.e. such that the unit receives no 18 input signal). If either of the pre-processor 12 or the postprocessor 22 fails, the signal source switch is set to provide an input signal and its output selector is set to provide the input signal rather than a processed signal.

It is noted that the graceful degradation provided as described hereinabove occurs while the imaging processor 20 is in use .

It will still further be appreciated that the microprocessor controlled configurability provides the imaging processor 10 with changing operating parameters, such as the coefficients of the various filters, the type of histogram to calculate, etc, before and during operation.

Reference is now made to Figs. 8 and 9A - 9D which respectively illustrate a schematic of an alternative embodiment of the present invention and the dynamic range monitoring function it performs.

In the alternative embodiment of Fig. 8, a loss function generator 100, which can be implemented in software or hardware and is generally similar to the histogram generator 18, and a loss buffer 102 are additionally included. The histogram generator 18 performs a threshold histogram on the enhanced video signal from the pre-processor 12. An example histogram, labelled 104, is shown in Fig. 9A as is an example threshold level. The thresholded histogram, an example of which is shown in Fig. 9C, consists of those parts of histogram 104 which are above . the threshold level. It can be seen that the thresholded histogram has a plurality of gaps 108, denoted by dotted lines.

Under control of the microprocessor 28, the histogram produced by the histogram generator 18 is provided to the loss function generator 100 and a loss histogram, being a histogram of the histogram for a given threshold value, is calculated. Specifically, each datapoint in the loss histogram is the number of times in the histogram that there were Xi number of occurrences. The sum of the datapoints in the loss histogram provide the number of pixels incorporated in the histogram.

The process is repeated, with the same histogram stored 19 in buffer 21, for a multiplicity of threshold values and, for each threshold level, a loss percentage is calculated, where the loss percentage is the number of pixels not incorporated into the histogram (i.e. the sum of the datapoints in the loss histogram) divided by the total number of pixels in the image. A loss function, shown in Fig. 9B, as a function of threshold values is then determined .

The threshold value which provides a pre-determined percentage loss is selected by the microprocessor 28 which removes the gaps 108 from the corresponding histogram 106 to produce a gap removed histogram 110, illustrated in Fig. 9D- Gap removed histogram 110 is produced in accordance with the thesis by Menachem Dvir, mentioned hereinabove.

In accordance with the thesis of Menachem Dvir, the microprocessor 28 modifies the gap removed histogram 110 to have a predetermined number of gray levels (i.e. stretches or shrinks the gap removed histogram 110 as necessary) and from the modified histogram, determines the LUT. The LUT is then provided to the LUT processor 20 for mapping the enhanced video signal as described hereinabove. The remainder of the imaging processor elements are as described hereinabove for the first embodiment.

It will be appreciated that the adaptive gap removal process provides accurate histogram processing with a thresholded histogram. This is in contrast with standard histogram modification techniques which are inaccurate if a threshold is utilized.

In accordance with the alternative embodiment of the present invention, the threshold can be adapted as necessary to maintain a predetermined percentage loss. The LUT is recalculated for each new threshold. It will be appreciated that the alternative embodiment of the present invention enables maintenance of the image quality and the number of grey levels even with dynamic images.

Source code, written in the FORTRAN language, for the dynamic range monitoring described hereinabove is provided in Annex B.

Alternatively, the apparatus of Fig. 8 can be utilized 20 to maintain the number of grey levels, rather than the percentage loss, in the output video signal. In this embodiment, the loss percentage generator 1ΘΘ is modified to calculate the number of grey levels remaining in the histogram after thresholding.

The threshold value which provides a pre-determined number of grey levels, such as 256, is selected by the microprocessor 28 which removes the gaps 108 from the corresponding histogram IO6 to produce the gap removed histogram 110 (Fig. 0)· The gap removed histogram is processed as described hereinabove.

Reference is now briefly made to Fig. 10 which illustrates an application specific integrated chip 120 for implementing the imaging processor 10 of Fig. 1. It can be seen that it has a l4 bit input video line as well as a clock signal (P_CLK) and vertical and horizontal blank signals (V_BLK and H_BLK, respectively) . The output is just the output video signal produced by the post-processor 22.

The chip 120 is connected to the microprocessor 28 via data, address and control busses 122 - 126 and to a memory bank 130 via data, address and control busses 132 - 136.

It will be appreciated by persons skilled in the art that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention is defined only by the claims that follow: 21

Claims (2)

1. 02904/3 C L A I M S 1. An imaging processing system comprising: a multiplicity of processing units, at least one of which is operative to generate a histogram of image pixel values; a configure connected to each of said processing units; and a microprocessor comprising a histogram gap remover operative to remove from the histogram gaps which fall below a threshold, whereby said microprocessor provides arameters to said processing units and connects at least one of said processing unites to each other via said configure.

2. An imaging processing system comprising: an imaging processor comprising a multiplicity of processing unites formed on a single integrated circuit chip and operative to produce output including a histogram of image pixel values; a memory; and a microprocessor comprising a histogram gap remover operative to remove from the histogram gaps which fall below a threshold, whereby said processing units store said output in said memory, said microprocessor and said memory are connectable to said single integrated circuit chip, and whereby said microprocessor is operable to configure said multiplicity of processing units. 22 102904/3 5. An imaging processing system comprising:' a histogram generator operative to generate a histogra of pixel values in an image to be processed; a dynamic range monitor operative t monitor the dynamic range of the image; and a histogram gap remover responsive tc the dynamic range monitor and operative to remove 'gaps from the histogram. 6. A system according to cl aim 5 wherei n the histogram generator, dynamic range monitor and histogram gap remover form an imaging processor, the system also comprising a memorv external to the imaging processor. 7. A system according to cl a im 5 wherei n said histogram gap remover comprises a 8. A system according to cl a im 3 wh re re i n said histogram generator is operative to generate a mul ti pl i ci ty . cf types cf histograms with different memory requirements, the system also comprising a configurer providing a configuring input ..to the histogram generator which determines, based at least in part on the configuring input, which, type of histogram is generated. ■ 9. A system according tc cl aim 8 wherei n the configurer comprises a multiplicity of configurable selectors which can. be updated, during operation, in accordance with an input configuration signal. 102904/ 3 10· A system according to claim 8· v srsin said multiplicity of histograms includes a histogram wherein each .point on the abscissa' of the histogram represents a consecutive group cf intensify levels. 11. system according to claim 15 and also comprising: a built-in tester having associated therewith a multiplicity cf test signals, each corresponding to at least cne cf the multiplicity cf processing units; whereby during a blank period of a video signal received by the processing units, said tester provides at least one cf said test signals to its- at least one corresponding processing unit and receives an output signal from said corresponding processing unit responsive to said at least one test signal; and a tester processor capable cf indicating proper functioning of said at least cne corresponding processing unit- based on analysis of said output signal. 12. Apparatus according to claim 11 a d wherein said tester comprises a controller operative to. measure ≥n amount cf time during which said at least one corresponding processing unit processes said at least one test signal.. 13. Apparatus according to claim 11 and wherein said conigurer is connected to said "multiplicity' cf processing units whereby said configurer reconfigures the connections cf said multiplicity cf processing units to bypass a processing unit identified by said tester as improperly functioning. V-■·''· '·'· : ··· ".·.·-. 102904/ 3 14. A system according to claim 5 wherein the histogram generator is operative to produce a multiplicity cf threshclded histograms cf an input signal, each histogram produced with a different threshold value and wherein the system also comprises: a percentage less calculator respensive to each cf said threshclded histograms; and a less level maintained which selects a threshold level corresponding to a desired percentage loss wherein a threshoided histogram having said selected threshold, level has gaos therein; wherein the gap remover is responsive to the selected threshold histograms. 15. A system according to claim '5 wherein the histogram generator is operative to produce a multiplicity of threshclded histograms cf an input signal, each histogram produced with a different threshold value and wherein the system also comprises: a number of gray levels calculator respensive tc each of said thrasholded histograms; a number cf gray levels maintainer which selects a threshold level corresponding tc a desired number cf remaining gray levels wherein a threshoided histogram having said selected threshold level has gaps therein; and wherein the gap remover is responsive tc the selected threshold histograms. 5# Apparatus according tc claim 14 wherein the dynamic-range monitor repeatedly operates said histogram generator, said percentage loss calculator and said loss level maintainer tc change said threshold level as said input signal changes, thereby to maintain said desired percentage loss. 17. Apparatus according to claim 15 wherein the dynamic range monitor repeatedly operates said histogram_ generato , said ■number of gray levels calculator and said number of gray levels maintainer to change said threshold level as said input signal changes, thereby to maintain said desired percentage less. 13# A system according to claim 1 wherein said histogram gap remover comprises an adaptive histogram gap remover operative to selec . said threshold. ig< A systes according to claim 2 wherein said histogram gap remover comprises an adaptive histogram gap recover operative to select said threshold. For the Appl icant, Sanford T. Colb & Co. C: 13509