IL100672A - Multi-layer ablative etch-resistant coating - Google Patents

Description

MULTI-LAYER ABLATIVE ETCH-RESISTANT COATING •JID^N ""aDa -nny "Ίηοω m ■•IDS QUICK TECHNOLOGIES LTD.

C: 14057 General This invention relates to laser-programmable integrated circuits, and more specifically to the fabrication of prototype devices of application specific integrated circuits (ASIC's) by laser micro-machining.

Background of the invention In the fabrication of a laser programmable integrated circuit the device is produced with a metal grid interconnecting all the active elements of the device. In the personalization step of the device the undesired metal connections are removed by applying laser radiation thereto, and only the metal connections required for the implementation of the specific application remain on the device.

The removal of the undesired metal connections at selected locations can be affected, for example, by coating the device with standard polymeric photoresist, applying patterned radiation thereto, developing the resist, and etching the metal through the apertures formed in the photoresist mask.

The drawbacks of this approach are that handling the photoresist requires high quality yellow clean rooms, which are expensive. Also, polymeric photoresists have a limited shelf life, and they must be processed within a few hours from application on the device. Hence the photoresist handling adds to the personalization cycle time. Furthermore, with existing photoresist technology the application of photoresist is done over a large wafer which includes many devices, so an additional step of sawing the wafer into individual dice must be performed before the devices are ready for packaging and delivery.

For prototyping of ASIC's it is desirable to reduce the cost and the cycle time of the personalization process. Thus it is desirable to stockpile the devices as close as possible to the stage of personalization, and have them ready for packaging immediately after the step of removing the undesired interconnection links.

This can be achieved by using inorganic ablative photoresists. In U.S. / Europe / Japan patent applications No. 117,580 / 8731027 / 62-29650 a method of direct laser machining of metal lines coated with an inorganic photoresist is described. In this case a resist layer 30 shown in Fig. IB is applied long before the device is personalized, it can be stored at ambient room conditions, and after exposure it does not have to be developed but rather the resist is directly micro-machined by Q-switched pulsed laser ablation. After laser ablation the exposed underlying metal is etched while the a-Si provides metal etch-protection to the non-irradiated metal grid points.

However, this method has the following drawbacks : a. Because of the varying topography of the device, particularly when double or triple metal layers are used, the thickness of the resist layer over the metal varies from site to site. This dictates different pulse energies at different locations on the device, which complicates the personalization process. b. Due to the nature of the photo thermal ablation process in some inorganic resists the apertures opened in the resist layer are wider than the dimensions of the laser pulses, which limits the ultimate achievable resolution. c. Because of the varying thickness of the resist layer over the device, the target thickness of the resist layer must be such that at the locations of minimum thickness it provides sufficient etch protection. This dictates a relatively thick resist layer at other locations, which requires high energy to ablate the layer (above 10 J/ cm2 per pulse). This high energy may cause damage to the underlying device layers or to nearby metal lines. d. When the laser energy is higher than the minimum energy required to ablate completely the resist layer, but lower than the energy required to remove completely both the resist and the underlying metal layer, the remaining metal link gets hardened due to the heating/ cooling cycle, and it becomes difficult to remove the metal residue by successive chemical etching.

To achieve a high yield in personalization by laser micro-machining it is desirable to use the minimum possible energy and to obtain the most reproducible results over a wide range of metal topographies and a wide range of laser energies.

Summary of the Invention It is disclosed that when a material of high laser energy absorption such as a-Si is deposited over a dielectric material such as silicon nitride, and a laser pulse hits the laser - absorbing layer, the precise shape of the laser pulse is imprinted in the underlying dielectric material. The dimensions of the pulse shape are reproduced in the dielectric layer even if the laser pulse energy is high enough so that the dimensions of the ablated area of the energy absorbing layer are much wider than the pulse boundaries.

The imprint in the dielectric material does not depend on the optical absorption of the dielectric layer, and it occurs even if the dielectric material is transparent to the laser radiation.

The depth of the imprint depends on the laser energy and on the thickness of the laser absorbing layer overlying the dielectric material. When an additional lower layer of a different dielectric material such as polyimide or p-SiOx (plasma deposited silicon oxide) is applied under the silicon nitride layer and the energy of the laser pulse is increased, the depth of the imprint in the silicon nitride will reach the boundary between the layer of silicon-nitride and the lower layer, and it will not penetrate deeper into the lower layer even if the laser pulse energy is increased to over 2 times the energy required to form an imprint through the middle layer.

Accordingly, in the present invention the metal links in a laser programmable integrated circuit are coated with a double layer dielectric coating comprising a dielectric layer such a silicon nitride of thickness typically between 3000 and ΙΟ,ΟΟθΑ, over which is deposited a layer of laser absorbing material such as a-Si at thickness typically between 2000 and 8,ΟΟθΑ. During the step of personalization the a-Si is exposed at selected locations to an ablating laser radiation of a Q-switched pulsed laser such as a Nd:YAG or Nd:YLF laser at energy density typically between 1 and 20 J /cm2. Under these conditions the a-Sl will ablate and an imprint will be formed in the underlying dielectric layer.

.When laser energy at the lower energy limit is used, the imprint may not reach the underlying metal. In that case selective etching of the dielectric layer will remove the dielectric material residues over the metal at the irradiated spots, while the a-Si provides etch protection to the dielectric layer at non-selected spots.

Following the dielectric residue removal the metal links are etched through the apertures formed iri the dielectric layer, to produce the electronic function of the device.

In another embodiment of the present invention, the metal links are coated with a triple-layer dielectric coating comprising a first layer of one of p-SiOx, spin-on glass, phosphorus doped glass (PSG) polyimide or probeimide of thickness typically between Ι ,ΟΟθΑ and 2O,O00A, over which is deposited a second layer of a different dielectric material such as silicon nitride, and over which is deposited a layer of laser energy- absorbing material. In the step of personalization the laser absorbing layer is ablated at selected location by directing thereto pulsed laser radiation, and an imprint is formed in the second dielectric layer, extending down to the interface between the first and second dielectric layers. The device is then subjected to selective reactive ion etching (RIE) or wet chemical etching to remove the first dielectric layer at the selected locations through the apertures formed by the laser in the second dielectric layer, and subsequently the metal layer is etched.

Usually, after laser ablation and before the metal etching step the device is subjected to a wet or dry cleaning cycle, to remove the ablation debris from the surface of the device.

After metal etching, the remaining portion of the metal etch-resistant coating is removed to expose the bonding pads for testing and packaging. ure Description is a cross-sectional illustration of a typical integrated circuit with locations designated for selective removal. is a cross -sectional illustration of a laser programmable device according to the prior art . is a cross-sectional illustration of a laser programmable device with a two-layer ablative etch resistant coating. is a cross-sectional illustration of the device of Fig. 2A after laser ablation at a selected point. is a cross-sectional illustration of Fig. 2B after etching of the residual dielectric material. is a cross-sectional illustration of Fig. 2C after metal etching. is a cross-sectional illustration of a laser programmable device with a three-layer ablative etch- resistant coating. is a cross-sectional illustration of Fig. 3A after laser ablation. is a cross-sectional illustration of Fig. 3B after selective etching of the residual second dielectric layer. is a cross-sectional illustration of Fig. 3C after selective etching of the bottom dielectric layer. is a cross-sectional illustration of Fig. 3D after metal etching. is a cross-sectional illustration of a laser programmable device with a three-layer ablative etch-resistant coating where the bottom layer is a planarization layer. is a cross-sectional Illustration of Fig. 4A after laser ablation. is a cross-sectional illustration of Fig. 4B after selective etching of the bottom dielectric layer. is a cross-sectional illustration of the devices of Fig. 2D & 3E after removal of the ablative etch resistant layer.

Detailed Description of the invention Figure 1A shows a cross-section of a typical integrated circuit of the double-metal , C-MOS type comprising a semiconductor substrate 10, implant regions 12&13, insulation layers 14, 15, 17 & 19, gate layer 16 and interconnection layers 18 & 20. The interconnection layers may be preferably composed of a conductive substance such as metal, metal silicide or a conductive glass such asJTiN or ITO, or combinations thereof. In Fig. 1A the upper interconnection layer 20 is coated with a passivation layer 21 , and windows 22A&B are opened in the insulation layers 21 & 19 to expose the metal at the potential locations at which the metal may sought to be removed.

Fig. 2A illustrates the device of fig 1 A coated with a double layer ablative etch-resistant coating 40 & 42 according to the present invention, ready for laser personalization.

Layer 40 comprises a dielectric material such as silicon nitride (SiNx), silicon oxide (SiOx), phosphorus doped glass (PSG), polyimide, or spin-on glass of a thickness typically between 300θΑ and 12,000A.

Layer 42 comprises a laser absorbing material whose absorptance at the selected laser wavelength is at least 0.1 and preferably over 0.5.

For a Q-switched frequency-doubled Nd:YAG or Nd:YLF laser operating at a wavelength of 532 nm or 523 nm, respectively, layer 42 may be composed of evaporated or sputtered amorphous silicon of thickness above 500A, or of plasma-enhanced chemical vapor deposited amorphous silicon (PECVD a-Si:H) of thickness above 1 ,ΟΟθΑ. In the latter case the a\m must be thicker since the PECVD process produces a-Si films of lower absorption coefficient.

The a-Si material is particularly convenient for the makeup of layer 42 since it has the highest optical absorptance for a given thickness of all materials which are compatible with state of the art integrated circuit fabrication technology. However, other laser absorbing materials may be used as well.

The thickness of layer 42 may be preferably more than 2,000A, to provide mechanical stability, and less than ΙΟ,ΟΟθΑ, to preserve the lateral topography and to limit the amount of laser energy required for complete ablation of the film.

Fig 2B illustrates the result of a laser pulse at one of the selected locations, 22A. The laser energy density may be between 1 and 20 J/ cm2, depending on the thickness of the layers 40 and 42. An apparatus to produce such pulses is available from Quick Technologies Ltd. of Haifa, Israel.

Following the step of laser ablation, the residual dielectric material is removed by selective etching as shown in Fig. 2C, while the laser absorbing layer provides metal etch protection at non-selected location 22B.

Following the dielectric residue removal, the metal links at the selected locations are removed, as shown in Fig. 2D, by chemical etching or RIE.

In another embodiment of the present invention, the metal links are coated with a triple-layer ablative etch resistant coating 50 + 42 shown in fig. 3A. The triple-layer coating comprises a first dielectric layer 52 which functions both as a laser imprint stop and as a chemical etch stop, a dielectric layer 54, and a laser absorbing layer 42.

The makeup of layer 52 must be different than that of layer 54, and it may comprise one of SiOx, SiNx, SOG, PSG, polyimide or probimide. Its thickness may be between 50θΑ and 500θΑ. Usually, the imprint in the upper dielectric layer starts to form at a laser energy of 2 J /cm2, it reaches the interface at a laser energy of about 6 J/cm2, but it does not pierce the bottom dielectric layer at laser pulse energies lower than 12 J/cm2. Hence layer 52 provides a laser imprint stop at laser energies between 6 and 12 J/cm2.

Fig. 3B Illustrates the device of fig. 3A after laser ablation, for the case where the laser energy is selected so as to remove most but not all the dielectric layer 54 at a selected location 22A. After laser ablation the device is subjected to selective etching in which the residue of layer 54 is removed, as shown in Fig. 3C. Fig. 3C illustrates also the case when the device of fig. 3A is irradiated with a laser pulse energy sufficient to ablate completely layers 42 and 54. Figure 3D shows the next step, in which layer 52 is etched at the selected location 22 A while layers 54 and /or 42 provide etch protection to the non-selected points. Finally the interconnection links at the selected locations are removed, as shown by fig. 3E.

Preferably, all the respective layers 42, 54, 52 20 and 18 can be etched successively in a reactive ion etcher (RIE) which is programmed to exchange the etching gases between the etching of each two layers. The cycle time of such etching process is of the order of minutes.

In yet another embodiment of the present invention, the first or the second dielectric layer of the ablative etch resistant coating may be a planarization layer. Figure 4A shows the case where layer 56 is a planarization layer Layer 56 may be composed of polyimide, probimide or SOG, of thickness preferably between 500θΑ and 20,ΟΟθΑ. Layer 54 may be composed of SiNx or SiOx of thickness between 50θΑ and 500θΑ. In this case the laser absorbing layer 42 and the second dielectric layer 54 are more uniform in thickness and in optical reflection, and it is easier to control the laser energy so as to achieve complete removal of the layers 42 and 54 at the selected locations, without any heating of the underlying layers 56, 18, or 20. The result of a laser pulse is shown in fig. 4B. The laser machining is followed by etching layer 56 through the apertures formed by the laser in layer 42 & 54 as shown in fig. 4C.

After metal etching, the remaining portion of the metal etch-resistant coating is removed, e.g. by RIE, to expose the bonding pads for testing and bonding, as shown in fig. 5.

It should be appreciated that while the device shown in fig. 1 has a passivation layer 21 in which windows were opened at potential etch location 22A & B prior to application of the ablative etch resistant coating, this passivation layer is not required in the present invention. However, when such layer is used, it gives the additional advantage that the windows 22A & B in the passivation layer serve to define the exact metal etching locations when a large or a displaced laser pulse is used in the personalization. Also, this invention can be applied with layers 19 and 21 without opening the windows 22A and 22B.

Also, this invention is not limited to a C-MOS device or a semiconducting subsrate, and it can be applied to any laser programmable integrated circuit or any device with built-in redundancy where laser fusing of interconnection links may be desirable. 100672/2

Claims (7)

1. A multi-layer ablative etch resistant coating comprising an upper layer of a laser energy absorbing material, and an underlying layer of a dielectric material, composed so that an ablating laser pulse absorbed in the upper layer forms an imprint in said underlying layer, said imprint serving as an etching window in the etching of layers underlying said coating.

2. A laser programmable electronic device whose electronic elements are connected by at least one interconnection layer, said interconnection layer being formed with a plurality of conductive links, said links being coated with a double-layer ablative etch resistant coating, said coating comprising an upper layer of a laser energy absorbing material and a bottom layer of a dielectric material, wherein said upper layer is ablated at selected locations by applying a laser pulse so as to form the pulse imprint in the bottom dielectric layer and thereafter the underlying interconnection links are etched through the apertures formed in said dielectric layer.

3. A laser programmable electronic device whose electronic elements are connected by at least one interconnection layer, said interconnection layer being formed with a plurality of conductive links, said links being coated with a triple-layer ablative etch resistant coating, said coating comprising an upper layer of a laser energy absorbing material, a middle layer of a dielectric material, and a bottom layer of a dielectric material of different chemical makeup than the middle layer, 100672/3 wherein said upper layer is ablated at selected locations by applying a laser pulse so as to form the pulse imprint in the middle dielectric layer and thereafter the underlying interconnection links are etched through the apertures formed in said dielectric layer.

4. A coating according to any of claims 1 - 3, and where the laser energy absorbing layer is sensitive to visible light.

5. A coating according to any of claims 1 - 3, and where the laser energy absorbing material comprises at least one of amorphous silicon and amorphous silicon alloy.

6. A coating according to any of claims 1 - 3, and where the dielectric material of the layers underlying the laser energy absorbing layer comprises one of silicon nitride, silicon oxide, spin-on glass, phosphorous doped glass, amorphous hydrogenated carbon, polyimide or probimide.

7. A device according to claim 3 and where the bottom dielectric layer is a planarization layer. For the A¾¾±cafvE, Sanford T. Colb & Co. C: 14057