IES970629A2 - A method for preparing masks for use in the manufacture of¹a semi-conductor IC wafer, and a combination of masks - Google Patents

Abstract

A method for preparing a set of masks for forming an IC wafer minimises the set-up required for setting up an automated critical dimension scanning electron microscope. The masks of size to form one field (3) of a plurality of fields (3) in the respective layers of the IC wafer. Each mask is provided with an alignment forming area for forming identical alignment area (11) in each field (3) of the layer at identical locations from an origin (12) of the respective fields. Critical dimension test forming features in the masks form test features (31) in test areas (26) the dimensions of which may be measured for facilitating a determination of the critical dimensions of components the critical dimensions of which are to be measured. The test areas (26) are located in identical locations in each field (3) in each layer and identical test features (31) are located in identical locations in their corresponding fields (26). The X and Y coordinates of each test feature (31) at which the critical dimension of the test feature (31) is to be measured is stored in software with reference to a reference point (29) of the corresponding test area (26), and the X and Y coordinates of the reference points (29) with reference to the origin (12) are also stored in software. Thus, computation of the X and Y coordinates of the locations at which the test features (31) are to be measured can readily easily be computed as the masks are being prepared, and stored in software, ready for down loading into the automated critical dimension scanning electron microscope during the set up of the microscope. The alignment areas (11) define alignment points (14) at identical locations, and the X and Y coordinates of one of the alignment points (14) from its corresponding origin (12) is stored in software for down loading into the automated critical dimension scanning electron microscope during set-up of the microscope.<Figs.1&2>

Description

A method for preparing masks for use in the manufacture of a semi-conductor IC wafer, and a combination of masks The present invention relates to a method for preparing a plurality of masks of a set of masks, and a combination of the masks of the set for use in manufacturing a semi-conductor IC wafer for facilitating set-up of measuring apparatus for testing critical dimensions of components on a layer of the wafer. The invention also relates to a method for setting up measuring apparatus for measuring critical dimensions of a layer of a semi-conductor IC wafer, and the invention further relates to a method for measuring critical dimensions of components on a layer of a semi15 conductor IC wafer.

Integrated circuit chips are manufactured on semiconductor IC wafers, and in general, each IC wafer comprises a plurality of integrated circuit chips. The integrated circuits of the chips are formed in the wafer in layers in production apparatus and the layers are patterned by sequentially exposing the respective layers to a plurality of masks of a set of masks. One or more masks may be required for the formation of each layer of the IC wafer.

JNL. NO. ...12.3.0......xrW OPBNTOPU8UC INSPECTION UNDER fi&CTION 28 AND RULE 23 597082 » Because of the relatively intricate nature of the artwork which is required in the respective masks it is not commercially viable to provide individual masks of size sufficient to pattern an entire layer of an IC wafer in one exposure. Additionally, the cost of apparatus to pattern an entire layer simultaneously over the entire surface area of the IC wafer would be prohibitive.

Accordingly, to overcome this problem the wafer is divided into imaginary identical fields, and each mask is of size for patterning a layer on the semi-conductor material of area similar to one field only. The layers of the IC wafer are exposed to the corresponding mask or masks by indexing each mask sequentially across and down the IC wafer. In general, each field comprises many integrated circuits, which may be identical to each other or different. Typically, each field is divided into imaginary cells, and each cell may comprise one or more integrated circuits, but typically, one integrated circuit.

During manufacture of the IC circuit, border areas are formed which define the fields and the cells of the wafer, and also separate the fields and cells from each other. These border areas are generally referred to as scribes, and when the manufacture of the IC wafer has 970629 been completed, the wafer is cut along the scribes for separating the integrated circuit chips from the wafer. This will be well known to those skilled in the art.

In many of the layers components are formed, the dimensions of which are critical. Such components, may be conductors, voids or other features. It is important that as each layer with such components is formed, the critical dimension or dimensions of the component is checked. This, typically is carried out by transferring the IC wafer into an automated critical dimension scanning electron microscope where the critical dimensions of the component or components are measured. The alignment of the IC wafer in the microscope is first determined, and the IC wafer is then moved in the microscope for aligning the component, the critical dimension of which is to be measured with an optical microscope of the microscope. When the component is aligned with the optical microscope, the component is then scanned by a scanning electron microscope for determining the critical dimension of the component. This operation of an automated critical dimension scanning electron microscope will be known to those skilled in the art.

Initially, alignment is carried out by aligning and focusing the optical microscope on two spaced apart 5ί70β2 9 features on the IC wafer, the coordinates of which are known from origins of corresponding fields. After the alignment of the IC wafer in the microscope has been determined, the component the critical dimension of which is to be measured is checked in each field by sequentially indexing the IC wafer across and down for sequentially aligning the component in the respective fields with the optical microscope, and in turn the scanning microscope, correction being made for any misalignment of the wafer in the microscope. The location of the component, the critical dimension of which is to be measured in each field is located by the optical microscope from the coordinates of the component from the origin of the corresponding field.

In order that the automated critical dimension scanning electron microscope can determine the alignment of the IC wafer in the microscope, and locate the component or components in the respective fields, the X and Y coordinates of the respective alignment features from the origins of the corresponding fields, as well as the X and Y coordinates of the component or components must be entered into the electron microscope and stored in a look-up table. Since in general, the component or components to be tested are in different locations in different layers, and furthermore, since in general, alignment features, which typically are specific 5070629 components in the layer, are formed in different locations in the different layers of the IC wafer, a vast amount of data regarding the X and Y coordinates of the alignment features and the components, must be entered into the automated critical dimension scanning electron microscope during set-up of the microscope prior to the commencement of a production run of IC wafers. In other words, it is essential to enter the X and Y coordinates of the alignment features and the locations of the components the critical dimensions of which are to be measured, for each layer, and these are different from layer to layer. The entering of this data is time consuming and relatively expensive. Additionally, for short production runs of an IC wafer the cost of setting up an automated critical dimension scanning electron microscope can form a significant proportion of the cost of production of the IC wafers.

There is therefore a need for a method for preparing a plurality of masks of a set of masks, and for a set of masks for use in manufacturing a semi-conductor IC wafer which overcomes these problems.

The present invention is directed towards providing such a method and a set of masks, and the invention is also directed towards providing a method for setting up measuring apparatus for testing critical dimensions in 597062 the layers of an IC wafer, as well as to a method for testing the critical dimensions of the components.

According to the invention there is provided a method for preparing a plurality of masks of a set of masks for use in manufacturing a semi-conductor IC wafer in a production run of similar IC wafers for facilitating set-up of measuring apparatus for testing a critical dimension of a component on at least one layer of the wafer, each mask defining a field of the IC wafer, the method comprising the steps of: providing on each one of the masks of the set of masks which are for use in forming the layers comprising respective components the critical dimension of which are to be tested an alignment forming means for forming a corresponding alignment means in each field in the corresponding layer of the wafer for facilitating a determination of the orientation of the wafer in the measuring apparatus, the alignment means of the respective layers being identical for facilitating identification by the measuring apparatus, and the alignment forming means being located so that each alignment means is formed in the corresponding layer adjacent to, but off-set from, the origin of the corresponding field, and so that the off-sets of the respective alignment means from their corresponding 597962 9 origins are similar for all the layers in which the alignment means are formed, at least one critical dimension test forming means for forming a corresponding critical dimension test means in each of the fields in the corresponding layer of the wafer, each critical dimension test forming means being located for forming the corresponding critical dimension test means at a location in the respective fields spaced apart from the alignment means and the origin of the corresponding field; and identifying the location at which the alignment means are to be formed in the layers of the wafer with reference to the origin of the respective fields, and identifying the location at which the respective critical dimension test means are to be formed in the layers of the wafer by the corresponding critical dimension test forming means with reference to the location of the alignment means or the origin of the corresponding field.

Preferably, a test area defining means is provided on the respective masks for use in forming the layers comprising a component, a critical dimension of which is to be tested, each test area defining means being provided for defining a corresponding test area in each of the fields in the corresponding layer for containing the corresponding critical dimension test means, the S97962 9 s test area defining means being located on the respective masks so that the test areas defined by the test area defining means are defined in the respective layers at similar locations relative to the origin and the alignment means of the respective fields, and each critical dimension test forming means is located in the corresponding test area defining means for forming the corresponding critical dimension test means in its corresponding test area defined in the layer.

In one embodiment of the invention each test area defining means defines a reference point in the corresponding test areas defined in the respective fields in the corresponding layer, and the location at which each test area is to be defined is identified with reference to its reference point and the alignment means or the origin of the corresponding field.

Preferably, the location at which each critical dimension test means is to be formed is identified with reference to the reference point of the corresponding test area.

In one embodiment of the invention each test area defining means defines the corresponding test areas with a pair of intersecting side edges, which intersect at a point which defines the reference point of the 597αβ29 corresponding test area.

In another embodiment of the invention each test area defining means defines the corresponding test areas of substantially rectangular shape.

Preferably, the critical dimension test forming means are located in the masks so that the critical dimension test means of the corresponding layers are formed at different locations in the corresponding test areas of the respective layers .

Advantageously, a plurality of spaced apart test area defining means are provided on each of the masks for use in forming the layers comprising a component, the critical dimension of which is to be tested, each of the masks comprising the same number of test area defining means, and the test area defining means being located so that the test areas defined by the respective test area defining means are defined in similar locations in each field of each layer.

Preferably, the critical dimension test forming means are located in the test area defining means of each mask so that critical dimension test means of the same type are formed in the corresponding test areas at similar locations. 597 0 62 9 In one embodiment of the invention each test area defining means is located for defining the corresponding test area in a border area defining the corresponding field.

In another embodiment of the invention each test area defining means is located for defining the corresponding test area in a border area defining a cell of the corresponding field.

In another embodiment of the invention each critical dimension test forming means is provided for forming the critical dimension test means as a test feature which is identical to the part of the component, the critical dimension of which is to be tested so that by measuring the relevant dimension of the test feature a determination of the corresponding dimension of the component to be tested may be made.

In one embodiment of the invention the test feature formed by the corresponding critical dimension test forming means is a short conductor which corresponds to a conductor of a component, the critical dimension of which is to be tested.

In another embodiment of the invention the test feature formed by the critical dimension test forming means is a void which corresponds to a void of a component, the critical dimension of which is to be tested.

In a further embodiment of the invention each alignment forming means is adapted so that the respective alignment means formed by the corresponding alignment forming means are formed to appear to the measuring apparatus different to any other component formed in the layers for facilitating identification of the alignment means by the measuring apparatus.

Preferably, each alignment forming means forms the corresponding alignment means of size sufficient to be captured by an optical microscope of the measuring apparatus .

Advantageously, each alignment forming means forms the corresponding alignment means as an alignment area in the respective fields of the corresponding layer, the respective alignment areas in the respective fields of the respective layers being identical.

Preferably, each alignment forming means forms a plain area surrounding the alignment area.

Advantageously, each alignment forming means is adapted so that the plain areas formed by the respective S97082 » alignment forming means which surround the corresponding alignment areas form respective origin defining areas which define the origin of the respective fields of the layers.

In one embodiment of the invention each alignment forming means is adapted so that each origin defining area formed by the corresponding alignment forming means defines a pair of intersecting side edges which intersect at the origin of the corresponding field.

In one embodiment of the invention each alignment forming means is adapted so that each alignment area formed by the corresponding alignment forming means defines an alignment point which is spaced apart from the origin of the corresponding field.

Another embodiment of the invention each alignment forming means is adapted so that each alignment area formed by the corresponding alignment forming means defines a pair of intersecting side edges, which define the alignment point at their point of intersection.

In a further embodiment invention each alignment forming means is adapted so that each alignment area is of triangular shape, the alignment point being defined by a corner of the triangle which is closest to the S979629 origin.

In a further embodiment of the invention each alignment forming means is adapted so that one of the side edges defined by each alignment area which defines the alignment point is spaced apart from and parallel to one of the side edges defined by the corresponding origin defining area which defines the corresponding origin.

In a still further embodiment of the invention each 10 alignment forming means is adapted so that the parallel side edges of the respective corresponding alignment areas and origin defining areas extend parallel to a Yaxis of the corresponding fields.

Preferably, each alignment forming means is adapted so 15 that each alignment area is formed wholly within and completely surrounded by the corresponding origin defining area.

In one embodiment of the invention each alignment forming means is adapted so that the respective origin defining areas are formed in corresponding border areas which defines the corresponding fields.

In another embodiment of the invention each alignment forming means is adapted so that each origin defining area is of square shape, each side edge being of length substantially similar to the width of the border area defining the corresponding field.

Preferably, the origin of each field is the origin of that field as determined by the measuring apparatus.

Ideally, the locations at which the alignment means, the critical dimension test means and the test areas are to be formed are identified in computer readable form for entering and storing in the measuring apparatus.

Preferably, the locations at which the alignment means, the critical dimension test means and the test areas are to be formed are identified by their respective X and Y coordinates.

In one embodiment of the invention the location of each critical dimension test means is computed by summing the X and Y co-ordinates of the reference point of the corresponding test area from the origin, and the X and Y co-ordinates of the critical dimension test means from the reference point of the corresponding test area.

S97 0 62 9 In another embodiment of the invention the location of each critical dimension test means is stored as X and Y co-ordinates from the origin.

Further the invention provides a combination of a plurality of masks of a set of masks for use in manufacturing a semi-conductor IC wafer in a production run of similar IC wafers for facilitating set-up of measuring apparatus for testing a critical dimension of a component on at least one layer of the wafer, each mask defining a field of the IC wafer, and each mask for use in forming a corresponding layer which comprises a component the critical dimension of which is to be tested comprising an alignment forming means for forming a corresponding alignment means in each field in the corresponding layer of the wafer for facilitating a determination of the orientation of the wafer in the measuring apparatus, the alignment means of the respective layers being identical for facilitating identification by the measuring apparatus, and the alignment forming means being located on the respective masks so that each alignment means is formed in the corresponding layer adjacent to but off-set from the origin of the corresponding field, and so that the offsets of the respective alignment means from their corresponding origins are similar for all the layers in 597 0 62 9 which the alignment means are formed, at least one critical dimension test forming means for forming a corresponding critical dimension test means in each of the fields in the corresponding layer of the wafer, each critical dimension test forming means being located for forming the corresponding critical dimension test means at a location in the respective field spaced apart from the alignment means and the origin of the corresponding field; and a means being provided for identifying the location at which the alignment means are to be formed in the layers of the wafer with reference to the origin of the respective fields, and the location at which the respective critical dimension test means are to be formed in the layers of the wafer with reference to the location of one of the alignment means and the origin of the corresponding field.

Further the invention provides a semi-conductor IC wafer manufactured using the combination of masks according to the invention.

Additionally, the invention provides a semi-conductor IC wafer manufactured using the masks prepared by the method according to the invention.

Further the invention provides a method for setting up « 97 062 # measuring apparatus for testing a critical dimension of a component formed in one of the layers of an IC wafer which has been formed by one or more of the masks prepared by the method according to the invention, the method for setting up the measuring apparatus comprising the steps of initially entering into measuring apparatus the location of the alignment means with reference to the origin of one of the corresponding fields of the wafer, and storing this location for use in subsequently locating two alignment means of a wafer, the origin being the origin as determined by the measuring apparatus, and then entering the location of each critical dimension test means for each layer with reference to the origin or the alignment means.

In one embodiment of the invention the location of each critical dimension test means is entered into the measuring apparatus by way of it's X and Y coordinates from the origin.

In another embodiment of the invention the location of each critical dimension test means is entered into the measuring apparatus by down loading the respective locations from the storing means. 07 0 62 9 In a further embodiment of the invention the location of the alignment means, is entered into the measuring apparatus by down loading the X and Y coordinates of the alignment means from the storing means.

A method for testing a critical dimension of a component formed in a layer of an IC wafer which has been formed by one or more of the masks prepared by the method according to the invention, and in which the measuring apparatus has been set-up according to the method according to the invention, the method for testing the critical dimension comprising the steps of loading the IC wafer into the measuring apparatus, determining the orientation of the IC wafer in the apparatus by moving one of the IC wafers and an optical microscope of the measuring apparatus for aligning one of the alignment means in the layer and the optical microscope, recording the location of the alignment means on the layer, moving one of the IC wafers and the optical microscope for aligning another of the alignment means in the layer and the optical microscope, recording the location of that alignment means on the layer, determining the orientation of the IC wafer in the measuring apparatus by determining the off-set of one of the two alignment means from its properly aligned position, and moving one of the IC wafers and an electron beam scanning microscope of the 597 0 62 9 measuring apparatus at low resolution so that one of the critical dimension test means and the electron beam scanning microscope are aligned with each other, operating the electron beam scanning microscope at high resolution focused on the critical dimension test means, scanning the critical dimension test means with the electron beam microscope operating at the high resolution, and reading signals from the electron beam scanning microscope for determining the critical dimension of the critical dimension test means, the distance and direction of travel of the one of the IC wafers and the electron beam scanning microscope to optical microscope to the critical dimension test means being determined from the entered locations of the critical dimension test means.

In one embodiment of the invention the one of the wafer and the electron beam scanning microscope is moved for sequentially aligning the respective critical dimension test means of the respective fields of the layer with the electron beam scanning microscope for determining the critical dimensions of the respective critical dimension test means from signals from the electron beam scanning microscope.

The invention will be more clearly understood from the following description of a preferred embodiment thereof S97 0 62 9 which is given by way of example only with reference to the accompanying drawings, in which: Fig. 1 is a diagrammatic plan view of a layer of a semi-conductor IC wafer, Fig. 2 is an enlarged diagrammatic plan view of a portion of the layer of the semi-conductor IC wafer of Fig. 1, Fig. 3 is a further enlarged diagrammatic plan view of a detail of the layer of the semiconductor IC wafer of Fig. 1, Fig. 4 is a diagrammatic plan view of a mask according to the invention for use in patterning the layer of the semi-conductor IC wafer of Fig. 1, Fig. 5 is an enlarged diagrammatic plan view of a detail of the mask of Fig. 4, Figs. 6(a) to (c) are enlarged diagrammatic plan views of details of a layer of the semi-conductor IC wafer of Fig. 1, and Figs. 7(a) to (c) are enlarged diagrammatic plan 597 0 82 9 views of details of the mask of Fig. 4.

Referring to the drawings there is illustrated a mask according to the invention which is indicated generally by the reference numeral 1, which is one of a plurality of masks which form a set of masks for patterning the layers of a semi-conductor IC wafer which is indicated generally by the reference numeral 2. Each mask 1 is of size sufficient for patterning one field 3 of the corresponding layer of the IC wafer 2. The manufacture, testing and general construction of such IC wafers, will be well known to those skilled in the art.

Typically, such wafers are formed on a silicon substrate which is circular in plan view having a portion removed along a cord for forming a straight edge 4. The straight edge 4 facilitates alignment of the substrate in the various apparatus used in the production process for forming and testing the wafer 2. Conductive and insulating and other layers are sequentially formed on the silicon substrate which eventually form the integrated circuits. The layers are laid down by subjecting the substrate and the layers previously formed thereon to various gasses for forming conductive layers, insulating layers and the like. Each layer is patterned by exposing a 7 0 62 9 photosensitive or a photoresist material deposited on the layer to one or more of the corresponding masks 1. This will be known to those skilled in the art.

In this embodiment of the invention the apparatus for forming and testing the IC wafers divides the substrate into a plurality of imaginary fields of similar size, which correspond with the fields 3 which are formed by the respective masks 1. Each field 3 is sub-divided into a plurality of similar size cells 5. Adjacent fields 3 are separated from each other by border areas, which are referred to as scribes 6. Scribes 7 within the fields 3 divide each field 3 into the cells 5 in this case sixteen cells 5 per field 3. Each cell 5 comprises one integrated circuit (not shown). When all the layers of the wafer 2 have been formed, the wafer 2 is cut along the scribes 6 and 7 for separating the respective integrated circuit chips from the wafer.

Each layer is patterned by indexing the corresponding mask 1 across and down the substrate for sequentially patterning the fields 3 of the layer, typically, the substrate is moved within the exposure apparatus so that the fields 3 are patterned from left to right. After patterning of the layer has been completed, the wafer 2 is removed from the exposure apparatus and placed in apparatus for etching or other appropriate S97 0 6 2 9 step in the manufacturing process.

The masks 1 according to the invention, each comprise an alignment forming means, namely, an alignment forming area 10 for patterning an area in each field of the corresponding layer for forming an alignment means, namely, an alignment area 11 in the respective fields 3 of the layer of the wafer 2. The alignment areas 11 are formed on the wafer 2 for facilitating determination of the orientation of the wafer 2 in measuring apparatus for measuring critical dimensions of a component or components in each field. The alignment forming areas 10 on the masks 1 of the set of masks are identical to each other, and are located in identical locations for forming the alignment areas 11 on the respective layers of the wafer 2 at identical locations relative to an origin 12 of the corresponding fields. The origins 12 coincide with the origins of the respective fields as defined by the measuring apparatus, which in this embodiment of the invention is an automated critical dimension scanning electron microscope. In this case, the automated critical dimension scanning electron microscope determines the origin 12 of each field 3 as being the bottom left hand corners of the respective fields 3.

In this embodiment of the invention the alignment 5870629 forming area 10 is of triangular shape for forming the alignment area 11 as a triangle which is of size sufficient to be captured by an optical microscope of the automated critical dimension scanning electron microscope. The alignment area 11 defines an alignment point 14 which is spaced apart from the origin 12. The alignment point 14 is defined by the point of intersection of side edges 15 and 16 of the alignment area 11. The location of the alignment point 14 for the respective fields is identified with reference to the origin 12 of the corresponding field. In other words, the off-set of the alignment point 14 from the corresponding origin 12 is recorded and stored in software by the X and Y coordinates of the alignment point 14 relative to the origin 12, and as mentioned above, the off-sets of the respective alignment points 14 from the corresponding origins 12 formed in the respective layers by all the masks of the set of masks are identical.

The alignment forming area 10 also forms a plain origin defining area 18 which completely surrounds the alignment area 11 for facilitating identification of the alignment areas 11 by the optical microscope. Side edges 19 and 20 of the origin defining area 18 define the origin 12 of the respective fields 3 at their point of intersection. The origin defining areas 18 formed δ97 0 62 9 by the alignment forming areas 10 of the respective masks 1 are identical and are located within one of the scribes 6 adjacent the bottom left hand corner of the respective fields 3. Each origin defining area 18 is of square shape, the length of each side being similar to the width of the scribe 6.

Each mask 1 which is provided for patterning a layer of the wafer 2 for forming a component or components, the critical dimensions of which are to be subsequently tested comprises a plurality of test area forming means, namely, test area forming areas 25 for forming corresponding test areas 26 in the scribes 6 and 7 in the fields 3 of the corresponding layer. The test area forming areas 25 in each of the masks 1 are formed in corresponding identical locations on the respective masks, and are all of identical size and shape. In this way, the test areas 26 formed in the respective layers are of identical shape and size, and are formed at identical corresponding locations.

Each test area 26 comprises a pair of intersecting side edges 27 and 28 which intersect to define a reference point 29 by which the location of each test area 26 is identified. The reference point 29 is the point of each test area 26 which is closest to the alignment point 14. The location of the reference points 29 are §97 0 62 9 identified with reference to the corresponding origin 12 and are recorded and stored in software by their respective X and Y coordinates.

Critical dimension test forming means, namely, critical dimension test forming features 30 are provided in some or all of the test forming areas 25 of the respective masks, for forming test features 31 in the corresponding test areas 26 which are formed by the masks 1 in the corresponding layers. The test features 31 which are formed in each layer are identical to the part of the component or components of that layer, the critical dimension of which is to be determined. Accordingly, by determining the critical dimension of the corresponding test features 31 in the fields 3 of the layer of the wafer 2 in the automated critical dimension scanning electron microscope, a determination of the critical dimension of the corresponding component may be made.

Only the test feature 31 or test features 31 which are relevant to a particular layer are formed in the test areas 26 of that layer. However, the critical dimension test forming features 30 are located at slightly different locations within the test forming areas 25 of the different masks, so that the test features 31 for the different layers are formed in 5970629 slightly different locations in the test areas 26 to avoid a build up of test features 31, one on top of the other in the finished wafer. For example, referring to Figs. 6 and 7 the test feature 31a may be a test feature for a metal layer, for example, a feature of a conductor. The test feature 31b may be a test feature for a poly layer, for example, an interconnect line.

The test feature 31c may be a test feature of a void.

The critical dimension test forming features 30 for forming similar test features 31 are located in the test forming areas 25 so that identical test features are formed in identical locations in their corresponding test areas. The locations at which the respective test features 31 are to be measured are recorded and stored in software with reference to the reference point 29 of their corresponding test areas 26. This is achieved by recording and storing the X and Y coordinates of the locations at which the respective test features 31 are to be measured from the reference point 29 of the corresponding test area 26. Accordingly, the location at which the respective test features 31 are to be measured with reference to the origin 12 can easily be computed by summing the X and Y coordinates of the reference point 29 of the corresponding test area 26 from the origin 12 and the X and Y coordinates of the location at which the test 5970629 feature 31 is to be measured from the corresponding reference point 29. According, since identical test features 31 are located at the same locations in the corresponding test areas 26, the number of X and Y coordinates which must be stored in order to enable the X and Y coordinates of the locations at which the test features 31 are to be measured with reference to the origin 12 is minimised.

Since the off-set of each alignment point 14 from the corresponding origin 12 of each field 3 is identical for all fields for all layers, when setting up the automated critical dimension scanning electron microscope it is necessary to enter in only one pair of X and Y coordinates which are stored in software for the alignment point 14, and these can readily easily be down loaded to the automated critical dimension scanning electron microscope. The X and Y coordinates of the locations at which the test features 31 are to be measured from the origin 12 are stored in software, these can readily easily be down loaded into the automated critical dimension scanning electron microscope when it is being set-up.

Typically, the pairs of X and Y coordinates from the origin 12 of the alignment points 14, the reference points 29 and the locations of the test features 31 are ί 7 0 ft 2 9 stored in computer readable digital form for a set of masks, and this can readily easily be down loaded into the automated critical dimension scanning electron microscope. Typically, the X and Y coordinates of the alignment points and the test features are stored in a look-up table in the automated critical dimension scanning electron microscope.

Furthermore, sets of masks for different IC wafers can be prepared with alignment forming areas 10 for forming alignment areas which are identical to the alignment areas 11, with test forming areas 25 for forming test areas which are identical to the test areas 26, and with critical dimension test forming features for forming test features which are identical to the test features 31. The different test features 31a, 31b and 31c, can be located at corresponding identical locations relative to the reference point 29 in the corresponding test areas 26. In such cases, computation of the X and Y coordinates from the origin 12 of the locations at which the test features 31 are to be measured can readily easily be computed with the minimum amount of data using suitable software, and can then be stored in software when the masks are being prepared. Accordingly, when setting up the automated critical dimension scanning electron microscope the X and Y coordinates with reference to origin 12 at which SJ7 0 62 9 the test features 31 are to be measured can readily easily be down loaded into the automated critical dimension scanning electron microscope, and since the X and Y coordinates with reference to the origin 12 of the alignment points 14 is identical for all masks of all IC wafers, the X and Y coordinates of the alignment point 14 can be permanently stored in the automated critical dimension scanning electron microscope. This significantly minimises the set-up requirements for a production run of IC wafers, and between production runs of different types of IC wafers. Additionally, when the masks for different IC wafers are provided with alignment forming areas for forming identical alignment areas, the automated critical dimension scanning electron microscope may be programmed to recognise just one type of alignment area.

When a layer of the wafer 2 has been formed and where that layer contains components and corresponding test features 31 the critical dimensions of which are to be measured the wafer 2 is placed in the automated critical dimension scanning electron microscope, and the microscope moves the IC wafer 2 for aligning the IC wafer with an optical microscope of the automated critical dimension scanning electron microscope. Typically, the microscope is aligned with an alignment area 11 on a central X-axis to the left hand side of a S 07 0 62 ? central Y-axis, for example, the alignment area 11a, see Fig. 1, and a reading of the position of the wafer 2 is recorded. The wafer 2 is then moved for aligning another of the alignment areas 11 with the optical microscope, typically, an alignment area 11 on the central X-axis on the right hand side of the central Yaxis of the wafer 2, for example, the alignment area lib, and another reading of the wafer 2 is recorded.

The angular orientation of the wafer 2 in the automated critical dimension scanning electron microscope can thus be determined from the two readings. The automated critical dimension scanning electron microscope is now ready for measuring the test features 31 in the respective test areas 26 in the respective fields 3 in the layer of the wafer 2. The wafer 2 is sequentially stepped from test area 26 to test area 26 in each field commencing, typically, with the top right hand field 3 and the electron beam scanning microscope at low resolution is aligned each time with the corresponding test feature 31. Once the electron beam scanning microscope has been aligned with the test feature 31 the electron beam scanning microscope is operated at high resolution and is focused on the test feature 31, at the location at which the test feature 31 is to be measured. The electron beam scanning microscope scans the test feature 31 for determining the critical dimension of the test feature 31, for in 597 0 62 9 turn determining the corresponding critical dimension of the component, the dimension of which is to be measured. The position to which the wafer 2 is to be moved each time for aligning the test feature 31 to be measured with the optical microscope is determined by reading the X and Y coordinates of the locations of the test features 31 at which the critical dimension is to be determined from the look-up table in the automated critical dimension scanning electron microscope. By determining the orientation of the IC wafer in the automated critical dimension scanning electron microscope correction for any minor misalignment of the wafer in the microscope can readily be compensated for by software in the microscope.

Accordingly, it will be readily apparent that by providing the masks 1 of the set of masks according to the invention for each type of IC wafer, computation of the X and Y coordinates of the locations at which the test features 31 are to be measured with reference to the origin 12 is significantly simplified.

Additionally, and importantly set-up of the automated critical dimension scanning electron microscope for measuring the critical dimensions of components in the respective IC wafers is likewise significantly simplified, and the time required for setting up the automated critical dimension scanning electron microscope is minimised.

Claims (5)

1. A method for preparing a plurality of masks of a set of masks for use in manufacturing a semi-conductor IC wafer in a production run of similar IC wafers for facilitating set-up of measuring apparatus for testing a critical dimension of a component on at least one layer of the wafer, each mask defining a field of the IC wafer, the method comprising the steps of: providing on each one of the masks of the set of masks which are for use in forming the layers comprising respective components the critical dimension of which are to be tested an alignment forming means for forming a corresponding alignment means in each field in the corresponding layer of the wafer for facilitating a determination of the orientation of the wafer in the measuring apparatus, the alignment means of the respective layers being identical for facilitating identification by the measuring apparatus, and the alignment forming means being located so that each alignment means is formed in the corresponding layer adjacent to, but off-set from, the origin of the corresponding field, and so that the off-sets of the respective alignment means from their corresponding origins are similar for all the layers in which the alignment means are formed, at least one critical dimension test forming means 5970629 for forming a corresponding critical dimension test means in each of the fields in the corresponding layer of the wafer, each critical dimension test forming means being located for forming the corresponding critical dimension test means at a location in the respective fields spaced apart from the alignment means and the origin of the corresponding field; and identifying the location at which the alignment means are to be formed in the layers of the wafer with reference to the origin of the respective fields, and identifying the location at which the respective critical dimension test means are to be formed in the layers of the wafer by the corresponding critical dimension test forming means with reference to the location of the alignment means or the origin of the corresponding field.

2. A method for preparing a plurality of masks of a set of masks for use in manufacturing a semi-conductor IC wafer in a production run of similar IC wafers for facilitating set-up of measuring apparatus for testing a critical dimension of a component on at least layer of the wafer, each mask defining a field of the IC wafer, the method being substantially as described herein with reference to and as illustrated in the accompanying drawings. *>97 0 92 9

3. A combination of a plurality of masks of a set of masks for use in manufacturing a semi-conductor IC wafer in a production run of similar IC wafers for facilitating set-up of measuring apparatus for testing a critical dimension of a component on at least one layer of the wafer, each mask defining a field of the IC wafer, and each mask for use in forming a corresponding layer which comprises a component the critical dimension of which is to be tested comprising an alignment forming means for forming a corresponding alignment means in each field in the corresponding layer of the wafer for facilitating a determination of the orientation of the wafer in the measuring apparatus, the alignment means of the respective layers being identical for facilitating identification by the measuring apparatus, and the alignment forming means being located on the respective masks so that each alignment means is formed in the corresponding layer adjacent to but off-set from the origin of the corresponding field, and so that the offsets of the respective alignment means from their corresponding origins are similar for all the layers in which the alignment means are formed, at least one critical dimension test forming means for forming a corresponding critical dimension test means in each of the fields in the corresponding layer of the wafer, each critical dimension test forming 4970 82 9 π means being located for forming the corresponding critical dimension test means at a location in the respective field spaced apart from the alignment means and the origin of the corresponding field; and a means being provided for identifying the location at which the alignment means are to be formed in the layers of the wafer with reference to the origin of the respective fields, and the location at which the respective critical dimension test means are to be formed in the layers of the wafer with reference to the location of one of the alignment means and the origin of the corresponding field.

4. A combination of a plurality of masks of a set of masks for use in manufacturing a semi-conductor IC wafer in a production run of similar IC wafers for facilitating set-up of measuring apparatus for testing critical dimensions of components on respective layers of the wafer, each mask defining a field of the IC wafer, the masks being substantially as described herein with reference to and as illustrated in the accompanying drawings .

5. A semi-conductor IC wafer manufactured using the combination of masks as claimed in Claim 3 or 4.