IES83744Y1 - A method and device for interfacing two incompatible devices - Google Patents

Abstract

ABSTRACT A CAPl—to—Synchronous serial bridge device (1) is provided for interfacing a CAPI compatible device provided by a laptop computer (2) and a synchronous serial compatible device provided by an encryption device (3). The CAPI-to-Synchronous serial bridge device is in the form of a PCMCIA card (6) installed on the laptop (2), and is coupled to the encryption device (3) for communicating data between the encryption device (3) and a CAPI application (23) installed on the laptop (2). The CAPI application (23) sends CAPI messages to the CAPI-to-Synchronous serial bridge device (1) when it requires data from the encryption device (3). A compact disk (9) in the CD ROM drive of the laptop (2) stores predetermined instructions as CAPI software functions for instructing a microprocessor (7) on the PCMCIA card (6) to create and operate an interface communication link between the CAPI application (23) and the encryption device (3) in response to the microprocessor (7) receiving CAPI messages from the CAPI application (23).

Description

A method and device for interfacing two incompatible devices The present invention relates to a method and a device for interfacing two incompatible devices, and in particular, the invention relates to a CAP|— to- Synchronous serial bridge device for providing a communication link between a Common Application ISDN Programming compatible device and a synchronous serial compatible device.

Telecommunication standards provides the industry with a framework that allows telecommunication devices from various telecommunication solution providers to communicate with each other. Low to medium cost telecommunication devices such as mobile phones and computers have a relatively short technology life span.

Demand by consumers for the latest available features ensures that these devices are constantly upgraded to the latest technology and are designed to be compatible with the latest standards. The establishment of ISDN (integrated Services Digital Network) networks and the associated telecommunication revolution resulted in a telecommunication standard known as Common Application ISDN Programming Interface (CAPI) that provides a framework for developers of ISBN hardware and software solutions which standardises the industry for developing compatible solutions.

However, the technology associated with high cost telecommunication devices such as non-standard encryption devices have a much longer life span. Due to the relatively small number of consumers which require such high cost devices as compared with the demand for mobile phones, and the relatively high cost associated with upgrading such devices, the technology associated with such devices and the telecommunication standards associated with them is archaic when compared with modern telecommunication devices. Such archaic devices are still capable of adequately fulfilling their primary role in a modern communication network. However, due to the fact that they were designed to be synchronous serial ‘compatible they are unable to communicate directly with modern CAPI compatible devices. Most modern telecommunications networks tend to incorporate CAPI compatible devices such as PCs and laptops. Typically in mobile hardware solutions, routers are required to interface modern CAPI technology with synchronous serial hardware.

There is therefore a need for a mobile/laptop based CAPl- to-Synchronous serial bridge device for facilitating communication between a CAPI compatible device and a synchronous serial compatible device without the need to incorporate expensive hardware in the telecommunications network.

The present invention is directed towards providing such a device.

According to the invention there is provided a CAPl- to-Synchronous serial bridge device for interfacing a CAPI compatible first device and a synchronous serial compatible second device, the CAPl- to-Synchronous serial bridge device comprising a first receiving means for receiving a CAPI message from the first device, an executing means for converting the received CAPI message to a synchronous command, a first relaying means for relaying the synchronous command to the second device, a second receiving means for receiving data from the second device in response to the synchronous command, and a second relaying means for relaying the data received from the second device to the first device.

In another embodiment of the invention the CAPl- to—Synchronous serial bridge device comprises a first establishing means for establishing if the second device is operable to interface with the CAPl- to-Synchronous serial bridge device.

In one embodiment of the invention the CAPl- to-Synchronous serial bridge device comprises a storing means for storing predetermined instructions as CAPI software functions for instructing the executing means to execute an operation in response to receiving a CAPI message. in another embodiment of the invention the storing means comprises predetermined operating instructions for instructing the first device to provide a framework for facilitating the communication of data between the CAPl- to-Synchronous serial bridge device and the first device.

In one embodiment of the invention the first device is communicable with the storing means for reading instructions stored thereon.

In another embodiment of the invention the storing means is provided by an electronic storing means, advantageously, the storing means is provided by at least one compact disk (CD).

In one embodiment of the invention the CAPl- to-Synchronous serial bridge device is operable to access resources located on the first device, advantageously, the CAPl- to-Synchronous serial bridge device is operable to access memory located on the first device.

In one embodiment of the invention the CAPl- to-Synchronous serial bridge device comprises a second establishing means for establishing if data is available from the second device.

In one embodiment of the invention the CAPl- to-Synchronous serial bridge device comprises a CAPI compatible interface means for interfacing with the first device and a synchronous serial interface means for interfacing with the second device.

In one embodiment of the invention the CAPI compatible interface means is directly linked to the first device.

In another embodiment of the invention the CAPl- to-Synchronous serial bridge device is operable to receive CAPI messages from at least one CAPI application which is co-operable with the first device for communicating data.

In one embodiment of the invention the CAPl- to-Synchronous serial bridge device comprises a monitoring means for monitoring incoming data to the CAPl- to- Synchronous serial bridge device from the first device for identifying if a CAPI message is received.

In one embodiment of the invention the CAPl- to-Synchronous serial bridge device comprises a central processing means, and preferably the central processing means is programmed to act as the monitoring means, the first establishing means, the second establishing means, the executing means, the first receiving means, the second receiving means, the first relaying means, and the second relaying means.

In one embodiment of the invention the monitoring means monitors for a CAPI_REG|STER message, and in response to a CAP|_REGISTER message monitors for further CAPI messages which may be subsequently received.

In another embodiment of the invention the monitoring means monitors for a CAPl_RELEASE message in response to receiving the CAPI_REGISTER message.

In a further embodiment of the invention the monitoring means is operable to monitor for the CAP|_RELEASE message for a first predetermined time period.

In one embodiment of the invention the monitoring means monitors during a second predetermined time period for a CONNECT_REQ message.

In another embodiment of the invention the monitoring monitors during a third predetermined time period for a LISTEN_REQ message in response to the monitoring means not receiving the CONNECT_REQ message during the second predetermined time period.

In a further embodiment of the invention the monitoring means monitors for the CAP|_RELEASE message in response to the monitoring means not receiving the L|STEN_REQ message during the third predetermined time period.

In one embodiment of the invention the monitoring means reverts to monitoring for the CAPI_REGISTER message in response to receiving the CAP|_RELEASE message.

In another embodiment of the invention the synchronous serial interface means is activated for receiving and transmitting data between the CAPl— to-Synchronous serial bridge device and the second device in response to receiving the CONNECT_REQ message.

In one embodiment of the invention the CAPl- to-Synchronous serial bridge device comprises an indicating means for indicating to the second device that it is operable to interface with it when the synchronous serial interface means is activated in response to receiving the CONNECT_REQ message.

In another embodiment of the invention the synchronous serial interface means is prepared for receiving and transmitting data between the CAP|— to-Synchronous serial bridge device and the second device in response to receiving the L|STEN_REQ message.

In one embodiment of the invention the first establishing means determines during a fourth predetermined time period if the second device is operable to interface with the CAP|- to-Synchronous serial bridge device. in a further embodiment of the invention the synchronous serial interface means is deactivated if the second device is not operable to interface with the CAP|- to- Synchronous serial bridge device during the fourth predetermined time period and the monitoring means subsequently monitors for the CAPl_RELEASE message. in one embodiment of the invention the monitoring means monitors during a fifth predetermined time period for the CAPl_RELEASE message in response to the second device being operable to interface with the CAPl— to-Synchronous serial bridge device during the fourth predetermined time period.

In a further embodiment of the invention the monitoring means reverts to monitoring for the CAPI_REGlSTER message in response to receiving the CAPl_RELEASE message during the fifth predetermined time period.

In one embodiment of the invention the monitoring means monitors during a sixth predetermined time period for a DiSCONNECT_REQ message in response to the CAPl_RELEASE message not being received during the fifth predetermined time penod.

In another embodiment of the invention the monitoring means monitors for the CAP|_RELEASE message in response to receiving the DiSCONNECT_REQ message.

In one embodiment of the invention the first establishing means establishes during a seventh predetermined time period if the second device is operable to interface with the CAPl— to-Synchronous serial bridge device in response to the monitoring means not receiving the DiSCONNECT_REQ message during the sixth predetermined time period.

In a further embodiment of the invention if the second device is not operable to interface with the CAPl— to-Synchronous serial bridge device during the seventh predetermined time period the monitoring means monitors for the CAP|_RELEASE message.

In one embodiment of the invention the monitoring means monitors during an eighth predetermined time period for a DATA_B3_REQ message if the second device is operable to interface with the CAPl- to—Synchronous serial bridge device during the seventh predetermined time period.

In one embodiment of the invention if the DATA_B3_REQ message was received during the eighth predetermined time period the executing means translates the DATA_B3_REQ message to a synchronous command for initiating the process for the transmission of data between the second device and the first device.

In a one embodiment of the invention the second establishing means establishes during a ninth predetermined time period if there is data available from the second device.

In another embodiment of the invention the CAPl- to—Synchronous serial bridge device indicates to at least one CAPI application that data is available from the second device.

In one embodiment of the invention the second receiving means retrieves data from the second device.

In another embodiment of the invention the second relaying means relays the retrieved data to the first device for communicating the data to at least one CAPI application.

In one embodiment of the invention the CAP|- to-Synchronous serial bridge device comprises a Personal Computer Memory Card international Association (PCMCIA) card. in another embodiment of the invention the CAP|- to-Synchronous serial bridge comprises a peripheral component Interconnect (PCI) card.

The invention also provides a method for interfacing a CAPI compatible first device and a synchronous serial compatible second device, the method comprising the steps of receiving a CAPI message from the first device, converting the received CAPI message to a synchronous command, relaying the synchronous command to the second device, receiving data from the second device in response to the synchronous command, and relaying the data received from the second device to the first device.

The invention will be more clearly understood from the following description of an embodiment thereof, which is given by way of example only, with reference to the accompanying drawings: Fig. 1 is a block diagram of a CAP|— to-Synchronous serial bridge device for interfacing a CAPl compatible first device and a synchronous serial compatible second device according to the invention, Fig. 2 is a block diagram illustrating the system level of a communication system utilising the device of Fig. 1, Fig. 3 is a block diagram of the communication system of Fig. 2, and Fig. 4 is a flow chart representation of a sub—routine under the control of which the CAPI-to-Synchronous serial bridge device of Fig. 1 operates.

Referring to the drawings, there is illustrated a CAPl— to-Synchronous serial bridge device according to the invention indicated generally by the reference numeral 1 for interfacing a CAPI compatible first device, in this case a laptop computer 2, with a synchronous serial compatible second device, in this case an encryption device 3.

The CAPl— to-Synchronous serial bridge device 1 is provided by a PCMCIA card 6 which comprises a central processing means provided by a microprocessor 7 for controlling the overall operations of the PCMCIA card 6, and a storing means which is provided by a CD (compact disk) 9 for storing operating instructions for instructing the laptop 2 to provide a CAPI interface layer 10 for facilitating the communication of data between the laptop 2 and the CAP|- to-Synchronous serial bridge device 1, and for storing predetermined instructions as CAPI software functions for instructing the microprocessor 7 to convert received CAPI messages into corresponding synchronous commands. A CAPI compatible interface means on the PCMCIA card 6 is provided by a PCMCIA plug 12 which is operable for releasably engaging a corresponding PCMCIA slot (not shown) of the laptop 2 for directly coupling the PCMCIA card 6 to the laptop 2. A synchronous serial interface means on the PCMCIA card 6 is provided by a port 15 which is adapted for receiving a connector 16 of a data bus 18 for communicating data between the encryption device 3 and the CAPl~ to-Synchronous serial bridge device 1.

The central processing unit (not shown) of the laptop 2 is communicable with a plurality of CAPI applications 20 which are installed on the laptop 2. The CAPl— to- Synchronous serial bridge device 1 is operable to receive a CAPI message from one of the CAPI applications 20 at any one time. The CAPl— to-Synchronous serial bridge device 1 appears to the operating system of the laptop 2 as a CAPI service provider.

The encryption device 3, the laptop 2, the CAPl— to-Synchronous serial bridge device 1 and one CAPI application, in this example a cryptographic application 23 form a communication system 26 which facilitates the exchange of data between two incompatible devices.

To open an interface communication link between the cryptographic application 23 and the encryption device 3, the cryptographic application 23 logs its presence to the CAPl— to-Synchronous serial bridge device 1 by sending a request in the format of a CAPI message to the CAPl— to-Synchronous serial bridge device 1 via the CAPI interface layer 10 of the laptop 2. The microprocessor 7 allocates memory (not shown) located on the laptop 2 for dealing with further requests from the cryptographic application 23, and monitors to establish if further requests are received from the cryptographic application 23. if the CAPl— to-Synchronous serial bridge device 1 receives a further request from the cryptographic application 23, the microprocessor 7 will execute an operation in response to the received request. The microprocessor 7 ceases to monitor for further requests from the cryptographic application 23 when the cryptographic application 23 logs off from the CAPl— to- Synchronous serial bridge device 1, and the memory which was allocated by the microprocessor 7 is released. initially the microprocessor 7 monitors incoming data to the CAPl- to-Synchronous serial bridge device 1 for a CAPl_REG|STER message. If the CAPl- to-Synchronous serial bridge device 1 receives the CAP|_REG|STER message from the cryptographic application 23, the microprocessor 7 monitors for further CAPI messages from the cryptographic application 23. If a CAP|_RELEASE message is received after the CAP|__REG|STER message, the microprocessor 7 reverts to monitoring the incoming data to the CAPl- to-Synchronous serial bridge device 1 for the next CAPl_REGlSTER message. If a CONNECT_REQ message is received, the port 15 is activated for receiving and transmitting data between the CAPl- to- Synchronous serial bridge device 1 and the encryption device 3, and the microprocessor 7 subsequently generates a Data Terminal Ready (DTR) signal which it relays to the encryption device 3. If a L|STEN_REQ message is received, the port 15 is prepared for transmitting and receiving data between the CAPl- to- Synchronous serial bridge device 1 and the encryption device 3.11‘ a CAP|_RELEASE message is received any time after the port 15 is activated, the port 15 returns to its inactive state, and the microprocessor 7 reverts to monitoring for the next CAPl_REG|STER message. If a D|SCONNECT_REQ message is received, the microprocessor 7 monitors for further CAPI messages from the cryptographic application 23.lf a DATA_B3_REQ message is received, the microprocessor 7 initiates the process for the transmission of data between the encryption device 3 and the cryptographic application 23.

Referring now to fig. 4 a flow chart of a sub-routine for controlling the operation of the CAPl- to-Synchronous serial bridge device 1 in response to the CAPl- to- Synchronous serial bridge device 1 receiving a CAPI message from the cryptographic application 23 will now be described. Block 30 initiates activation of the sub-routine in response to the CAPl- to-Synchronous serial bridge device 1 receiving the CAP|_REG|STER message from the cryptographic application 23, and controls the microprocessor 7 to allocate memory located on the laptop 2 for dealing with subsequent CAPI messages received from the cryptographic application 23. The sub-routine then moves to block 31 which determines during a first predetermined time of 10 milliseconds if the CAPl_RELEASE message is received. if block 31 determines that the CAP|_RELEASE message is received, the sub-routine moves to block 32 which causes the sub-routine to terminate resulting in microprocessor 7 releasing the memory which it had assigned for dealing with CAPI messages received from the cryptographic application 23.The sub-routine can only be reactivated if the block 30 receives another CAP|_REGlSTER message from either the cryptographic application 23 or some other CAPI application 20. If block 31 determines that the CAP|_RELEASE message was not received during the first predetermined time period, the sub-routine moves to block 33 which determines during a second predetermined time period of 10 milliseconds if the CONNECT_REQ message is received. If block 33 determines that the CONNECT_REQ message was received, the sub-routine moves to block 34 which activates the port 15 for receiving and transmitting data between the CAPI- Synchronous serial bridge device 1 and the encryption device 3. When the port 15 is fully activated the sub-routine moves to block 35 which instructs the microprocessor 7 to raise a data terminal ready (DTR) signal and to relay the DTR signal to the encryption device 3 for indication to the encryption device 3 that the CAPl- to- synchronous serial bridge device 1 is operable to interface with it. The sub-routine then moves to block 36 which will be described below.

Alternatively, if block 33 determines that the CONNECT_REQ message was not received during the second predetermined time period, the sub—routine would then move to block 37 which instructs the microprocessor 7 to determine during a third predetermined time period of 10 milliseconds if the LlSTEN_REQ message is received. If block 37 determines that the L|STEN_REQ message is received, the sub—routine moves to block 38 which prepares the port 15 for receiving and transmitting data between the CAPI-Synchronous serial bridge device 1 and the cryptographic application 23. When the port 15 is prepared for communicating data, the sub—routine moves to block 36. If block 37 determines that the LlSTEN_REQ message is not received, the sub—routine moves to block 31 which operates as previously described.

Block 36 determines if the encryption device 3 is operable to interface with the CAPI- to-Synchronous serial bridge device 1 during a fourth predetermined time period of 200,000 milliseconds in response to the CONNECT_REQ message or during an infinite time period in response to the L|STEN_REQ message. If block 36 determines that the encryption device 3 is not operable to interface with the CAPl— to- Synchronous serial bridge device 1, the sub—routine then moves to block 39 which deactivates the port 15 to it original state. When the port 15 is deactivated, the sub- routine moves to block 31 which operates as previously described. In the event that block 36 determines that the encryption device 3 is operable to interface the CAPI- to-Synchronous serial bridge device 1, the sub—routine moves to block 40 which affirms to the CAPI-Synchronous serial bridge device 1 that the interface communication link now exists between the cryptographic application 23 and the encryption device 3.

The sub-routine then moves to block 41 which determines during a fifth predetermined time period of 10 milliseconds if the CAPl_RELEASE message is received. If block 41 determines that the CAP|_RELEASE message is received during the fifth predetermined time period, the sub-routine moves to block 32 which causes the sub-routine to terminate resulting in the microprocessor 7 releasing the memory which it had assigned for dealing with CAPI messages if received from the cryptographic application 23.The sub-routine can only be reactivated if the block 30 receives another CAP|_REG|STER message from either the cryptographic application 23 or some other CAPI application 20.

If block 41 determines that the CAP|_RELEASE message is not received during the fifth predetermined time period, the sub-routine moves to block 42 which instructs the microprocessor 7 to determine during a sixth predetermined time period of 10 milliseconds if the DlSCONNECT_REQ message is received. If block 42 determines that the DlSCONNECT_REQ message is received during the sixth predetermined time period, the sub-routine moves to block 31 which operates as previously described. If block 42 determines that the D|SCONNECT_REQ message was not received, the sub-routine moves to block 43. Block 43 instructs the microprocessor 7 to determine during a seventh predetermined time period of 10 milliseconds if the encryption device 3 is operable to interface with the CAP|- to-Synchronous serial bridge device 1. If block 43 determines that the encryption device 3 is not operable to interface with the CAPl- to-Synchronous serial bridge device 1 during the seventh predetermined time period, the sub-routine moves to block 31 which operates as previously described.

In the event that block 43 determines that the encryption device 3 is operable to interface with the CAPl- to-Synchronous serial bridge device 1 during the seventh predetermined time period, the sub-routine moves to block 44. Block 44 instructs the microprocessor 7 to determine during an eighth predetermined time period of 10 milliseconds if the DATA_B3_REQ message is received. if block 44 determines that the DATA_B3_REQ message is received, the sub-routine moves to block 45 which instructs the microprocessor 7 to convert the DATA_B3_REQ message to a synchronous command for initiating the transmission of requested data by the cryptographic application 23 from the encryption device 3 to the cryptographic application 23. The sub-routine then moves to block 46 which instructs the microprocessor 7 to determine during a ninth predetermined time period of 10 milliseconds if any data is available from the encryption device 3. if block 46 determines that data is available from the encryption device 3, the sub-routine moves to block 47 which instructs the microprocessor 7 to retrieve the data from the encryption device 3 and to relay the retrieved data to the cryptographic application via the CAPI interface layer 10 of the laptop 2.

In use the PCMCIA card 6 is inserted into the PCMCIA slot of the laptop 2.The laptop 2 is powered up, the BIOS of the laptop 2 scans its PCMCIA bus for hardware. Once the CAPl— to-Synchronous serial bridge device 1 is detected, the operating system of the laptop 2 requests that the drivers associated with the PCMCIA card 2 are installed on the laptop 2, the CD 9 is inserted into the CD ROM disk drive (not shown) of the laptop 2. When the drivers are installed from the CD 9 on the laptop 2, the PCMCIA card 6 appears to the operating system of the laptop 2 as CAPI service provider. The encryption device 3 is coupled to the port 15 of the CAPl- to-Synchronous serial bridge device 1 by the connector 16 of the data bus 18.

The cryptographic application 23 calls the CAP|- to-Synchronous serial bridge device 1 by sending the CAPl_REGlSTER message to the CAP|- to-Synchronous serial bridge device 1 via the CAPI interface layer 10 of the laptop 2 to initiate the creation of an interface communication link between the cryptographic application 23 and the encryption device 3. The microprocessor 7 allocates memory (not shown) on the laptop 2 for dealing with requests from the cryptographic application 23 once it receives the CAPl_REGlSTER message from the cryptographic application 23. The microprocessor 7 monitors during a first predetermined time of 10 milliseconds the incoming data to the CAPl- to-Synchronous serial bridge device 1 for the CAPl_RELEASE message. If the CAPl_RELEASE message is received, the microprocessor 7 releases the memory which it allocated for the cryptographic application 23, and terminates operations until it receives a further CAPl_REGlSTER message from either the cryptographic application 23 or some other CAPl application 20. However, if the microprocessor 7 doesn't receive the CAPl_RELEASE message during the first predetermined time period, it subsequently monitors for the CONNECT_REQ message during a second predetermined time period of 10 milliseconds. If the microprocessor 7 receives the CONNECT_REQ message during the second predetermined time period, it activates the port 15 for transmitting and receiving data between the CAPI-Synchronous serial bridge device 1 and the encryption device 3. When the port 15 is activated the microprocessor 7 generates a Data Terminal Ready (DTR) signal and relays the DTR signal to the encryption device 3 for indicating to it that it is ready for the encryption device 3 to interface with it.

The microprocessor 7 subsequently determines during a third predetermined time period of 200,000 milliseconds if the encryption device 3 is operable to interface with the CAPl- to-Synchronous serial bridge device 1. If the encryption device 3 is inoperable to interface with the CAPl- to-Synchronous serial bridge device 1 during the third predetermined time period, the port 15 is deactivated and the microprocessor 7 monitors for the CAPl_RELEASE message from the cryptographic application 23. In the event that the encryption device 3 is operable to interface with the CAPl- to-Synchronous serial bridge device 1 during the third predetermined time period, the microprocessor 7 determines during a fourth predetermined time period of 10 milliseconds if the CAPl_RELEASE message is received. if the CAP|_RELEASE message was received during the fourth predetermined time period, the microprocessor 7 releases the memory (not shown) on the laptop 2 which it allocated for the cryptographic application 23, and it terminates operations until it receives a further CAPl_REGlSTER message from either the cryptographic application 23 or some other CAPI application 20. if the CAP|_RELEASE message was not received during the fourth predetermined time period, the microprocessor 7 determines during a fifth predetermined time period of 10 milliseconds if the D|SCONNECT_REQ message was received. In the event that the D|SCONNECT_REQ message was received during the fifth predetermined time period, the microprocessor 7 monitors for the CAPl_RELEASE message from the cryptographic application 23.

However, if the DlSCONNECT_REQ message was not received during the fifth predetermined time period, the microprocessor 7 determines during a sixth predetermined time period of 10 milliseconds if the encryption device 3 is operable to interface with the CAP|- to-Synchronous serial bridge device 1. In the event that the encryption device 3 is not operable to interface with the CAP|- to-Synchronous serial bridge device 1 during the sixth predetermined time period, the microprocessor 7 monitors for the CAPl_RELEASE message from the cryptographic application 23.|f the encryption device 3 is operable to interface with the CAP|- to-Synchronous serial bridge device 1 during the sixth predetermined time period, the microprocessor 7 determines during a seventh predetermined time period of 10 milliseconds if a DATA_B3_REQ message is received. In the event that the DATA_B3_REQ message is received during the seventh predetermined time period, the microprocessor 7 converts the DATA_B3_REQ message to a synchronous command for initiating the process for the transmission of data requested by the cryptographic application 23 from the encryption device 3 to the CAP|- to- Synchronous serial bridge device 1.The microprocessor 7 subsequently determines during an eighth predetermined time period of 10 milliseconds if any data is available from the encryption device 3. If data is available from the encryption device 3, the microprocessor 7 retrieves the data from the encryption device 3 and relays the data to the cryptographic application 23.

While the CAP|- to-Synchronous serial bridge device has been described as comprising a PCMCIA card, it will be readily apparent to those skilled in the art that the device may comprise a PCI card or any suitable hardware device operable to communicate with a CAPI compatible device and a synchronous compatible device.

While the CAP|- to-Synchronous serial bridge device has been described as being directly linked to the laptop, it is envisaged that the device may be provided as a portable independent device remotely linked to the CAPI compatible device.

While the CAP|— to-Synchronous serial bridge device has been described as comprising a port for interfacing with the synchronous serial compatible device, it is envisaged that any suitable interfacing means may be provided for interfacing with the synchronous serial compatible device.

While the CAP|- to-Synchronous serial bridge device has been described as performing operations within predetermined time periods, it will be appreciated that these predetermined time periods may vary.

The invention is not limited to the embodiment hereinbefore described which may be varied in construction and detail.

Claims (5)

1. A CAPl— to-Synchronous serial bridge device for interfacing a CAPI compatible first device and a synchronous serial compatible second device, the CAPl— to-Synchronous serial bridge device comprising a first receiving means for receiving a CAPI message from the first device, an executing means for converting the received CAPI message to a synchronous command, a first relaying means for relaying the synchronous command to the second device, a second receiving means for receiving data from the second device in response to the synchronous command, and a second relaying means for relaying the data received from the second device to the first device.

2. A CAPl— to-Synchronous serial bridge device as claimed in claim 1 in which the CAPl— to-Synchronous serial bridge device comprises a first establishing means for establishing if the second device is operable to interface with the CAPl— to- Synchronous serial bridge device.

3. A CAPl— to-Synchronous serial bridge device substantially as described herein with reference to and as illustrated in the accompanying drawings.

4. A method for interfacing a CAPI compatible first device and a synchronous serial compatible second device, the method comprising the steps of receiving a CAPI message from the first device, converting the received CAPI message to a synchronous command, relaying the synchronous command to the second device, 22 receiving data from the second device in response to the synchronous command, and relaying the data received from the second device to the first device.

5. A method for interfacing a CAPI compatible first device and a synchronous serial compatible second device, the method being substantially as described herein with reference to and as illustrated in the accompanying drawings. F.F. GORMAN & CO.