IES20010030A2 - Data communication - Google Patents

Abstract

A method and apparatus for data communication using signature sequences and spread spectrum techniques to reduce the effects of certain transmission impairments in a Wireless local area network (WLAN). The invention uses a number of correlators and M-ary Code Keying with a Supergold signature sequence for simultaneously generating a periodic signal for acquiring symbol synchronisation, a difference squarewave signal for acquiring and maintaining chip synchronisation and a sum signal for determining received signal strength and setting threshold levels. <Figure 2>

Description

DATA COMMUNICATION The present invention relates to data communication and more particularly, to data communication using spread spectrum techniques. The invention also relates to communication applications using signature sequences.

Spread spectrum communication techniques are used for information carrying signals in a variety of communication systems because of their ability to reduce the effects of certain transmission impairments. Many multi-user communication techniques suffer co-channel interference, multiple access interference and intersymbol interference. The use of spread spectrum transmission and reception attenuates these interference types.

In Local Area Networks (LANs) there is an increasing need for wireless access. This wireless access allows mobile computer users to remain in contact with a given corporate LAN over short distances. Currently available systems provide such connections using either radio or infrared communication technology. For certain system requirements, this communication is adequate. However, the data transmission rates achievable are relatively low and this significantly limits the number of applications to which the systems may be applied and implementation costs are often prohibitive.

Wireless local area network (WLAN) products were thus for a long time a specialty, made available by a small number of vendors and built according to meet proprietary requirements. The Institute for Electrical and Electronic Engineers (IEEE) in June 1997 formalized a standard that will control interoperability of such products known as 802.11. 25 While this standard will undoubtedly promote the growth of WLAN products, the problems of transmission rates, reliability and cost remain. One possible solution is obtained by the application of spread spectrum communication techniques using signature sequences. While implementations of this type overcome the traditional problems, it is difficult to synchronise data communication without the use of complex circuitry.

Synchronisation difficulties include symbol synchronisation, chip synchronisation anH OPEN TO PUBLIC INSPECTION UNDER SECTION 28 AND RULE 23 JNL No. QP SQ& INT CL , fobi. iSloo IE010030 signal strength measurements (SSM) as well as the problem of synchronisation maintenance.

One solution to these problems has been proposed by Haris for use used in the new 802.11 WLAN standard at 11 Mb/s. In common with most proposed solution there is an acquisition phase and a maintenance phase. Acquisition in this case, is accomplished using a single correlator and an embedded Barker sequence. Synchronisation is maintained using an early-late detector. While the previously know ‘Harris type’ transition detector solution is practical in a wide variety of applications, the early-late detector operates directly on the incoming sequence stream, which is composed of modified Walsh codes at the input. This leads to reliability problems in that quality of the signal cannot be guaranteed.

There is therefore a need for a method and apparatus, which will overcome the aforementioned problems.

It is an object of this invention to provide a method and apparatus for data communication which delivers synchronisation acquisition in terms of chip and symbol synchronisation and signal strength measurement.

It is a further object of the invention to provide synchronisation maintenance in terms of chip synchronisation.

It is a still further object of this invention to allow compatibility to synchronise across the various modes of communication.

Accordingly there is provided a method and apparatus for data communication in a WLAN network using M-ary signaling.

Preferably M-ary signaling is used for synchronisation of data communication in the network.

IE010030 Preferably the synchronisation scheme utilises Supergold structured codes for acquisition.

Ideally, the synchronisation scheme also utilises Supergold structured codes for maintenance.

In one arrangement maintenance is achieved using an early-late detector.

In a particularly preferred arrangement, synchronisation signals are derived at the output of a correlator bank during data detection wherein the incoming sequence stream incorporates structured codes as mentioned above. This provides a significant improvement in reliability in synchronisation resulting from an improved signal. This implementation allows for the codes to be used for all aspects of communication reducing circuit complexity and cost as well as component count and possibility for error during fabrication of data communication networks. Furthermore, the data communication method and apparatus are more resilient to noise as a result of implementation after correlation.

Preferably, the sum of the responses of all correlators to the repetitive periodic transmission of one code, is a constant.

Preferably, the difference between the sum of the responses of the odd-group correlators and the sum of the responses of the even-group correlators or vice versa, defines a periodic bipolar waveform.

In a preferred embodiment, the periodic bipolar waveform is a square waveform.

Preferably, a transition detector circuit is used at the correlator outputs deriving substantial signal to noise ratio benefit from the processing gain advantage of spread spectrum.

Ideally, the waveform has a period equaling half the chip rate.

IE010030 Preferably, the correlator coefficients are configured such that when one sample is taken per chip with all signals and correlation taken to be in bipolar form that the sum of the responses of all correlators to the repetitive periodic transmission of one code, is a constant Ideally also the difference between the sum of the responses of the odd-group correlators and the sum of the responses of the even-group correlators or vice versa, is a periodic bipolar waveform with a period equaling half the chip rate. Both of these properties being particularly useful for synchronisation acquisition purposes. Preferably, the difference is a square waveform.

Ideally, both the method and apparatus described above are formed for both acquisition and maintenance of synchronisation.

Ideally, a transceiver of the system is formed that implements the concept of acquire-andmaintain.

Preferably, a threshold value is determined in response to an operational mode governing the link.

In one arrangement the threshold may be lowered to half of the peak height if the midsamples are discarded. This later approach requires a further gating logic to block the midsamples from being passed onto the threshold circuitry Preferably the symbol acquisition circuitry will deliver a periodic single pulse with a periodicity equaling the symbol period.

Ideally, the time epoch of the pulse coincides with the peak sample in the upper waveform.

The invention will now be described more particularly with reference to the accompanying drawings, which show, by way of example only, one embodiment of data communication method and apparatus according to the invention. In the drawings: IE010030 Figure 1 shows a codebook used in synchronisation schemes of the invention; Figure 2 shows a correlators bank for use in the invention; Figure 3 shows packet synchronisation; Figure 4 shows a tapped delay line correlator; Figure 5 shows sum(0,2) and sum(l,3); Figure 6 shows symbol-synchronisation acquisition; Figure 7 shows operation of a symbol synchronisation acquisition scheme; Figure 8 shows symbol synchronisation declaration; Figure 9 shows a harris type transition detector; Figure 10 shows a sampling-dependant clock; Figure 11 shows a modified version of the harris type transition detector of figure 9.

Figure 12 shows a chip synchronisation detector; Figure 13 shows output of a supergold chip synchroniser under perfect and imperfect input waveform sampling; Figure 14 shows signal strength measurement unit; Figure 15 shows instantaneous signal strength; Figure 16 shows the three elements of acquisition; Figure 17 shows symbol synchronisation loss detection; Figure 18 shows mode ir( 1); Figure 19 shows synchronisation for mode ir(l); Figure 20 shows symbol synchronisation (normalised waveforms); Figure 21 shows output of chip synchroniser under perfect and imperfect input waveform sampling; Figure 22 shows instantaneous signal strength measurement; Figure 23 shows output of chip synchroniser under perfect and imperfect input waveform sampling; Figure 24 shows instantaneous signal strength measurement; Figure 25 shows mode ir(2); Figure 26 shows symbol synchronisation (normalised waveforms); IE010030 Figure 27 shows symbol synchronisation (normalised waveforms); Figure 28 shows instantaneous ssm (perfect synchronisation condition); Figure 29 shows output of chip synchroniser under perfect and imperfect input waveform sampling: i-channel; Figure 30 shows output of chip synchroniser under perfect and imperfect input waveform sampling: q-channel; Figure 31 shows mode ir(3); Figure 32 shows symbol synchronisation (normalised waveforms); Figure 33 shows instantaneous signal strength measurement; Figure 34 shows output of chip synchroniser under perfect and imperfect input waveform sampling: i-channel; Figure 35 shows output of chip synchroniser under perfect and imperfect input waveform sampling: q-channel; and Figure 36 shows mode ir(4).

For the purposes of this specification reference will be made to the codebook of Figure 1 used in the synchronisation method and apparatus of the invention. The codebook is used to set each of the coefficients of a bank of correlators for use in the invention shown in Figure2.

For convention, the first code, SO, is selected for periodic application to the input of the bank of correlators. The sum of the response of the Oth and 2nd correlators, denoted by Sum(0,2) (for the purposes of this specification the convention Sum(i,j) will be used to denote the summation of the ith and jth correlator outputs.), is an ideal impulse occurring at twice the symbol rate. Additionally, the sum of the outputs ofthe 1st and 3rd correlators, Sum(l,3), has the same property but is time-delayed by Va of a symbol period. The table shown below gives the profile and the relationship between the two summations, where the peak value of 16 has been normalised to unity.

Sum(0,2) 10000000100000001000 Sum(l,3) 00001000000010000000 IE010030 In addition use of the codebook in setting correlator coefficients in this way ensures that, providing one sample is taken per chip with all signals and correlation taken to be in bipolar form that:the sum of the responses of all correlators to the repetitive periodic transmission of one code, is a constant; and the difference between the sum of the responses of the odd-group correlators and the sum of the responses of the even-group correlators or vice versa is a periodic bipolar square waveform with a period equaling half the chip rate.

Both of these properties being particularly useful for synchronisation acquisition purposes : There are two elements to synchronisation in data communication, irrespective of data type, namely, the acquisition and maintenance of synchronisation.

Acquisition is carried out at the start of data transmission and its sole purpose is to acquire the incoming signal by aligning the receiver chip and symbol clocks with the incoming signal.

Maintenance techniques are used to maintain the chip and symbol clocks in line with the incoming signal during the transmission of the data.

Ideally, the receiver must be in synchronisation all the time with the transmitter. Consequently, synchronisation maintenance techniques are used to maintain both the chip and symbol clocks in line with the incoming signal. However, the availability of synchronisation related information for synchronisation updates may not be present all the time in the receiver. Hence, synchronisation maintenance techniques often adjusts synchronisation when possible, otherwise the receiver is made to flywheel.

For Synchronisation a simple protocol is imposed on the transceiver operation that basically implements the concept of acquire-and-maintain. The 802.11 standard packet IE010030 format, which has been adopted by the Harris/prism chip set, follows this concept. The protocol outline is shown in Figure 3.

No data is transmitted during the header section of the transmission. Both chip and symbol synchronisation and the signal strength are determined during this acquisition phase. Other aspects of synchronisation acquisition may be performed during this period.

Synchronisation which includes frequency and phase estimation, such as in RF systems does not form part of the current invention and is omitted for clarity.

In the data section, the receiver makes synchronisation updates when synchronisation related information becomes available from the samples of the received signal e.g. chip/symbol transitions. Alternatively the receiver is made to “flywheel”, when such information is not derivable from the samples of the received signal.

For chip synchronisation to be possible, two samples per chip are needed, thereby doubling the sampling rate. Thus the correlator is designed to have double the length of the delay line of the correlator to 32. From a detection point of view, the number of taps, however, may be kept at 16, where in this case, a tap is drawn from every other position in the delayline. The correlator design is shown in more detail in Figure 4 but this does not compromise the adopted synchronisation algorithms.

A perfect periodic impulse being obtained from the sum of the Oth and the 1st correlator output while transmitting code SO periodically ensures that the resultant zero sidelobe of the summed correlation occurs because of the relationship between code SO and code S2. This is also true for S4, S6, S8, S10 etc. Since this periodic impulse is at twice the symbol rate, some form of ‘frequency halving’ must be employed which removes the ambiguity in the symbol synchronisation point. For example, taking the odd peaks to correspond to the alignment of one complete received code, SO, within the delay line of the Oth correlator, the even peaks may be taken to correspond to the natural response of the 2nd correlator to the code SO. In this context, this translates to an inherent discrepancy as to which of the peaks of Sum(0,2) corresponds to the correct timing edge. Given that, say, the odd peaks occur when the received SO resides completely inside the Oth correlator delay-line; and the fact IE010030 that the codes themselves are orthogonal, then at each odd/even peak epoch of the Sum(0,2), a decision can be made whether the peaks correspond to the correct timing edge or not, on the basis of the output of the correlators Corr(SO) and Corr(S2). If the output of the Oth correlator is greater than the output of the 2nd then the peak corresponds to the correct timing edge.

Figure 5 shows the summing of Corr(SO) and Corr(S2) and the summing of Corr(Sl) and Corr(S3) in response to the periodic transmission of code SO. The former and latter are marked with *’s and o’s respectively. Figure 6 shows the implementation of the symbol synchronisation acquisition scheme, where it is assumed that code SO is periodically transmitted. The summation of correlators Corr(SO) and Corr(S2) is used as inputs to a thresholding circuit, which uses a pre-specified threshold. The outputs of the correlators of interest are also applied to a comparison logic which, when strobed, determines if the output of Corr(S0) is greater than Corr(S2).

Every time Sum(0,2) passes the threshold, a comparison is made between the output Corr(S0) and Corr(S2). If the output of Corr(S0) is greater than Corr(S2), then a symbol synchronisation is declared by driving the output of the comparison logic high; otherwise the output is made low.

It is clear from the results of Figure 5 that the threshold of Figure 6 must be chosen carefully and its value may very well be affected by which communication mode the link is operating in.

When the symbol SO is applied periodically, and Corr(SO) and Corr(S2) outputs are applied to the comparison circuit and Sum(0,2) is fed to the input of the threshold. Here, it suffice to use a threshold of height % of the peak sample value to detect the time epoch of the peak sample and suppressing all the others. The threshold may be lowered to half of the peak height if the mid-samples are discarded. This later approach requires a further gating logic to block the mid-samples from being passed onto the threshold circuitry. Such gating logic will in one arrangement use the derived chip clock. The later approach will increase the IE010030 ίο probability of correct synchronisation, resulting in less probability of missed data. This preferred solution illustrates the reason that flywheeling is not being used.

The upper waveform in Figure 7 constitutes the Sum(0,2), which is applied to the thresholding circuit. After the thresholding and comparison, the output obtained from the comparison circuitry is shown as the lower waveform in Figure 7. It can clearly be seen that the symbol acquisition circuitry of Figure 6 will deliver an ideal periodic single pulse with a periodicity equaling the symbol period. Moreover, the time epoch of the pulse coincides with the peak sample in the upper waveform.

During the acquisition phase, symbol synchronisation is declared with a high degree of certainty after the successful acquisition of several contiguous symbols. A symbol synchronisation assessment circuit is therefore needed to track the output of the symbol synchronisation acquisition of Figure 6, and declare if the symbol timing has been successfully acquired with sufficient certainty. One such circuit is shown in Figure 8.

Here, a counter, which counts a pre-defined number of sampling clock pulses, is initialised on the occurrence of the first symbol pulse emerging from the symbol synchronisation acquisition circuitry. The counter’s all-zero state is detected and an add-and-accumulate circuit is used to count the number of times the counter all-zero state coincides with the presence of a pulse in the output of the symbol synchronisation acquisition circuitry. Symbol synchronisation is declared when the accumulator contents exceed a constant prespecified value, C out of L symbols.

The Harris chip set (described in brief above) takes two samples per chip. Ideally, a sample is required to be placed in the middle of one chip. The other sample will fall in the mid point between the mid samples of the two consecutive chips, i.e. on the chip transition in the case when there is a chip transition. Chip synchronisation adjustment can only be made when a chip transition occurs and is detected.

When a chip transition takes place then, with two samples per chip the following sample patterns shown in Figure 9 are possible. The two end samples shown in the figure are used IE010030 for correlation, the mid and end samples are used for synchronisation purposes. The procedure is as follows: Determine if a chip transition has occurred. A chip transition occurs when the two end samples have different signs. The chip transition flag is set.

If chip transition occurs then determine if a chip synchronisation error occurred. This is done by comparing the sign of the mid sample with the signs of the two end samples.

If the sign of the mid sample is the same as the RHS sample, then sampling is speeded up (Late flag is set). Else sampling is slowed down (Early flag is set).

Note this technique will always make a synchronisation adjustment when there is a chip transition. The logic required for the Harris chip tracking is also shown in Figure 9.

Three outputs are produced. The chip transition flag (F) indicates that chip synchronisation information is available when driven to logic Τ’. When set, the early (E) and late (L) flags indicate that the sampling clock is early and late, respectively.

The difference between the sum of the responses of the odd-group correlators and the sum of the responses of the even-group correlators is a periodic square waveform with a period equaling half the chip period. This is the case when the sampling is perfect, i.e. one sample lies in the middle of the chip while the other lies on a chip transition. The middle plot of Figure 10 depicts this case.

The effect of early, perfect and late sampling on the resultant periodic square waveform is also given in Figure 10. The early and late conditions can he seen from the two plots by noting the start of the waveform in each plot. The three shown waveforms constitute the different clock profiles obtained in response to the periodic transmission of code SO, where two samples per chip were taken and the correlators are based on Figure 4.

While when the sampling is perfect, samples fall at the maximum (+16) and the minimum (-16), whilst other samples fall exactly at the middle point between the two waveform IE010030 extremes indicating the usefulness of a circuit based on the Harris type transition detector can be used, this circuit is used at the correlator outputs and therefore, derives substantial signal to noise ratio benefit associated with the processing gain advantage of spread spectrum.

Figure 11 shows a modified version of the Harris type transition detector of Figure 9. The modification is required because it is desired to derive chip synchronisation using the signal available in Figure 2, which is no longer binary in general.

The addition of a thresholding logic, denoted by T in the diagram, essentially converts the potentially non-binaiy clock of Figure 2, into a three-level waveform. Consider the third sample (Smp(3)), which can take a value between -16 and +16. The value of Smp(3) is represented in sign (one bit, al) and magnitude (multiple bits, bl) format and are applied to the level discrimination circuit confined within the shaded box in the figure. The outputs of the level discrimination circuit are the sign bit a2 and the flag bit b2. The thresholding circuit denoted by T, gives a logical T if its input is greater than the threshold level‘T’ and zero otherwise. The overall action of the level discriminator is described by the truth table below.

Input Range al bl a2 b2 Equivalent Decimal Representation of a2, b2. ip>+T 0 >h 0 1 1 0 < ip < +T 0 0 0 0 -T < ip < 0 1 0 0 0 ip<-T 1 >h 1 1 -1 The above described level discrimination circuit is applied to the other two samples, Smp(l) and Smp(2), in the delay line to derive their respective (a2,b2) values. The outputs (a2,h2) from all the three samples are employed as inputs to a series of adders. The threshold circuit T is used to determine the synchronisation status (E, L and F), that implements the function shown in the following function.

IE010030 Τ if |ζρ| > Ο Ο otherwise For the waveforms of Figure 10, the 4 possible scenarios of the sample distribution for the early, late and perfect sampling conditions are described in the tables below, for a threshold value of T=8. Note, scenario 1 and 2 correspond to the high-to-low and low-to-high chip transitions, respectively.

Perl ect Scenario 1 Perfect Scenario 2 Smp(l) Smp(2) Smp(3) Smp(l) Smp(2) Smp(3) +16 0 -16 -16 0 +16 (a2,b2) +1 0 -1 -1 0 +1 Adders +2 +1 +1 -2 -1 -1 F E L +1 +1 +1 +1 +1 +1 Early Scenario Late Scenario Smp(l) Smp(2) Smp(3) Smp(l) Smp(2) Smp(3) +16 +16 -16 -16 +16 +16 (a2,b2) +1 +1 -1 -1 +1 +1 Adders +2 0 +1 -2 -2 0 F +1 +1 E 0 +1 L +1 0 A new chip synchronisation module forming part of the invention is shown in Figure 12.

The clock obtained from processing the output of the bank of correlators is input directly to the modified transition detector. The outputs of the transition detector are then used to affect the sampling of the input waveform to the bank of correlators.

In Figure 13, three plots are given which show the effect of prefect and imperfect sampling 15 of the input waveform to the bank of correlators upon the outputs of the chip synchronisation status detector.

IE010030 It is important to note that the transiton detector described above implements the chip synchronisation tracker of Figure 5 before correlation, that is to say at chip level. For this reason, such detectors specify that a positive signal-to-noise ratio is required in the chip bandwidth limiting the proposed solution. In contrast, the technique of the invention while similar to the traditional detector in concept, is implemented after correlation and does not require this restriction on the SNR ratio in the chip bandwidth, and thus has a broader dynamic SNR range of operation.

The sum of the responses of all the correlators (see above) was indicated as being constant at +16. Whereas, this constant value constitutes an instantaneous measure of the received signal strength and can be used to derive any signal-strength dependant threshold that is used in the receiver, e.g. the threshold required by symbol synchronisation acquisition (Figure 6) and chip synchronisation status detector (Figure 12).

This signal strength measurement continues to give the required results when the two samples per chip are taken with the correlators as shown in Figure 4. Furthermore, it is also valid under all perfect and imperfect chip synchronisation, However due to the presence of additive noise, it is recommended to average the instantaneous signal strength measure over a number of symbols.

A simple method for implementing an averaging process is to use an add-and-accumulate circuit. The instantaneous signal measure is fed to an adder, which adds this measure to an accumulated sum. The adder output is stored in an accumulator, whose output is fed back to the adder. This process of addition, accumulation and feedback is carried out at the sampling rate. Every 2*N samples, the contents of the accumulator are clocked to a register and the content of the accumulator is cleared. As a result, the register will hold a measure of the average signal strength taken over N symbols. Figure 14 shows the structure of the signal strength measurement unit.

Figure 15 gives a plot of the instantaneous signal value obtained from the summation of all outputs from the bank of correlators. This was generated taking two samples per chip and under perfect sampling scenario.

IE010030 Both symbol and chip synchronisation acquisition units employ a threshold in. order to derive their respective outputs. This threshold is dependent on the signal strength and hence can be derived from the SSM unit of Figure 14, whose output is required to be scaled appropriately in order for the symbol and chip synchronisation acquisition units to operate correctly. Figure 16 shows how the three acquisition elements may coexist in the final synchronisation architecture. The two scaling factors shown in the diagram may not be equal and depend on the communication mode of operation.

Once the acquisition phase is completed, the receiver then switches to data receiving mode. During this phase, the receiver must remain in synchronisation in order for optimum data detection to be possible.

The exact symbol timing epoch having been determined from the symbol acquisition phase of the transmission, a counter mechanism is then used to periodically activate the data decision circuit and hence produce received estimates of the transmitted data. Such a counter mechanism gives a symbol synchronisation condition once every 32 samples (one symbol period). In fact the counter, which counts upto-32 sampling clock pulses of Figure 8, constitutes the counter mechanism for this purpose. Once initialised and symbol synchronisation is declared, then one complete symbol can be assumed to be resident in the bank of correlators whenever the counter reaches the all-zero state.

Symbol synchronisation loss detection, however, is still required to declare such an event when it occurs. One way to implement such a detector is shown in Figure 17.

The bank of correlators outputs are fed into a selector circuit, which uses the detector output as the address of the correlator number to process. The selected correlator output is then thresholded to determine if it has fallen below a pre-defined level, denoted by V.

The threshold circuitry produces a +1 if the input is above the threshold V, otherwise 0 is produced; that is IE010030 if ip > v 0 otherwise The threshold circuitry output is applied to an add-and-accumulate circuit, which will count the number of times the detected correlator output is above the threshold V. On the application of a start monitoring instruction, a counter counts up to K at the symbol rate.

On the detection of the all-zero state, the content of the accumulator is examined. If the value contained in the accumulator is below a pre-specified value, D, then symbol synchronisation loss state is declared. Hence this detector design will give a symbol synchronisation loss declaration when the selected correlator output has fallen D out of K times below the threshold, V.

The chip synchronisation acquisition circuitry of Figure 16 can also be used for chip synchronisation maintenance, where in the acquisition phase, the received signal is assumed to be resulting from the periodic transmission of one pre-specified symbol. In the case of synchronisation maintenance, the received signal will be due to the random transmission of symbols. This added randomness will affect the way the synchronisation tracker is implemented for different communication modes of operation.

During the data-receiving mode, the signal strength estimate will vary in the presence of different symbols in the received signal. Whether this is the case or not can very well depend on the communication mode the system is operating in. However, this is not a problem. A simple protocol solution can be implemented which will over come this problem. In such a solution the obtained signal strength measurement from the synchronisation acquisition mode is assumed to be also valid during the data receiving mode and hence, no further signal strength measurement is considered in the later mode. The averaging of the signal strength measurement during the transmission of random data will be further investigated in the future. In developing an appropriate averaging technique, the receiver can be made more adaptive to instantaneous signal strength variation during the transmission of random data. ΪΕ010030 In the Mode IR(1): Half-Rate mode, the upper and lower codebooks are identical and are constructed from the Supergold codes by selecting the first 8 codes from the original 16hy-16 codebook. The target 16-by-16 codebook, CI, is then constructed from the selected 8 codes and their complement giving a total of 16. CI is then used in the upper and lower branches of the transceiver as shown in Figure 18. It will be assumed that the receiver is AC coupled.

Since only half of the original codebook is used, this scheme differs from that of Figure 16 in the following: At the transmitter, only half of the original codebook is used. The other half is totally ignored.

At the receiver, only half of the correlators are need.

The above means that half of the structure of Figure 16 is now missing. In particular, Sum(3) and Sum(4) are no longer available and can be considered to be zero in the context of Figure 16.

Since effectively, the same waveforms are obtained from the upper and lower banks of 8correlators, two options for connecting the synchronisation scheme emerge.

The first is to apply Sum(l) and Sum(2) to the synchronisation unit of Figurel6 and zeroing the inputs Sum(3) and Sum(4). Hence this option uses, say, the Rx upper branch for the purpose of synchronisation, and this is shown in Figure 19.

The second option is to sum the corresponding Sum(l) and Sum(2) from the Rx upper and lower correlator banks and then feed then into the synchronisation unit, in a similar manner to that of the first option.

During the synchronisation acquisition phase, one symbol, which is known to both the transmitter and receiver, is transmitted periodically.

IE010030 Figure 20 shows the obtained correlation waveforms due to the periodic transmission of code SO. It is clear from the figure that the waveforms possess the required properties, shown in Figure 5, which are needed for symbol synchronisation acquisition. The symbol synchronisation section of the synchronisation acquisition module of Figure 16, will therefore still be applicable here.

Figure 21 shows the obtained chip synchronisation results due to the periodic transmission of code SO and for the three possible synchronisation conditions. The threshold in Figure 12 was set to +2. This threshold is adequate for the noiseless case. However, it will have to be set at a higher level when additive noise is considered.

The above results clearly show that the signaling structure of this mode, has no detrimental effect on the chip synchronisation section of the synchronisation acquisition module of Figure 16, and is therefore still applicable here.

Figure 22 shows the obtained SSM results due to the periodic transmission of code SO and for the three possible synchronisation conditions. Here, the obtained estimate is not continuously constant. However, the summation of any 16 samples and subsequent division by 8 will always give 16. This is true for any of the three synchronisation conditions.

When compared with the instantaneous measurement of Figurel5, it is clear that the above waveforms appear to have suffered a 50% loss of signal. This can be attributed to the fact that only half of the original codebook is used as discussed in section 0.

Figure 23 shows the obtained chip synchronisation results due to the random transmission of all the codes and for the three possible synchronisation conditions. The threshold of Figure 12 was set to +8.

The above show that randomising the transmitted symbols combined with raising the threshold of Figure 12 to +8, allows the chip synchronisation section of the synchronisation IE010030 acquisition module of Figure 16 to be still applicable during the data section of transmission.

Figure 24 shows the obtained SSM results due to the random transmission of all the codes and for the perfect synchronisation conditions. Here, the obtained estimate is not continuously constant as in the ideal case of Figure 15. Furthermore, it appears that there is not any simple and straightforward procedure for extracting the estimate of the signal strength. This suggests that SSM should be carried out during the synchronisation acquisition phase and the estimate obtained is used during the data phase of the packet.

In the Mode IR(2) : Half-Rate mode, the upper and lower codebooks are not identical. The target codebooks for the upper and lower branches of the system, CI and CQ, respectively, are constructed using exactly the same procedure for mode IR( 1), with CQ being constructed from the lower half of the original Supergold codebook. See Figure 25.

Again, note the transmitter sends out the unipolar versions of CI and CQ; the transmitted code members from CI and CQ are effectively algebraically added during transmission through the optical channel. The correlator’s coefficients in the Rx are all bipolar. It will be assumed that the Rx is AC coupled.

Due to the structure of this mode, both the upper and lower banks of 8-correlators at the receiver will experience codes from the upper and lower codebooks in the transmitter.

Since CI and CQ are different, the corresponding outputs of the two banks of correlators will also be different, two options for connecting the synchronisation scheme emerge.

The first is to use only the upper bank of correlators for synchronisation in an identical manner to that of Figure 18. The second option is to apply a second synchronisation unit (Figure 16) to the outputs of the lower bank of correlators and thus obtain another set of synchronisation flags. In this case, the synchronisation information from the upper and lower synchronisation units will have to be combined together by OR-ing corresponding outputs from the upper and lower synchronisation units. While the first approach offers less complexity, the second method is expected to give an increase in the synchronisation update rate and hence reliability.

IE010030 Ideally, the corresponding first codes from CI and CQ would be transmitted periodically during the acquisition phase of the transmission. However, and due to the structure of the received signal and the two correlator banks, the output of the bank of correlators used for symbol synchronisation no longer maintain the same profile as that shown in Figure 20. Figure 26 shows the correlation waveforms obtained from the 1st group of correlators in response to the periodic transmission of the corresponding first codes from CI and CQ, simultaneously.

It is evident from these waveforms that the circuit of Figure 16 will fail to achieve the required initial symbol synchronisation, without some modification.

Two solutions to this problem are possible. The first approach is a protocol solution and that is to constrain the periodically transmitted symbol to one code from CI. No code from CQ will be transmitted during this phase of the transmission. As a result, this will effectively produce the same correlation in the receiver as those obtain for IR(1), and hence the same synchronisation procedure will be applicable here too.

The second approach is to transmit the corresponding codes from CI and CQ, but in this case, the outputs of the 1st and 2nd correlators are added together to give an impulsive clock, which is used to clock the thresholding circuit. The waveform upon which the synchronisation is made, is derived by subtracting the output of the 3rd correlator from the output of the 1st correlator. Figure 27 shows the correlation waveforms obtained.

When waveform 1 is active, the threshold circuit Figure 16 produces a ‘1 ’ if waveform 2 is above a pre-specified threshold or ‘0’ if below the threshold. The correct symbol timing is derived by counting the appropriate number of samples forward (or backward) so as to align the periodically received symbol within the delay line of the corresponding correlator.

While the first solution complements the synchronisation schemes for the previous modes, the second solution reduces the complexity of the synchronisation protocol.

IE010030 21 The chip synchronisation is not affected by the use of either approach given above. The value for the threshold in Figure 12 can be set to 2 or higher.

SSM can be obtained by the summation of the two threshold estimates obtained from the upper and lower synchronisers, see Figure 28. This solution is also chip-sampling independent.

Figures 29 and Figure 30 show the obtained chip synchronisation results due to the random transmission of all the codes and for the three possible synchronisation conditions. The threshold in Figure 12 was set to +8. Signal strength measurement in this case is the same as described above for mode IR(1).

Mode IR(3): Half-Rate (Differential) In the Mode IR(3): Half-Rate (Differential) mode, the upper and lower codebooks are not identical. The target bipolar codebook for the upper branch of the system, CI, is constructed using exactly the same procedure for mode IR(1). The target bipolar codebook for the lower branch of the system, CQ, is derived from the lower half of the original Supergold codes. See Figure 31.

Again, note the transmitter sends out the unipolar versions of CI and CQ; the transmitted code members from CI and CQ are effectively algebraically added during transmission through the optical channel. The correlator’s coefficients in the Rx are all bipolar. It will be assumed that the receiver is AC coupled.

This mode is very much similar to IR(2) in the sense that both the upper and lower banks of 8-correlators at the receiver will experience codes from the upper and lower codebooks of the transmitter. This is again due to the structure of the signaling of this mode. Hence, the same two solutions discussed for IR(2) will also be applicable here.

Figure 32 shows the correlation waveforms obtained for the purpose of symbol synchronisation from the periodic transmission of the corresponding first codes from CI and CQ.

IE010030 It is evident from these waveforms that the circuit of Figure 16 will perform correctly to achieve the required initial symbol synchronisation. The outputs of the Oth and 2nd correlators are added together to give an impulsive clock, which is used to trigger the thresholding circuit in Figure 16. The Oth and 2nd correlators outputs are then compared to derive the required symbol synchronisation.

With a threshold of+8, the chip synchronisation detector of Figure 12 will work correctly. Lowering the threshold to +4, leaves the operation of the early and late flags intact under imperfect chip synchronisation. However, with the later threshold value , the early and late flags alternately pulse, when the chip synchronisation is perfect; and their average alternating pulsing averages to zero.

SSM measurements for this mode is similar to that of IR(1). Figure 33 shows the obtained SSM results due to the periodic transmission of code SO and under perfect chip synchronisation conditions. Here, the obtained estimate is not continuously constant. However, the average taken over any successive 4 samples and subsequent scaling by a constant can always be made to give 16. This is true for any of the three chip synchronisation conditions.

Figures 34 and 35 show the obtained chip synchronisation results due to the random transmission of all the codes and for the three possible synchronisation conditions. The threshold in Figure 12 was set to +4. SSM will be identical to that described for mode IRQ).

In the Mode IR(4): Full-Rate mode, the target upper and lower codebooks are not identical and they are identical to the target codebooks of mode IRQ) See Figure 36. Again, the transmitter sends out the unipolar versions of CI and CQ; the transmitted code members from CI and CQ are effectively algebraically added during transmission through the optical channel. The correlator’s coefficients in the receiver are all bipolar. It will be assumed that the receiver is AC coupled.

IE010030 Due to the identical signaling structure of this mode with that of IR(2), the same synchronisation methods, which are applicable to IR(2), will equally be valid for this mode as well.

Unlike optical systems, the RF platform naturally makes full use of the bipolar code signaling. Consequently, the Supergold codebook of Figure 1 and their relevant properties, which are described above, are directly applicable to the RF implementations. Since the synchronisation module of Figure 16 was developed using the relevant bipolar properties of the Supergold codes, it can be stated that the synchronisation module of Figure 16 constitutes the synchronisation module for the RF platform.

It will be understood that the current invention relates both to the specific architectures described as embodiments of the underlying invention namely the use of communication codes for synchronisation. This use has the technical effect of reducing component count, complexity and cost. Additionally the manner of use of the signal downstream of the correlators to improve signal quality and therefore system robustness is also an important feature of the invention. Both of the above being read in conjunction with benefits of using Supergold structured codes for this purpose.

It will also be understood that the method and apparatus described may be used in any suitable communication medium It will be noted that the method and apparatus is not limited to implementation with the packet based IEEE 802.11 standard but may equally be implented for synchronous transmission with embedded synchronisation symbols.

It will of course be understood that the present invention is not limited to the specific details described herein, which are given by way of example only and that various modifications and alterations are possible within the scope of the invention, as defined in the appended claims.

Claims (5)

CLAIMS:

1. An apparatus for data communication in a Wireless local area network (WLAN) using a plurality of correlators and M-ary Code Keying with an associated chip period characterised in that the communication utilises a Supergold signature sequence for simultaneously generating any or all of :a periodic signal for acquiring symbol synchronisation; a difference squarewave signal for acquiring and maintaining chip synchronisation; and a sum signal for determining received signal strength and setting threshold levels.

2. An apparatus as claimed in claim 1 in which the sum of the responses of all correlators to the repetitive periodic transmission of one code is a constant.

3. An apparatus as claimed in claim 1 or claim 2 including periodic transmission means for producing a zero value sidelobe of a summed correlation and optionally in which the difference signal is a periodic bipolar squarewave signal, the signal optionally having a period of twice the chip period.

4. An apparatus as claimed in any preceding claim including means for windowthresholding a chip synchronisation waveform or optionally in which:correlator summation is initiated in response to the periodic transmission; a correlator summation is directed to a thresholding circuit; a correlator summation is directed to a comparison logic for level determination; IE010030 an early-late detector circuit is connected at the correlator outputs;

5. An apparatus substantially in accordance with any of the embodiments as herein 5 described with reference to and as shown in the accompanying drawings.