IE940854A1 - Data processor with branch prediction and method of¹operation - Google Patents

Data processor with branch prediction and method of¹operation

Info

Publication number
IE940854A1
IE940854A1 IE940854A IE940854A IE940854A1 IE 940854 A1 IE940854 A1 IE 940854A1 IE 940854 A IE940854 A IE 940854A IE 940854 A IE940854 A IE 940854A IE 940854 A1 IE940854 A1 IE 940854A1
Authority
IE
Ireland
Prior art keywords
branch
address
instruction
fetch
circuitry
Prior art date
Application number
IE940854A
Other languages
English (en)
Inventor
Paul C Rossbach
David S Levitan
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of IE940854A1 publication Critical patent/IE940854A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3846—Speculative instruction execution using static prediction, e.g. branch taken strategy

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
IE940854A 1993-11-02 1994-11-01 Data processor with branch prediction and method of¹operation IE940854A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14438893A 1993-11-02 1993-11-02

Publications (1)

Publication Number Publication Date
IE940854A1 true IE940854A1 (en) 1995-05-03

Family

ID=22508362

Family Applications (1)

Application Number Title Priority Date Filing Date
IE940854A IE940854A1 (en) 1993-11-02 1994-11-01 Data processor with branch prediction and method of¹operation

Country Status (4)

Country Link
CN (1) CN1117618A (fr)
GB (1) GB2283595B (fr)
IE (1) IE940854A1 (fr)
TW (1) TW261676B (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1306394C (zh) * 1994-12-02 2007-03-21 现代电子美国公司 有限游程转移预测的方法
US5752014A (en) * 1996-04-29 1998-05-12 International Business Machines Corporation Automatic selection of branch prediction methodology for subsequent branch instruction based on outcome of previous branch prediction
SE520343C2 (sv) * 1997-02-12 2003-07-01 Ericsson Telefon Ab L M Förfarande, system och dator för grenprediktion
US6341348B1 (en) 1998-12-03 2002-01-22 Sun Microsystems, Inc. Software branch prediction filtering for a microprocessor
US6427206B1 (en) * 1999-05-03 2002-07-30 Intel Corporation Optimized branch predictions for strongly predicted compiler branches
US7421572B1 (en) * 1999-09-01 2008-09-02 Intel Corporation Branch instruction for processor with branching dependent on a specified bit in a register
US6859875B1 (en) * 2000-06-12 2005-02-22 Freescale Semiconductor, Inc. Processor having selective branch prediction
US11163577B2 (en) 2018-11-26 2021-11-02 International Business Machines Corporation Selectively supporting static branch prediction settings only in association with processor-designated types of instructions

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4477872A (en) * 1982-01-15 1984-10-16 International Business Machines Corporation Decode history table for conditional branch instructions
US4755966A (en) * 1985-06-28 1988-07-05 Hewlett-Packard Company Bidirectional branch prediction and optimization
US5265213A (en) * 1990-12-10 1993-11-23 Intel Corporation Pipeline system for executing predicted branch target instruction in a cycle concurrently with the execution of branch instruction

Also Published As

Publication number Publication date
CN1117618A (zh) 1996-02-28
GB2283595B (en) 1998-06-03
GB9420379D0 (en) 1994-11-23
GB2283595A (en) 1995-05-10
TW261676B (fr) 1995-11-01

Similar Documents

Publication Publication Date Title
US5805877A (en) Data processor with branch target address cache and method of operation
US5553255A (en) Data processor with programmable levels of speculative instruction fetching and method of operation
USRE35794E (en) System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
US5530825A (en) Data processor with branch target address cache and method of operation
US5761723A (en) Data processor with branch prediction and method of operation
US8145890B2 (en) Pipelined microprocessor with fast conditional branch instructions based on static microcode-implemented instruction state
US5628024A (en) Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions
US6609194B1 (en) Apparatus for performing branch target address calculation based on branch type
US6550004B1 (en) Hybrid branch predictor with improved selector table update mechanism
US5072364A (en) Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel
US6526502B1 (en) Apparatus and method for speculatively updating global branch history with branch prediction prior to resolution of branch outcome
US5075844A (en) Paired instruction processor precise exception handling mechanism
US7971044B2 (en) Link stack repair of erroneous speculative update
US6247122B1 (en) Method and apparatus for performing branch prediction combining static and dynamic branch predictors
US11599361B2 (en) Flushing a fetch queue using predecode circuitry and prediction information
US6766442B1 (en) Processor and method that predict condition register-dependent conditional branch instructions utilizing a potentially stale condition register value
EP2084602A1 (fr) Système et procédé pour utiliser un registre historique mondial de travail
US5748976A (en) Mechanism for maintaining data coherency in a branch history instruction cache
IE940854A1 (en) Data processor with branch prediction and method of¹operation
US10963260B2 (en) Branch predictor
US6421774B1 (en) Static branch predictor using opcode of instruction preceding conditional branch
US6871275B1 (en) Microprocessor having a branch predictor using speculative branch registers
EP0666538A2 (fr) Processeur de données avec antémémoire pour adresse de branchement et procédé d'opération
JPH09507321A (ja) 分岐予測および推論的状態変化を用いるパイプライン化マイクロ命令装置および方法

Legal Events

Date Code Title Description
MM9A Patent lapsed through non-payment of renewal fee