IE913838L - A transmission system - Google Patents

Description

This invention relates to a transmission system such as for use in a subscriber unit for a wireless digital telephone system* According to the invention, there is provided a transmission system employing a transmission path comprising an input for applying time multiplexed I and Q samples, in the form of complex samples pairs/symbol, to a demultiplexer; an equalizer coupled to said demultiplexer for receipt therefrom of the demultiplexed I and Q samples; means at the transmitting end of said path for applying a plurality of training signals to said path, said training signals corresponding to undesirable characteristics that might be present in the demultiplexed I and Q samples; and means at the receiving end of said path for comparing the actual inputs applied to said equaliser with each of said training signals to obtain a. set of weighting coefficients.

There follows a description of preferred features of the transmission system and of a subscriber unit for a wireless digital telephone system in which the system is suitable for use« The subscriber unit is adapted to be in wireless connection with a base station. The subscriber unit has a baseband processor which performs a number of functions including the transcoding of incoming and outgoing signals from one type of bit stream to another and the provision of echo cancellation. It also acts as a control microprocessor such as, for example, by informing a synthesizer in the system as to the desired operational 3 frequency to be used. It is, in addition,, coupled to storage means for receiving and storing the various functions performed or received thereby.

The baseband processor is connected to a modem processor to which it is coupled by a direct access means that prevents simultaneous access by both of these processors, but the two processor do communicate with each other, and the modem processor, which acts as the master in the system, m&v access the baseband processor's memory through the direct access means. However, lock-out means are provided whereby, in certain circumstances, control of the baseband processor by the modem processor is prevented.

The modem processor sends its signals, at a predetermined sampling rate, through a frequency translated complex signal which is converted to an anlog signal. This analog signal is subjected to deglitching by means of a blanking process. The deglitched signal is then upconverted and filtered to form an IF signal which is thereafter amplified. The frequency of the amplified IF signal is added to a frequency generated by the aforesaid synthesizer and the resultant RF signal is amplified and passed to an antenna. 4 The subscriber unit utilises continuously repetative frames in which it transmits during one portion of each frame and receives during another portion thereof, these portions being designated "slots". On the basis of 5 certain signals received frost the base station, the baseband processor produces initiating signals which determine whether the subscriber unit will be in the transmit mode or the receive mode,.

In intervals between actuation of the system, a 10 training mode is used wherein a known signal from the modem processor is compared with a, leoped-baek signal to produce correction constants to compensate for undesirable variations in the IF signal due to variations in temperature, component values, etc, are obtained. These 15 correction constants are stored for use in correcting actual received signals.

During the demodulation, the modulated digital signals are fed to the modem processor in the form of time multiplexed I and Q samples and are demultiplexed. The 2o demultiplexed I and Q samples are fed to an equalizer and frequency correction circuit for minimization of errors, resulting in the production of frequency correction signals which are used to correct any errors in the timing of the system and in the output of the synthesizer.

In the drawings, Figure 1 is a diagramatic view showing a Subscriber Unit embodying the present invention.

Figure 2 is a block diagram of the modulator portion of the modem processor shown in Figure i.

Figure 3 is a block diagram of the DPSX conversion unit shown In Figure 2.

Figure 4 illustrates the structure and function of the 5 FIR filter shown in Figure 2.

Figure 5 is a block diagram of the interpolator shewn in Figure 1- Figure 6 is a block diagram of the synthesiser shown in Figure 1- Figure 7 is a modified form of the input portion of the system shown in Figure l.

Figure 8 is a block diagram of the demodulator portion of the modem processor shown in Figure 1.

Figure 9 is a block diagram of the course frequency 15 control module shown in Figure 8.

Figure 10 is a block diagram of the AFC and symbol timing module shown in Figure 8.

Glossary of acronyms and words used in the Specification ACRONYM DEFINITION 2o A/D Analog-to-Digital Converter ADJ Adjustment Input AFC Automatic Frequency Control AGC Automatic Gain Control BLANKING Control means for causing a signal to be held at a predetermined amplitude level during actuation of the control ®eans CODEC Combined Coder and Decoder CPE Customer Provided Equipment (telephone instrument) 3o D/A Digital~to-Analog Converter DMA Direct Memory Access DPSK Differential Phase Shift Keying Modulation DS Data Select EEPROM EPROH FIFO FIR 5 GLITCH HOLD 1 IF Kbps 10 nS PAL PCM PROM PSK 15 Q ram HELP RF r/w 20 S/H SLIC STROBE uart VCXO 25 XF Electrically Erasable Programmable Read Only Memory Erasable Programmable Read! Only Memory First-in First-Out Memory Finite Impulse Response Undersired Transient Signal Idle Mode la-Phase Intermediate Frequency Kilobits per second Nanosecond Programmable Array Logic Pulse Cod® Modulation Programmable Head Only Memory Phase Shift Keying Modulation Quadrature Random Access Memory Residual .Excited Linear Prediction Radio Frequency Read/Write Sample and Hold Subscriber Loop Interface Circuit Sampling Signal Universal Asynchronous Receiver Transmitter Voltage Controlled Crystal Oscillator External Flag Output Used for Signalling Other Processors This invention relates to a transmission system such as for use In communications systems for the wireless transmission of multiple information signals utilizing 30 digital time division circuits between a base station and one or more subscriber stations „ and it particularly relates to the structure and functioning of such a system.

Referring now in greater detail to the drawings wherein similar reference characters rafer to similar parts, there 35 is shown in Figure 1 a connector 10 for 7 connection to the customer-provided equipment (CPE). h line pair 12 leads from the connector 10 to a SLIC 14 and is also connectable to a ringer circuit 16 through a relay 18. The SLIC 14 is a standard chip for providing various 5 functions such as battery voltage, overvoltage protection, ringing, signalling detection, as from a rotary dial, the handset status,, line testing,, etc.- It also contains the hybrid which separates a plurality of voices into ingoing and outgoing signals. The SLIC 14 is coupled to a codec 20 10 having ingoing and outgoing lines to and from a baseband processor 22 whereby in the ingoing direction it converts analog voice signals to digital signals, i.e., 64 kbps u-lav PCM, while in the outgoing direction, it converts the digital signals to analog voice signals. It may sometimes 15 be desirable to bypass the codec so that the SLIC 14 is directly coupled to the baseband processor 22. There is an alternative access to the baseband processor through a connector 24 and a UAHT 26, which provides a direct digital connection to the baseband processor, thereby bypassing the 20 SLIC and codec. This direct access connection serves two purposes: (1) to pass only digital signals, when so desired, thereby bypassing all analog connections, and (2) to allow direct access to the processors and memories for easy maintenance and test purposes.

The baseband processor 22 has several functions, one q£ which is to convert the 64 kbps PCM signal to 14.57... kbps by means of a transcoding function, such as, for example, provided by residual excited linear prediction (HELP). It also provides echo cancellation, and, in 30 addition, acts like a control microprocessor, as, for example, by informing the synthesizer used in the system as to the desired operational frequency. The baseband processor 22 is coupled to a bootstrap memory chip 28 as well as to a serial EEPROM 30, which is an electrically 35 erasable, non-volatile Memory where selected bits may be electrically erased without erasing other bits stored therein. This EEPROH 30 is used to store both the subscriber identification number and the network i identification number (the base station with which it is used). In addition, thee baseband processor 22 is coupled to a full speed HAH 32 in which it stores the signals received therein. The RAH 32 also includes a "cache® 5 means,, and, in addition,, is used as a random access memory for HELP conversion,, echo cancellation and other control functions. The baseband processor 22 is also coupled to a half-speed EPROH 34 and a full-speed PROM 36 which store the RELP and echo cancellation functions as well as various 10 other functions such as the control function. The baseband processor 22 is, in addition, coupled via direct memory access (DMA) 38 to a modem processor 40.

The DMA 38 prevents the occurrence of simultaneous access of RAM 32 by both the baseband and modem processors. 15 The DMA interface is used to transfer voice and control data between the baseband and modem processors. The modem processor 4 0 acts as the master and controls the baseband processor 22 via hold lines (not shown)- The modem processor 4 0 has the capability to access the 20 baseband processor 22, halt its processing and cause the control lines, address and the data buses to assume the high impeder.ee state of a three-state output. This permits the modem processor 40 to access the baseband processor's DMA memory through the DMA Interface and read or write to 25 it.

This is accomplished by the modem processor 40 asserting its IF bit, which is gated to the baseband processor' s Hold input. When the baseband processor receives this command, it will finish executing the current 30 instruction, stop its processing, cause its control data and address buses to assume the high impedence state of a three-state output and then issue a Hold Acknowledge signal back to the modem processor. Immediately after the nodes processor issues the Hold command, it will continue on with 35 other tasks while waiting for the baseband processor to send the Hold Acknowledge signal. Once the modem processor receives the Hold Acknowledge signal, it will take control of the baseband processor's control, data, and address buses and then read or write to the DMA RAH 32. After the modem processor completes accessing the DMA RAH, it will take away the Hold input on the baseband processor, which Mill then resume processing where it left off. The 5 baseband processor also has the capability to lock out the roods® processor by setting its own X? bit high. The bit is gated with the Hold from the modem processor and can override the Hold line at any point before the baseband processor goes into the Hold state. The modem processor 10 uses 10 bits of the address bus and all 16 bits of the data bus. It also uses three control lines- strobe, R/W, and DS.

Either the baseband processor 22 or the modem processor 40, acting in either direction, may obtain 15 signals from the RAH 32 in accordance with the signals described above. The two processors communicate with each other by way of a portion of RAH 32 that is set aside to be used as a cache. The modem processor 40 is also coupled to a full speed PROM 4 4 which contains the program for this 20 processor.

The modem processor 40, in its modulation mode, sends its signals via a FIFO 46 to an interpolator 48, these signals being at a sampling rata of 320 kHz. The interpolator 48 effectively increases this sampling rate by 25 5 to convert it to 1600 kilosamples/second (1.6 megasamples/second). The interpolator„ in conjunction with the crystal filter (hereinafter described)t which acts as an integrator, effectively approximates a 5 tap FIR filter. This usage of digital and analog hardware to implement an 30 FIR filter differs from the classic all digital hardware FIR implementation. The interpolator output is fed into a PAL 50.

The PAL is configured as a type of mixer into wlv :h is fad a 400 kHz square wave, as indicated at 50, wfcr ,-h 35 comes from a timing generator 51, as well as the 16 30 kilosamples/second signal. The 1600 kilosamples/second signal represents a l6-kilosymbol/second PSK signal with a zero carrier and a desired 20 kHz bandwidth. In effect. 18 the PAL can be considered as a frequency translator- The PAL circuit which when, configured to perform a 2*s complement function controlled by a 400 kHz square wave effectively performs a time multiplexed quadrature mixing 5 and effectively translates the 20 kHz wide baseband signal up to 400 kHz.

The output from the PAL 50 is a time multiplexed, frequency translated complex signal which is passed to the D/A converter 52 which converts the digital signal into an 10 analog signal. The output from the D/A converter 52 is fed to a mixer 54 into which is also fed a deglitching/blanking pulse 56 from a blanking generation module 58.. Glitch energy is a major contribution to noise in a sampled data system.. Glitch energy occurs during transitions from one 15 input word to another. In a D/A converter, each incoming bit, depending upon its state, may cause a change in output analog level. Such changes resulting from the various bits usually do not occur simultaneously and therefore cause glitches. Classical solutions to this problem are the use 20 of a sample and hold following the D/A or the use of a deglitching D/A. Both of these alternatives, however,, are unduly expensive. "Blanking" returns the output of the .mixer to an intermediate reference level during the transition periods, typically about 35 nS before and 130 nS 25 after the digital switching times, thereby suppressing large glitch spikes that occur on the D/A output. Although blanking creates harmonics away from the center frequency of interest, the use of relatively tight IF filtering substantially removes' these harmonics. This blanking 30 method also reduces the sampling rate content in the output.

The output from mixer 54, indicated at 60, is fed to a mixer 62 in an upconverter, generally designated 64. The mixer 62 has a 20 KHz input indicated at 65, which is 35 common with a 20 MHz line 66. The output of mixer 62 is the sum of 20 MHz from input 65 and the 400 kHz signal received from mixer 54, with a resultant output of 20.4 MKz. This output is fed into a crystal filter SB which 4 4 * t passes only this sum, constituting the IF signal,, to an amplifier 70.

A synthesizer is shown at 72. within this synthesizer 72 is a synthesizer module which provides an S output LOI. Also within the synthesizer nodule, a second circuit derives a, second output L02 wherein the output of L02 tracks the output of LOI at a frequency of 5 MHz below the frequency of LOl« The synthesiser wses as a reference the 80 MHz VCXO. The output LOI is fed through line 74 to 10 a mixer 76 which also receives the IF output fro® amplifier 70- Since the IF signal has a value of 20.4 MHz, if, for example, a frequency of 455-5 MHz is desired at the output of mixer 76, the synthesiser is operated to generate a frequency of 435.i MHz, which when added to the 20.4 MHz, 15 gives the desired frequency of 455.5 MHz. This output is then amplified by a variable gain amplifier 30- The baseband processor 22, on the basis of decoding certain signals from the base station, sends a gain control signal on line 81, through a D/A converter 82, to the variable 20 gain amplifier 80» variable gain amplifier 80 has limited bandwidth and, therefore, does not pass the undesired difference frequency also produced by the mixer 76. The output of amplifier 80 is passed through line 83 to a power amplifier 84, which accomplishes the final amplification 25 before the RP signal passes through a relay £5 to an antenna 88.

The unit employs a system whereby a frame repeats every 45 milliseconds. In this system, the unit transmits during a portion of the second half of each frame and 30 receives during a portion of the first half of the frame. One configuration might be where both portions of the half are of equal length (although they may not necessarily be equal). Another configuration (16~ary) might be where four equal length portions are available to the subscriber 35 during an entire frame. Each of the four portions .may be termed a slot- Each slot contains, as part of its initial data, a unique word which is used by the unit to establish timing for reception of the remaining data in the slot. 1 f> JL £> The first slot of the four is preceded by an AM hole vhicfe is used to determine a slot arbitrarily designated by the base station as th© first slot. The AM hole and the unique word are part of the incoming signal from the base station.

The duration of th® AM hoi® is used to determine whether a particular RF channel is a control channel or a voice channel- A data signal is derived from the average magnitude of the signal represented at 116. A threshold proportional 10 to said average magnitude is compared to unaveraged magnitudes. If the threshold is not exceeded by said unaveraged magnitude for a predetermined period of time, it is assumed that an AH hole has been detected™ The modem processor 40 stores the time at which the AH hole was 15 determined to occur in RAM 32 - The baseband processor, on the basis of (a) modulation mode (4-ary or 16-ary), (b) the time at which an Ml hole occurred, as stored in RAM 32, and (c) the time at which a unique word was receivedf as separately determined by the baseband processor, produces 20 initiating signals which indicate when the unit should be in a transmit mode or a receive mode. Such initiating signals are coupled via line 90 to frame timing module 91.

The frame timing module 91 converts the initiating signals into two series of pulses. One series of pulses is 25 connected via line 92 to enable power amplifier 84 and to actuate relay 86 so as to connect the output of amplifier 84 to antenna 88. During the period of the pulse on line 92, the unit is designated to be in the transmit mode. When relay 88 is not so actuated, it is configured to 30 connect antenna 88 to the input of preamplifier 94.

The other series of pulses from frame timing module 91 are connected via line 93 to a preamplifier 94 to enable this preamplifier. The unit is designated to be in the receive mode during this series of pulses. The 35 preamplifier 94 passes received signals to a mixer 96, which also receives output L02 from the synthesizer 72 through line 98. The output of mixer 96 is fed t© a crystal filter 100, the output of which, in turn, is fed to X fti an IF amplifier 102.

The modem processor 40 passes via line 89, the aforementioned data signal, which is derived from the average magnitude of the signal represented at lie, to a 5 D/A converter 104 which produces an analog AGC voltage signal which passes through line 106 to amplifier 102, thereby indicating to this amplifier how much gain is required in order to compensate so that th© IF signal is always at the same amplitude. This amplifier also receives 10 the output from crystal filter 100. The output from amplifier 102 passes to a mixer 108 into which is also applied an input of 20 MHz from line 109 to produce a resultant 400 kHz signal. This 400 kHz signal is then passed to an A/D module which consists of sample and hold 15 circuits 110, and A/D converter 112 and a FIFO 114.

The output from the A/D conversion module is 64 kilosamples/second and this output is fed through line 116 into the modem processor 40. The modem processor 40 demodulates this signal and passes the demodulated data 20 into the cache portion of RAM 32 which is accessed by the baseband processor 2 2 in which the RELP conversion takes place. The resultant output has 64 kbps PCM on a continuous serial basis. This output is fed to the codec, which converts it to an analog signal that is then fed to 25 the SLIC which, in turn, feeds it to the -.elephone instrument; or, alternatively, the 16 kbps from the cache can be decoded into a digital signal which is fed to the UART 26 - When used in the training mode, a loopback is 30 provided at 118 between two relays 120 and 122. This loopback, which is at the IF side rather than at the RF side, decreases the number of elements required. The training mode is that in which a known signal is sent out by the modem processor through the remainder of the 35 transmitter elements set to IF amplifier 70 „ Because relays 120 and 122 are operated, the output of the amplifier 70 is connected to the input of crystal filter 100.

Additionally, an output of the baseband processor 22, indicated line 90, passes to frame timing 31 and causes a pulse on line 93 to totally disable amplifier 94 during the training node. Furthermore, during the training mode, 5 frame timing 91 produces another pulse on line @2 which totally disables amplifier 84. The known signal generated by the modulator is compared with the actual signal returned to the demodulator« A subsidiary program is then set up to compensate for variations due to various factors 10 such as variations in temperature, component values, etc.. The correction constants are stored in the RAM 32. The modern applies these stored corrections to the received signals. The training mode takes place in intervals between actuation of the system.

The synthesiser module 72 contains an, 80 MHz oscillator (VCXO) derived from the received signal. The 80 MHz signal generated by the oscillator goes through line 124 to a divide-by-4 circuit 126, the output of which goes to mixers 62 and 108. This output also goes to the two 20 processors to provide clock pulses (square waves). in addition,, it goes through line 124 to a divide-by-5 circuit 130 and then to timing module 51. The modem processor determines any difference in frequency between the center frequency of the input signal and a submultiple of the 25 clock' frequency.

Any resulting difference is applied by th© modem processor, via line 132, to a D/A converter 134. The output of the D/A converter 134 is applied via line 136 and ADJ input 138 to the VCXO (hereinafter described) in such a 30 manner as to change its frequency in the direction required to minimize the preceding resulting difference. A lock loss detector signal is applied through line 140 to the baseband processor 22 to indicate when there is a loss of synchronisation in the synthesiser.

The modem processor 40, as shown in Figure 2, comprises a DPSK converter 150 into which data is fed through line 152. The data is then fed at 16 kHz symbol/second rate? to a FIR filter 154. 'The output from FIR filter 154,, indicated at 156, is asynchronous data comprising 10 complex samples/symbol, time-multiplexed IQ pairs. This output is fed to the FIFO 46, described above,, where asynchronous to synchronous conversion takes place.

The output from the FIFO 46,, in the form of ISO,000 pairs of data words/second,, is fed into the interpolator 48, described above, which demultiplexes the IQ pairs, and remultiplexes the IQ samples at 1.6 HHs rate.

In a 16-ary modulation schesae , the binary input 10 sequence is divided up into 4-bit symbols. In 16-ary PSK, the 4-bit symbols determine the phase of the carrier during the given symbol period. The task of converting the binary input to the PSK waveform is performed by the modulator.

Figure 3 shows how a sequence of samples (S), shown IS at 160, is transformed into a sequence of In-Phase (I) and Quadrature (Q) samples in the DPSX converter 150 of the modem processor 40, The symbols are first inverse Gray encoded, as shown at 162. This is done to minimize the number of bit errors that occur due to the most likely 20 incorrect symbol decisions in the demodulator.

The output of the inverse Gray encoder 162 is fed into a phase quantizer 164 which determines the current phase value ©i introduced by the current symbol. This phase value is then fed into the differential encoder 166 25 which computes the absolute phase value ©i'. ©i8 represents the modulo 16 sum of the current phase 0i and the previous phase e-i•. ©i' = (Qx + 0-i') MOD 16 The modulo 16 addition corresponds to the modulo 3SO 30 addition that is performed when adding angles. • The absolute phase ©is is fed into cos and sin lookup tables to compute the I and Q components of the current symbol.

The I and Q samples are fed into the 6-tap Finite Impulse Response (FIR) filter 154 shown more specifically in Figure 4. The function of the FIR filter is to create an oversampled PSS waveform from the I and Q samples. The Q samples are fed into a bank of ten 6-tap FIR filters J* rfSfe * t) j— -v labelled ,s (j » 1 through 10). Similarly., the I !■> £ iff samples are fed into a bank of ten filters labelled »hr_ The outputs of these 20 filters are time division mulitplexed as shown onto a single parallel bus that runs 5 at a sampling rate which is ten times the sampling rate of the X,Q pairs at the input of the filter.

The interpolator 48, shown more specifically in Figure 5, comprises an input 180 and a relay 182 that is connected to the PAL 50 by a line 183, the relay 182 being 10 movable between the input 180 and a line 184. Optionally intertable in the line 183 is a multiplier 185 that may be used to multiply the inputs from the line 183 as well as an optional input 187 that may be applied from the mod,em processor or from any desired auxiliary memory. The relay 15 182 is connected to the PAL 50 by the line 183 ana the line 184 leads from the I memory 186 which has an input 188 from the Q memory 190. A 1.6 KHz input is provided for both the 1/0 and Q/I memories as indicated at 192 and 194 respectively. The interpolator demultiplexes the multiplexed I e Q samples at a 160 kHz rate and then resaiaples and remultiplexes at an 800 kHz rate.

The synthesizer 72,. functionally described above, is illustrated in Figure 6, where there is shown an 80 MHz VCXO module 200 that receives a signal from the ADJ input 25 138. This input controls the exact frequency of the vcxo module. The output from the VCXO Module is connected via line 202 to the synthesizer 204- This synthesizer 204 is capable of synthesizing frequencies between 438.625 and 439.65 MHz in appropriate synchronism with the signals over 30 line 202. The particular frequency is selected by an input signal over line 128 (also shown ir. Figure 1).

The output of the synthesizer 204 if fed, via line 206 and filter 208 to become LOI. The output of synthesizer 204 is also fed, via line 210, to a synchronous 35 translator 212. The output of the VCXO 200 is fed through line 214 to a divide by 16 module 216, the 5 MHz output of which is fed through line 218 to the synchronous translator module 212- The output on line 214 is also connected to a jL i reference output 221.

Modules 212 subtracts the 5 KHz input from line 218 from the frequency on line 210, producing a difference frequency that is fed,, via filter 220, to become LG2. In 5 this manner, the frequencies appearing as L02 vary between 433.625 and 4 34-65 KHz, whereby the frequency of the L02 is always 5 MHz below the frequency of LOI.

Additionally, the output from the synthesiser 204, via line 222, and the output from the synchronous 10 translator 212, via line 224, are combined in a synchronization detector 226 in such manner that if either the frequency on line 206 is not synchronous with the frequency on line 202 or the frequency output of synchronous translator 212 is not synchronous with the 15 combination of the frequency on line 206 and the output frequency of the divide-bv-16 module 216, a loss of synchronization (lock loss) signal is sent on line 140 (also shown in Figure 1).

The particular combination of one synthesizer 204 20 plus the divide-by-16 module 216 and the synchronous translator 212 provides the same function as the two separate synthesizers previously used, but with fewer parts, greater stability, easier tolerances, etc.

Figure 7 illustrates a preferred circuit to test the 25 customer interface. In this respect,, the xnodem processor 22 (shown in Figure 1) digitally generates a 1 kHz sine wave that is passed to the codec 20 (shown in Figure 1) that converts it to an analog sine wave which is, in turn, passed through the hybrid function of the SLIC 14 to line 30 pair 12. A relay K {not shown in Figure 1) is inserted immediately adjacent the connector 10 so that it may disconnect the connector from the circuit. Any reflected signal from the unterminated line pair 12 at the open re]ay K is returned through the hybrid function of the SLIC and 35 is converted to a digital signal by the codec 20. This digital signal is fed to the baseband processor 22 which compares the reflected signal with the originating signal and determines whether any undesired impedences or connections, e.g. grounds, are present on the line pair 12.

Figure 8 illustrates the demodulator portion of the modem processor 40 and shows the 400 kHz output from the mixer 108 (shown in Figure 1) applied to the high precision 5 sample and hold circuit 110, which has an aperture uncertainty of 25 nanoseconds or less,, the output of which is passed to the A/D converter 112. The output of A/D converter 112 is fed through line 116 to the nodes processor (all as shown in Figure 1). The input at line 10 13.6 comprises time multiplexed I and Q samples (which may have some cross-product distortion} in the form of two complex sample pairs/symbol. Said time multiplexed I and Q samples are applied to the demultiplexer 298 where they are demultiplexed. The demultiplexed I and Q samples are 15 applied to an equaliser module 300 whose objectives are to minimize (a) error energy of the received data stream, (b) .modified error energy of the data stream delayed by 0.05 T (T being 1/16000 of a second), (c) modified error energy of the data stream advanced by 0.05 T, (d) energy of the data 20 stream from the adjacent upper channel (desired receive frequency plus 25 kHz) , and (2) energy from the data stream of the adjacent lower channel (desired receive freguency minus 25 kHz).

The equaliser is a complex 28 tap FIR filter wherein 25 the filter weights are determined by minimizing the above five objectives. For this purpose, five training signals are generated by the modulator. These are: (a) a signal at the desired freguency wherein the receiver and transmitter clocks are synchronized, (b) the same signal as (a) but 30 wherein the receiver clock is advanced with respect to the transmitter clock by 0.05T, (c) the same signal as (b) except that it is delayed by 0.05T, (d) the same signal as (a) hut wherein the carrier frequency is increased by 25 kHz,, and ( By comparing the actual inputs during th® presentations of each of the five training signals with $ set of desired outputs, a set of weighting coefficients is obtained, which when implemented in the equalizer, achieve 5 the aforementioned objectives™ These weighting coefficients are stored in the RAM 32,.

The equalised I and Q samples are fed into a module 302 which produces an output which is the arc tangent of the ratio of the equalized Q and 1 samples- This output, IQ shown at 304,. represents the phase of the received signal,, The equalized I and Q samples are also simultaneously fed to a course frequency module 306, shown in greater detail in Figure 9 - The I and Q samples are summed! to produce a lower sideband 308 (as shown in Figure 9), and 15 simultaneously the difference between the 1 and Q samples is formed to produce an upper sideband 310. A magnitude calculation is then performed on both the upper and lower sidebands, as indicated at 312 and 314. The difference operation between the magnitudes takes place at 3lS» This 20 difference indicated at 318, represents a frequency error.

As shown in Figure 8, the output 304 of the arc tangent module 302 is fed to the AFC and symbol time tracking module 320 (which is shown in greater detail in Figure 10). The phase correction value, indicated at 322 25 in Figure 10, is subtracted from the detected phase 304, resulting in the corrected phase indicated at line 324. The corrected phase 324 is fed into a symbol detector 325 which detects the current symbol in terms of the phase value and quantises the phase to the nearest 22.5 degree 30 increment. The quantized phase, indicated at 328, is subtracted from the corrected phase 324 at 330. This results in the phase error signal indicated at 332. This error signal 332 is fed into a second order loop filter, generally indicated at 334, which computes the phase 35 correction value, indicated at line 336, as well as the frequency correction signal, shown at 338. This frequency correction signal is applied to the VCXO through line 132 shown in Figure l.

The error signal 332 is fed through line 340 to a symbol timing tracking module 34 2 which also receives the output from the symbol detection module 326 through line 344. The symbol timing tracking module 342 contains an 5 algorithm which tracks the phase over a number of predetermined symbols,, looking at the starting phase of the first symbol and the phase of the. last symbol,, and then determines the slope. It tries to determine from the phase versus time function where the ;sero crossings that actually 10 occurred and comparing them with where they should have occurred,, a timing adjustment is computed that will correct for the difference. The symbol clock will be adjusted at the beginning of the next slot. The symbol timing tracking module 342 provides an output 34 6 which is applied to the 15 timing module 51 (shown in Figure 1).

The frequency correction signal 3 38 from the AFC and symbol timing module 320 is applied to a weighting module 348 (as shown in Figure 8) where it is weighted. The output 350 from module 348 is fed into a summing module 352 20 where signal 350 is summed with the output 318 of module 306 to provide an output 354 which is applied to the D/A converter 134. The output from D/A converter is shown in Figure 1 as being applied to the synthesiser at 138.

Although the invention, as described above, provides 25 for various separate elements, it is possible to include the functions of many of these elements such as, far example,, the full speed PROM 44,* the FIFO 46,, the interpolator 4 8 and the PAL 50, within a modem processor of sufficiently large capacity. This may also be true of such 30 elements as the frame timing 91, the blanking generation 58, the timing means 51, the divide-by-4, the divide-by-5 and some or all of the synthesizer 72. Furthermore, the baseband processor and the modem processor may also be combined in a simple unit which may also include the codec 35 and the UART.

Attention is hereby drawn to the applicants copending Patent Specifications:- Patent Specification Ho. Patent Specification Ho. U.K. Patent Specification Mo. 8717218), Patent Specification No.

Patent Specification Ho. U»K. Patent Specification Mo» 8717221), U.K. Patent Specification Ho. 10 8717223), U.K. Patent Specification Ho. 8717224) and U.K. Patent Specification Ho. 8717225). 3C*S/rf > QaoiW i 30^/36- 2194404 (Application Ho. 2C4 2194403 (Application Ho. 2198916 (Application No. 2199214 (Application Ho. 2199206 (Application No.

Claims (9)

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1. A transmission system employing a transmission path comprising an input for applying time multiplexed I and Q samples, in the form of complex samples pairs/symbol, to a demultiplexer; an equalizer coupled to said demultiplexer for receipt therefrom of the demultiplexed I and Q samples; means at the transmitting end of said path for applying a plurality of training signals to said path, said training signals corresponding to undesirable characteristics that might be present in the demultiplexed I and Q samples; and means at the receiving end of said path for comparing the actual inputs applied to said equalizer with each of said training signals to obtain a set of weighting coefficients.

2. A system according to claim 1, wherein said equalizer is coupled to a storage means for storage of said weighting coefficients.

3. - A system according to claim 1 or 2, wherein said equalizer is coupled to arctangent means adapted to receive the output of said, equaliser and to produce the arctangent of the ratio of the equalized Q and I samples to produce a signal representing phase; said equaliser being also coupled to a course frequency control means which is adapted to receive said equalised 1 and Q samples, sum them to produce a lower sideband and simultaneously obtain a difference therebetween to produce an upper sideband, then obtain the magnitudes of said sidebands and thereafter obtain the difference between these magnitudes to represent a frequency error; said arctangent weans being coupled to frequency correction means which is adapted to provide a corrected frequency signal; and 9 9 (M

4. A subscriber unit for a wireless digital telephone system incorporating apparatus according to any one of claims 1 to 3.

5. , A subscriber unit according to claim 4„ ccraprising: 10 means employing repetitive frames for transmitting during one portion of each frame and receiving during another;, a baseband processor for receiving an input signal from an input source# said input signal constituting a digitized bit stream wherein each given number of 15 successive bits defines a symbol,, transcoding said input signal in accordance with a predetermined code and acting as a function control means for said unit? storage means coupled to said baseband processor for storing information associated with functions controlled 20 by said baseband processor and information supplied thereto^ control means coupled to said baseband processor in a manner permitting said control means to access said baseband processor and to obtain information stored in 25 said storage means and available to said baseband processor? said control means including programming means therefor, interpolator means for increasing the sampling rate of the trsnsccdect signal and producing a time multiplexed quadrature signal 30 fcherefrarn9 and a frequency translator means for performing a time multiplexed quadrature mixing and translating the entire frequency spectrum of the output from said interpolator means to a second frequency spectrum; fa? a digital to analog converter for receiving the tisjss wultiplexed digital signal from said frequency translator means and ccdvrertiiig it into an analog signal; c^gl itching means for resravirsg glitch energy from said analog signal% and means for converting said analog signal to an amplified IF signal-

6. The unit of claim 5 wherein said amplified IF signal is convertable by said control means to a signal of a predetermined assigned frequency; and amplifying means are provided for amplifying said signal of predetermined assigned frequency to provide as RF signal,, 7- The unit ©f claim S wherein a demodulator means is coupled to said control means for converting a second IF signal back to a bit stream. 8. The subscriber unit of claim 6 wherein that portion of said control means which is adapted to convert said IP signal to said signal of a predetermined assigned frequency comprises a frequency synthesiser having a pair of outputs wherein a first output is offset from a second output by a predetermined frequency, said first output acting to generate a frequency which, when combined with the frequency of the IF signal, provides a signal of a predetermined desired frequency, and said second output being combined with a received signal to produce a signal having the same frequency as said IF signal. 9- The subscriber unit of claim 5 wherein said baseband processor is adapted to provide echo cancellation. 10. The subscriber unit of claim 5 wherein said control means includes a modem processor that is in communication with said baseband processor via a direct memory access that prevents simultaneous access to both the baseband 9C processor and modem processor, said modem processor acting to control said baseband processor. 11. The subscriber unit of claim 5 wherein said control weans may selectively lock out the modem processor from 5 its control of the baseband processor. 12. The subscriber unit of claim 5 wherein as disconnect means is provided to selectively disconnect said input source from said baseband processor, said disconnect means being coupled to a conversion means adapted to receive an 10 originating digital signal from said control means and convert it to an analog signal, said analog signal forming a reflected signal being convertable to a reflected digital signal by said conversion means, said baseband processor being adapted to compare said reflected digital 15 signal with said originating digital signal to determine the presence of any undasired impedences or connections in the input circuit. 13. The subscriber unit of claim 5 wherein selection means are coupled to said control means for determining 20 whether a particular channel is a control channel or a voice channel, 14. The subscriber unit of claim 5 wherein a training mode is established by means of a loopback between the means for converting said analog signal to an amplified IF 25 signal and said control means via a filter means, said loopback being operative to produce correction constants? said correction constants being storable in said storage means. 15. A subscriber unit according to any one of claims 4 30 to 14, further comprising a modem comprising a modem processor including a DPSK converter coupled to a filter; said converter having a digital bit input and comprising an inverse Gray coding function whose output is applied to 5 a phase quantiser for determining the absolute value of the current symbol, said quantizer being coupled to a differential encoder for providing a differentially encoded phase value that represents the aodul© sua of the current phase and the prior absolute phase, said modulo sum being 10 computable to form the I and Q components of the current symbol; and said filter being adapted to create an oversampled PSX waveform from said I and Q components and to provide a tiae division multiplexed signal therefor. 25 is. A subscriber unit according to elaies 4, further comprising a deglitching system for removal of glitch spikes occurring during transition periods from digital signals to analog signals comprising a timing system producing a blanking signal, and means to mix said blanking signal with 20 the analog signal during said transition periods, whereby the output is returned to an intermediate reference level between the beginning and end of each of said transition periods. 1

7. A subscriber unit according to any one of claims 4 to 25 15, further conprising an interpolator for varying the sampling rate of a digital signal having tiros •divisic.n multiplexed I and Q components at an initial frequency,, comprising an input for said signal; a memory for the 1 or 0 corrponent serially copied to a memory 30 for the Q or I craiporvent; and means for applying a clock input of a predetermined frequency to both of said memories., thereby saxd time division multiplexed I and Q components are recirculated through the memories 5 during Miich they are demultiplexed at their initial frequencies and then 35 resarrpled and ramultiplexed at a second, higher frequency. 1

8. A subscriber unit according to claim 17 therein means are included for weighting the resulting I aid 0 sanples by filter coefficients, a digital-to-analog converter for converting said weighted I and Q samples to analog signals,, and means to integrate said analog signals. 1

9. A subscriber unit according to any one of claims 5 4 to 18, further comprising: selection means to determine the type ox channel in an incoming signal and to determine whether the mode of said unit is a receive mode or a transmit mode, said selection means comprising 10 means to receive signals produced by repetitive frames at predetermined intervals at a base station wherein'a portion of each of said intervals constitutes an AM hole,, the duration of said AM hole determining whether a particular channel is a control channel or a voice channel. 15 20. A subscriber unit according to claim 18 wherein a portion of the first half of each frame constitutes a receive mode and a portion of the second half of each frame constitutes a transmit mode, each of said portions comprising a slot, each of said slots containing, as part of 20 its initial data, a unique word for establishing timing for reception of remaining data in the slot. 21. A subscriber unit according to any one of claims 4 to 20, further comprising a frequency synthesiser system comprising a frequency synthesizer connected to an 25 oscillator to receive the oscillator output, said synthesizer having an output which is separated into two parts, one part forming a first output signal from the synthesiser system and the other part being passed to a mixer, said mixer being also connected to said oscillator 30 via a divider to receive a divided output of said oscillator, said divider acting to divide the output of said oscillator by a predetermined numbere said mixer acting to combine said divided output with said other part of the synthesiser output to fans a second output signal from the 35 synthesiser system, said second output signal being offset from said first output signal by said divided output of said divider. 22- A subscriber unit according to claim 21, wherein said mixer is a synchronisation detector which is coupled to a synchronous translator, said detector acting to detect, a lack of synchronisation between the freguency of a signal received from said, synthesiser and the freguency of a signal received from the synchronous translator and to provide an output signal when such lack of synchronisation is detected. 23. A transmission system substantially as hereinbefore described and as shown in Figure 8 of the accompanying drawings. Dated this the 1st day of November, 1991 . F. R. KELLY & CO., BY: EXECUTIVE. 27 Clyde Road, Ballshridge, Dublin 4. AGENTS FOR THE APPLICANTS.