IE911057A1

IE911057A1 - Level converter

Info

Publication number: IE911057A1
Application number: IE105791A
Authority: IE
Original assignee: Siemens Ag
Priority date: 1990-03-29
Filing date: 1991-03-28
Publication date: 1991-10-09
Also published as: EP0451365A3; DE4010145C1; JPH07131331A; EP0451365A2

Abstract

A level converter (PU) which is used for converting digital ECL input signals into digital CMOS output signals, is preferably connected together with a preamplifier (VV). In the preamplifier (VV), the ECL input signals are conditioned in such a manner that they can be optimally converted by the level converter (PU). The level converter (PU) can be optionally driven directly from the preamplifier output (Q) or indirectly via a bipolar transistor (Q14) in emitter follower circuit. Only one of the complementary outputs (Q,Q) of the preamplifier (VV) is needed for driving the level converter (PU). This is made possible by applying a reference voltage (VB2) to the gate terminal of a MOS transistor (M11) of the level converter (PU).

Description

The invention relates to a level converter for converting digital ECL input signals to CMOS output signals according to the precharacterising clause of Claim 1.

A circuit according to the precharacterising clause of Claim 1 is known, for example, from JP-A 63 300 20, Figure 1. The level converter disclosed therein consists of four MOS transistors which are connected in such a manner that they form the two current branches of the level converter. Each of the two current branches is connected with its external connections to each of the two supply voltages. To drive the level converter, both mutually complementary logic outputs of a preamplifier are needed.

The object forming the basis of the invention is to simplify the driveability of the level converter.

According to the invention, this object is achieved by the features specified in Claim 1.

Thus, the level converter is improved in such a manner that now only one logic signal is required for driving it. The reference voltage required for this improvement provides a further degree of freedom which can be utilised, for example, for purposes of temperature compensation. If necessary, the reference voltage can also be omitted by connecting, as a substitute, connections to which the reference voltage was to be applied, to the gate connections of the transistors involved in the current balancing circuit.

Particular embodiments and further developments of the invention are specified in the subclaims.

The driveability of the level converter by means of only one of the complementary outputs of the preampli35 fier has a particularly advantageous effect. The input of the level converter can be constructed as logic OR operation with little circuit expenditure. The same level converter is then in each case driven by several preamplifiers. This circuit capability can be utilised, for example, for using the level converter as memory decoder.

In the text which follows, several illustrative embodiments of the invention will be explained in greater detail with reference to the drawing, in which: Figure 1 shows a level converter constructed in accordance with the invention, comprising a preamplifier, Figure 2 shows a drive variant of the level converter according to Figure 1, Figure 3 shows a further drive variant of the level converter according to Figure 1, Figure 4 shows a level converter according to Figure 1 driven in complementary manner, and Figure 5 shows a level converter according to Figure 1 driven via a logic operation.

Figure 1 shows a level converter PU with preamplifier W. The base connection of an npn bipolar transistor Qll forms the input K of the preamplifier W. The collector connection of this npn bipolar transistor Qll is connected to a supply voltage VCC. Its emitter connection is connected via a current source IC1 to a second supply voltage VEE. The bipolar npn transistor Qll and the current source IC1 form the input stage of the preamplifier W. Using this input stage, the logic voltage levels normally used in ECL technology are converted in such a manner that, with predetermined voltage levels at the preamplifier output Q, Q, a saturation of the emitter-coupled bipolar transistors Q12, Q13 contained in the preamplifier W is prevented. The base connection of a second bipolar npn transistor Q12 is connected to the emitter connection of the first bipolar npn transistor Qll. The emitter connection of the second bipolar npn transistor Q12 is connected to the emitter connection of a third bipolar npn transistor Q13. At the base connection of the third bipolar npn transistor, a second reference voltage VB2 is present which determines a switching threshold with a defined voltage value at the base connection of the second bipolar npn transistor Q12. The collector connections of the second and third bipolar npn transistor Q12, Q13 are in each case used as output Q, 0 of the preamplifier W. The collector connection of the second bipolar npn transistor Q12, which emits the signals present at input K of the preamplifier W to the output Q in non-inverted form, is connected via a first load resistor Rll to the first supply voltage VCC. A second load resistor R12 connects the collector connection of the third bipolar npn transistor Q13 to the first supply voltage VCC. The emitter connections of the bipolar npn transistors Q12, Q13 are jointly connected via a second current source IC2 to the second supply voltage VEE. This second current source IC2 is of the same construction as the first current source IC1. A bipolar npn transistor Q21, Q22 is connected at its emitter connection to an ohmic resistor R to form a series circuit. The external connections of this series circuit are the connections of the current sources IC1, IC2 to be inserted into the constant current path. The base connection of the bipolar npn transistor Q21, Q22 in each case forms the control input of the current sources IC1, IC2. A third reference voltage VB3 establishing the current intensity is present at this control input.

The construction of the preamplifier W described above is identical for all further examples quoted. This is why the representation of the preamplifier W was omitted in the figures following Figure 1. What is shown are bipolar npn transistors provided for driving a level converter PU and the level converter PU. The operation of the level converter PU is not dependent on the preamplifier W, but on the fact that absolute voltage levels which can be processed by it are present at its input E.

Figure 1 shows the drive of the level converter PU by means of a fourth bipolar npn transistor Q14 used in an emitter-follower circuit. The collector connection of the fourth bipolar npn transistor Q14 is connected to the first supply voltage VCC. Controlled by the complementary output Q of the preamplifier W, the fourth bipolar npn transistor Q14 passes on the control signals, current-amplified at its emitter connection to the input E of the level converter PU. The source connection of a It 91 057 ( - 4 first p-MOS transistor Mil and the gate connection of a second p-MOS transistor M12 is connected to the emitter connection of the fourth bipolar npn transistor Q14. The drain connection of the first p-MOS transistor Mil is connected both to the source and to the gate connection of a first n-MOS transistor M13 and to the gate connection of a second n-MOS transistor M14. The drain connections of the two n-MOS transistors M13, M14 are connected to the second supply voltage VEE. The second n-MOS transistor M14 and the second p-MOS transistor M12 are connected to one another at their source connections. This junction is used, at the same time, as output A of the level converter PU at which the input signals of the level converter PU are output again in negated form. The second p-MOS transistor M12 is connected with its drain connection to the first supply voltage VCC.

The operability of the level converter PU in the form shown is ensured by the presence of a reference voltage VB1 at the gate connection of the first p-MOS transistor Mil. With a logical LOW level at the source connection of the first p-MOS transistor Mil, this transistor is cut off. When the first p-MOS transistor Mil is cut off, no current flows in the drain-source path of the first n-MOS transistor M13. Since the current in the drain-source path of the first n-MOS transistor M13 is balanced by the current flowing in the drain-source path of the second n-MOS transistor M14, no current flows in this, either. With a LOW level at the gate connection of the second p-MOS transistor M12, its drain-source path becomes conductive. Due to the simultaneous cutting-off of the second n-MOS transistor and conducting of the second p-MOS transistor M12, the voltage level of the first supply voltage VCC is approximately present at the output A of the level converter PU. With a HIGH level at the input of the level converter PU, the second p-MOS transistor M12 cuts off and the second n-MOS transistor M14 conducts. In this case, the voltage level of the second supply voltage VEE is approximately present at the output A of the level converter PU. - 5 Figure 2 shows a non-inverting level converter which is driven both directly and indirectly from output Q of the preamplifier W. The gate connection of the second p-MOS transistor M12 used as input E is directly connected to the output Q of the preamplifier W whilst the source connection of the first p-MOS transistor Mil used as input E' of the level converter PU is indirectly connected via a fifth bipolar npn transistor Q15 in an emitter-follower circuit. The collector connection of the fifth bipolar npn transistor Q15 is connected to the first supply voltage VCC, its base connection is connected to the preamplifier output Q and its emitter connection is connected to the source connection of the first p-MOS transistor Mil. At the gate connection of the first p-MOS transistor Mil, the reference voltage VB1 is present and the drain connection of the first p-MOS transistor Mil is connected to the source connection of the first n-MOS transistor M13. This junction is used as non-inverting output A of the level converter PU. The drain connections of the n-MOS transistors M13, M14 are connected to the second supply voltage VEE. Their gate connections are also connected to one another and connected to the source connection of the second n-MOS transistor M14. A link is connected from the source connection of the second n-MOS transistor to the source connection of the second p-MOS transistor. The gate connection of the second p-MOS transistor M12 is directly connected to the output Q of the preamplifier W and its drain connection is connected to the first supply voltage VCC.

With a HIGH potential at preamplifier output Q, the fifth bipolar npn transistor Q15 and the first p-MOS transistor Mil conduct. The other MOS transistors M12, M13, M14 are cut off so that the voltage potential of the first supply voltage VCC is approximately present at output A of the level converter PU. With a LOW voltage potential at output Q of the preamplifier, the previously conducting transistors are cut off and the previously cut-off transistors conduct so that approximately the - 6 second supply voltage VEE is present at output A of the level converter PU.

The level converter PU shown in Figure 3 corresponds to the level converter PU shown in Figure 1. In this variant, however, the fourth bipolar npn transistor Q14 is omitted. The input E of the level converter PU is directly controlled by the preamplifier output Q.

In Figure 4, a level converter PU is shown which needs two mutually complementary input signals. The construction of the level converter PU corresponds to that of the level converter PU shown in Figure 1. Only the type of drive is different. At output Q of the preamplifier W, the base connection of the fifth bipolar npn transistor Q15 is connected. Its collector connection is connected to the first supply voltage VCC and its emitter connection is connected to the source connection of the first p-MOS transistor Mil used as first input El of the level converter PU. The second output Q, complementary to the first output Q, of the preamplifier W is connected to the base connection of the fourth bipolar npn transistor Q14. The collector connection of the fourth bipolar npn transistor Q14 is connected to the first supply voltage VCC and its emitter connection is connected to the drain connection of the second p-MOS transistor M12 used as second input E2 of the level converter PU. The reference voltage VB1 is applied to the gate connections of both p-MOS transistors Mil, M12.

The level converter shown in Figure 5, including the fourth bipolar npn transistor Q14, Is Identical with the level converter PU shown in Figure 1. Additionally, however, a sixth bipolar npn transistor is introduced which is driven at its base connection by an output Q1 of a second preamplifier W. The sixth bipolar npn transistor Q16 is in parallel with the fourth bipolar npn transistor Q14. Its collector connection is connected to the first supply voltage VCC and its emitter connection is connected to the emitter connection of the fourth bipolar npn transistor Q14. With respect to output Ά of the level converter, the base connections of the two bipolar npn transistors Q14, Q16 are logically connected to the logic NOR function.

Patent claims 5 Figures

Claims

1. Patent Claims

1. Level converter for converting digital ECL input signals to CMOS output signals, consisting of two current branches in each case formed by a series circuit of the 5 drain-source path of one p-MOS transistor (Mil, M12) each and of an n-MOS transistor (M13, M14) each, which branches are arranged between two supply voltages (VCC, VEE), the coupling point of the series-connected MOS transistors (M12, M14) of one current branch being used 10 as logic output (S) of the level converter (PU) and the current of the other current branch being balanced in the first current branch by a current balancing circuit of the MOS transistors (M13, M14) of the same polarity which ί are connected with their source connection to the same 15 supply voltage (VEE), characterised in that a reference voltage (VB1) is connected to the gate connection of at least one of the MOS transistors (Mil) of the level converter, that the source connection of each MOS transistor (M12) not connected to the reference voltage (VB1) 20 and not involved in the current balancing circuit is connected to the supply voltage (VCC) to which the MOS transistors (M13, M14) involved in the current balancing circuit are not directly connected and that the gate connection of such a MOS transistor (M12), jointly with 25 the source connection of the MOS transistor (Mil) connected to the refer-ence voltage (VB1) is used as input C (E) of the level converter (PU).

2. Level converter according to Claim 1, characterised in that the reference voltage (VB1) is applied to 30 the gate connection of one of the MOS transistors (Mil) not involved in the current balancing circuit of the level converter (PU), that the source connection of the other MOS transistor (M12) is directly connected to the first supply voltage (VCC) and that the remaining connec35 tions of the MOS transistors (Mil, M12) are in each case connected to one another and are used as input (E) of the level converter (PU).

3. Level converter according to Claim 1 or 2, characterised in that the MOS transistors (Ml3, M14) involved in the current balancing circuit of the level converter (PU) are n-MOS transistors.

4. Level converter according to one of the preceding claims, characterised in that the first supply voltage 5. (VCC) is positive compared with the second supply voltage (VEE).

5. Level converter according to one of the preceding claims, characterised in that at the input a preamplifier (W) is connected in series, that the preamplifier (W) 10 also operating between the two supply voltages (VCC, VEE) consists of a bipolar input transistor (Qll) connected as emitter follower, to the emitter connection of which a constant current source (IC1) and the base connection of a second bipolar transistor (Q12) is connected, the 15 second bipolar transistor (Q12) being connected at its emitter connection to the emitter connection of a third bipolar transistor (Q13), to the base of which a second reference voltage (VB2) is applied, and to a second constant current source (IC2) and the collector connec20 tions of the two emitter-coupled bipolar transistors (Q12, Q13), in each case connected to the first supply voltage (VCC) via a load resistor (Rll R12), being used as mutually complementary logic outputs (Q, Q) to which in each case a further bipolar transistor (Q14) connected 25 as emitter follower can be connected, and that each input (E) of the level converter (PU) is connected directly or indirectly via the emitter connection of one of these bipolar transistors (Q14) in common-emitter circuit to an output (Q) of the preamplifier (W). 30

6. Level converter according to Claim 5, characterised in that the current sources (IC1, IC2) of the preamplifier (W) are in each case formed by a series circuit consisting of an ohmic resistor (R) and a bipolar current source transistor (Q21, Q22) which is connected 35 to a third reference voltage (VB3) at its base connection.

7. Level converter according to Claim 5 or 6, characterised in that the input (E) of the level converter (PU) is directly connected to the output (Q) of - 10 30 the preamplifier (W).

8. Level converter according to Claim 5 or 6, characterised in that the input (E) of the level converter (PU) is connected to the output (Q) of the preamplifier (W) via a fourth bipolar transistor (Q14) in emitter-follower circuit.

9. Level converter according to Claim 5 or 6, characterised in that the remaining source connection (E') is connected via a fifth bipolar transistor (Q15) in emitter-follower circuit to the output of the preamplifier (W) and that the remaining gate connection (E) is directly connected to the output of the preamplifier (W).

10. Level converter according to Claim 5 or 6, characterised in that the input (E) of the level converter (PU) is connected to the outputs (Q, Ql) of at least two different preamplifiers (W) via one bipolar transistor (Q14, Q16) each in emitter-follower circuit.

11. Level converter according to Claim 5 or 6, characterised in that in each case the base connection of a bipolar transistor (Q14, Q15) connected as emitter follower is connected to complementary outputs (Q, Q) of the preamplifier (W), that the emitter connection of these bipolar transistors (Q14, Q15) is in each case connected to a source connection, used as input (El, E2) of the level converter (PU), of one of the two MOS transistors (Mil, M12) not involved in the current balancing circuit and that the gate connections of these MOS transistors (Mil, M12) are connected to the first reference voltage (VB1).

12. A level converter according to any preceding claim substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.