IE910536A1 - Integrable circuit for processing logic signals - Google Patents

Abstract

Fast logic circuit technology has the disadvantage of generating high power dissipation. In each integrated circuit, however, there are also switching elements which do not participate in the fast switching processes. The power loss of these switching elements is reduced by replacing the load resistors with bipolar transistors and by replacing the fast bipolar switching transistors with MOS switching transistors. It is provided, for example, to use one MOS transistor (T3) as current source, two MOS switching transistors (T1, T2), which are connected at their source terminals, as current switches and two pnp bipolar transistors (T4, T5) as load resistors.

Description

Integrable circuit for processing logic signals The invention consists of an integrable circuit for processing logic signals according to the preamble of claim 1.

The number of circuit elements integrable on one chip has steadily risen as a result of refinements in the chip structure. For example, whilst at the beginning of the manufacturing phase of integrated circuits it was still possible to lead to the outside all the inputs and outputs necessary for operational testing of a gate circuit integrated in one component, in highly integrated circuits this is no longer possible because of the limited number of connecting pins. The consequence of this would be that the circuits integrated on one chip could no longer be tested and detailed error detection would no longer be possible. In order to overcome this problem, a logic test circuit is accommodated on the chip together with the circuit for producing the desired function. With the aid of this logic test circuit it is possible already on the chip to test the relevant gate inputs and outputs and then merely to supply the result of such a test to the outside via a connecting pin. The testing of logic circuits generally is not part of the regular function of the working circuit. Test circuits are only active at certain times, for example during switching-on, when possibly the demands with regard to speed are probably not as high as are the same demands made on the working circuit. High switching speeds are achieved with the known switching circuits only at the expense of permanently high current consumptions. This current consumption results in a high loss rate, excessive heating of the components and a costly cooling system for counteracting this. If there is an opportunity to reduce this high loss rate, it would be advantageous to use this opportunity. In the case of the test logic integrated on a chip, a power saving would be particularly advantageous as IE 91536 the proportion of logic test circuits to the total number of circuits integrated on a chip is in the region 10 to %.

In the case of circuits which are constructed according to the preamble of claim 1, as for example in the DE-OS 38 26 547, the current consumption of the circuit is determined by the current source alone. For example, if the current strength supplied by the current source is halved, the power loss is also reduced by a half. The outputs of the circuit are located in the two current arms between the load resistances and the main current paths of the switching transistors. The two possible logic conditions are produced by the blocking or conducting of the main current path of a switching transistor. In the ideal situation - zero load output - no current flows through the load resistance when the transistor's main current path is blocked. The level of the second constant supply voltage is available at the output. When the main current path of the switching transistor conducts, the current determined by the current source flows through the main current path of the switching transistor and through the load resistance. Across the load resistance there is a voltage drop which corresponds to the difference in level between the two logic conditions at the output. This difference in level, in the following referred to as logical swing, must not drop below 95% of its maximum value if it is to be evaluated properly and error-free. However, in contrast to the ideal condition, into the control input of a logic circuit connected in series with the circuit being looked at flows a current which is smaller, by the current amplification factor B, than the current in the main current path of the input switching transistor of this series connected logic circuit.

From the fact that the logical swing must not be allowed to drop to below 95% of its maximum value, follows the condition that the current in the main current path of the series connected logic circuit must be smaller, by the current amplification factor B, than 5% of the current which flows in the main current path of the circuit being looked at. Realisable values of the current amplification factor lie at around 50. By applying this value to the aforesaid condition the current in the main current path of the circuit being looked at must be at least 0,4 times as big as the current in the main current path of the series connected logic circuit. If several interconnected logic circuits operate with identical currents in the main current path, up to three inputs of a logic circuit can be connected to one output. In contrast to this, with the output of a logic circuit, in whose main current path flows only 0,4 times the current that normally flows, it is possible to drive only one input of a logic circuit operating with full current. Reducing the power by only a half, therefore has the drawback of reducing the so-called FAN-OUT from approximately 3 to approximately 1.

The object of the present invention consists in providing a possibility for power reduction which does not simultaneously result in a reduction of the FAN-OUT.

This object is achieved through a combination of the features of the preamble and the features of the characterising part of claim 1.

Achieving this object is based on the recognition that the object cannot be achieved alone by changing the ratings of the load resistances and changing the current consumption of a circuit. In consequence of this recognition, in the present invention all the usual components used in typical logic circuits are exchanged for different components which, moreover, also belong to other technologies. In circuits according to the preamble, for switching and current source transistors normally pnp bipolar transistors are used which - not driven at saturation - guarantee a high operating speed in the logic circuit. If these switching transistors are replaced by MOS switching transistors, whilst no longer having the previously high processing speed, because of the high resistance gate inputs such a circuit does have advantages with regard to reducing the power loss. In combination with the change in switching transistors, the load resistances commonly used in the current arms are exchanged with collector-emitterlines of pnp bipolar transistors. Whilst the currentvoltage characteristic curve of an ohmic resistance follows a linear course - in other words the resistance value is always constant - the collector current rises steeply when the collector-emitter-voltage is small, changing hardly at all with higher collector-emitter-voltages. Therefore, when the pnp-type bipolar transistor conducts, it has a low resistance; if it blocks, it has a very high resistance value. With the aid of this pnp bipolar transistor, used as a load resistance, it is possible therefore, depending upon the particular need, to change the value of this load resistance. If the drain-source-line of an MOS switching transistor referred to as the transistor main current path is conducting, a high load resistance with a small current ensures a sufficiently large logical swing in the output level, with the drain-source-line of the MOS switching transistor blocked, on the other hand, a low-resistance load guarantees a small voltage drop even when the output load is of relatively low resistance.

The intended change in the load resistance is achieved by connecting the base terminals of the pnp bipolar transistors to the other current arm respectively. In the present circuit, which can also be looked upon as a differential amplifier, only one of the two drain-sourcepaths of the MOS switching transistors respectively conducts, while the other one blocks. Complementary output conditions are always present at the drain terminals of the two MOS switching transistors, which form the logic outputs of the circuit. Therefore, when the first switching transistor blocks, approximately the second constant supply voltage is applied to its drain terminal. The pnp-type bipolar transistor, whose collector-emitter-line forms the load resistance for the current arm in which is located the second MOS switching transistor, is blocked and thus at high resistance, as its base is connected to the drain terminal of the first MOS switching transistor. The drain terminal of the second MOS switching transistor, which is connected to the base terminal of the pnp-type bipolar transistor whose collector-emitter-line is located in the same current arm as the first MOS switching transistor, is at a relatively low potential - low level -. This low potential makes the pnp-type bipolar transistor conductive or low resistance.

This slow and current-saving circuit can be advantageously used in combination with a pure bipolar logic current circuit, which is faster by a factor of 100. The highresistance input of the first MOS switching transistor hardly puts any load on the output of a preceding switching stage, thereby not interrupting the fast switching processes during the normal operation of the integrated circuit. Despite a small internal current consumption as a result of the variable load resistances, the circuit can drive a large number of series connected switching stages purely in bipolar technology.

The current amplification of the pnp-type bipolar transistors is the drawback, as it leads to different current strengths in the two current arms of the circuit. These different current strengths effect a hysteresis in the current switching threshold of the logic circuit. Thus, for example, the second MOS switching transistor, whose drain terminal is at a low level (-0,8V), can only be blocked when the gate terminal of the first MOS switching IE 91536 transistor is at a potential of -0,1 volt, i.e. switch to the high condition (OV), whereas this second MOS switching transistor can be transformed into the conducting condition again only when -0,4 volt is applied to the gate terminal of the first MOS switching transistor. The absolute switching thresholds, which are based on this hysteresis, heavily depend upon the strength of the current amplification of the pnp-type bipolar transistors - apart from the supply and reference voltages - and also upon whether this current amplification is equally high in both the pnp-type bipolar transistors. Technologically these demands, which have resulted from the said dependency on the current amplification of the two pnp-type bipolar transistors, can be realised only with the greatest of difficulties, whereas the features of claim 2 provide a useable means for controlling the current amplification and therefore the hysteresis. The emitter space relationship of the pnp-type bipolar transistors connected together to form a current mirror determines the total current amplification substantially independent of individual current amplifications. The adjustment of specific emitter space relationships can be controlled technologically. It is thus possible to select the desired hysteresis or to completely eliminate the hysteresis during the manufacturing process of the circuit.

With the present circuit in the form described up to now it is possible to produce only the basic function of a logic circuit, a so-called inverter with complementary output. In other known circuits, for example of the ECL type (EmitterCoupled-Logic) , this basic function is expanded to other more complex functions..

By connecting the drain-source-line of a further MOS switching transistor, also serving as gate input, in parallel with the drain-source-line of the MOS switching transistor serving as gate input, the basic function of the logic circuit is expanded to include an OR/NOR function. As in the known ECL type, this is achieved by connecting in parallel one or more main transistor current paths with the main current path of the input switching transistor.

A further possibility to realise more complex logic functions with the logic circuit described is provided by the method referred to in ECL technology as series gating. With series gating is described a series connected logic operation in which the current switches are arranged on top of each other and supplied together from the same current source. These circuits, comprising purely of bipolar technology, can also be used with the features referred to in claim 4 of the present invention. By introducing MOS switching transistors, connected together at their source terminals, at the connecting points between MOS switching transistors and pnp-type bipolar transistors it is therefore possible to produce NAND/AND logic operations, EXOR logic operations, multiplexers, flip-flops and combinations of all the logic operations.

In the ECL-type series gating circuits the logic voltage and reference voltage levels originating from outside e.g. from adjacent gates -, depending on the requirement for the individual series connected current switches, must be shifted by means of level converters. By using MOS switching transistors this level shifting can be avoided, as a variation in the area of an MOS transistor can have an effect on its current-voltage characteristic. The MOS switching transistors connected together at their source terminals each form a current switch. Changing the area of the MOS switching transistors from one current switch to another and applying to each of these current switches the same reference voltage, causes the absolute levels of the switching thresholds to differ from current switch to current switch. The consequent use of this effect can therefore render level shift circuits obsolete, resulting IE 91536 in a further current saving effect and a saving of space on the chip which would otherwise be required by the level converters. The change in the switching threshold of the current switches achieved through technological means also means that the need for various reference voltage levels becomes obsolete and a reference voltage can simultaneously be applied to several current switching transistor pairs arranged either in parallel or series.

Several embodiment examples of the invention are explained in more detail with the aid of the drawings as follows. These show: Fig. 1 a typical ECL gate without emitter followers at the outputs, Fig. 2 an inverter circuit according to the invention with complementary outputs, Fig. 3 a circuit according to Fig. 2 which has been expanded by two current mirror transistors, Fig. 4 a circuit according to Fig. 2 with a second MOS input switching transistor, Fig. 5 a circuit according to Fig. 2 with a further current switch.

Fig. 1 shows a typical CML-type inverter circuit. CML-type is referred to a current switching technique which differs from the ECL-type only in that the npn-type bipolar transistors in the emitter follower circuit are not present at the output. The current source is provided by a npn-type bipolar transistor TB3 whose emitter terminal is connected to a constant supply voltage VEE to the base terminal of which is applied a reference voltage VSM for controlling the current strength and whose collector terminal is 91536 connected both to the emitter terminal of a first npn-type bipolar switching transistor TB1 as well as the emitter terminal of a second npn-type bipolar transistor TB2. The collector terminals of the two npn bipolar switching transistors TB1, TB2 serve as mutually complementary outputs Q, ζ of the inverter circuit and are each connected via a load resistance Rl, R2 with a second constant supply voltage VCC which is positive with respect to the first constant supply voltage VEE. The switching threshold of the inverter is determined with the aid of a second reference voltage which is applied to the base terminal of the second npn-type bipolar switching transistor TB2. The inverter input E is formed by the base terminal of the first npntype bipolar switching transistor TB1.

Fig. 2 shows the circuit according to the invention. The MOS transistors shown in this and the subsequent Figs, are so-called self-blocking n-type MOS transistors. The source terminal of an MOS transistor T3 is connected to the supply voltage VEE. This MOS transistor is used as the current source and is controlled at its gate terminal by the reference voltage VSM. The drain terminal is connected to the source terminals of two MOS switching transistors Tl, T2. The drain terminals of these two MOS switching transistors Tl, T2 serve as complimentary gate outputs Q, ζ> the same as the collector terminals of the pnp-type bipolar switching transistors TB1, TB2, in Fig. 1. The drain terminal of the first MOS switching transistor Tl is connected to the collector terminal of a pnp-type bipolar transistor T4 and to the base terminal of a second pnp-type bipolar transistor T5 and the drain terminal of the second MOS switching transistor T2 is connected to the collector terminal of the second pnp-type bipolar transistor T5 and to the base terminal of the first pnp-type bipolar transistor T4. The emitters of the two pnp-type bipolar transistors T4, T5 are supplied by the second constant supply voltage VCC. To the gate terminal of the second MOS switching transistor T2 is applied the second reference voltage VB1 which is used for adjusting the switching threshold of the inverter, as in Fig. 1. The gate terminal of the MOS switching transistor Tl forms the inverter input E.

In Figs. 3, 4 and 5 are shown preferred further developments of the circuit according to Fig. 2.

In Fig. 3 a third and a fourth pnp-type bipolar transistor T6, T7 are additionally included in the circuit. The base and the collector terminals of the third pnp-type bipolar transistor T6 is connected to the base of the first pnptype bipolar transistor T4 and the base terminal and the collector terminal of the fourth pnp-type bipolar transistor T7 is connected to the base terminal of the second pnp-type bipolar transistor T5. The emitter terminals of the additionally included pnp-type bipolar transistors T6, T7 are connected to the second constant supply voltage VCC. The first and the third pnp-type bipolar transistor T4, T6 and the second and the fourth pnp-type bipolar transistor T5, T7 therefore each form a mirror current.

Additionally to the circuit shown in Fig. 2, Fig. 4 also shows an MOS switching transistor Til. Both the drain as well as the source terminal of the MOS switching transistor Til is connected to the corresponding terminal of the first MOS switching transistor Tl. The gate terminal of the MOS switching transistor Til additionally introduced into the circuit forms a second gate input El. Relative the gate outputs Q or the inputs E and El form the inputs of an OR NOR gate.

Fig. 5 shows an AND or NAND gate with the input E and an input E2 and the outputs Q or Q. Between the complementary output Q and the drain terminal of the first MOS switching transistor there is introduced the drain source path of a third MOS switching transistor T8. This MOS switching transistor T8 together with a fourth MOS switching transistor T9, whose source terminal is connected to the source terminal of the third MOS switching transistor T8, forms a second current switch which is arranged in series with the first current switch made up of the two MOS switching transistors Tl, T2. On the basis of this series connection this variation of the circuit is also known as series gating circuit. The switching threshold of the second current switch is determined by the connection of the gate terminal of the fourth switching transistor T9 to the second reference voltage VB1. The drain terminal of the fourth MOS switching transistor T9 is connected to the output Q. The two series connected current switches operate despite the fact that the switching threshold is determined by a single reference voltage VB1 at different absolute voltage levels. This is possible because the MOS switching transistors T8, T9 or Tl, T2 on the semiconductor chip occupy geometric areas of varying size.

Instead of n-channel MOS switching transistors and pnp-type pipolar transistors, in a similarly advantageous manner it is also possible to use p-channel MOS switching transistors and npn-type bipolar transistors when the operating voltages have their polarities reversed.

Claims (7)

1. Integrable circuit for processing logic signals with two current arms each formed by connecting a load resistance in series with the main current path of a switching transistor, which current arms at one end are together supplied from a current source and at the other end are connected to a constant supply voltage (VCC), and in which the control input of the respective switching transistor serves as the gate input or as connecting point for a reference voltage (VB1) for determining a gate switching threshold, wherein the current source is embodied by an MOS transistor (T3) which has a second reference voltage (VSM) applied to the gate terminal and a second constant supply voltage (VEE) is applied to the source terminal, the drain terminal of the MOS transistor (T3) being connected to the source terminals of two MOS switching transistors (Tl, T2), and in which the gate terminal of the first MOS switching transistor (Tl) serves as gate input and the reference voltage (VB1) is applied to the gate terminal of the second MOS switching transistor (T2) , characterised in that the collector-emitter-line of each bipolar transistor (T4, T5) serves as the load resistance, the base of the bipolar transistor having the same type of conductivity as the channel of the first and second MOS switching transistor (Tl, T2), and that each base terminal of a first bipolar transistor (T4, T5) is connected to the collector terminal of the bipolar transistor (T5, T4) in the other current arm respectively. IE 91536

2. Circuit arrangement according to claim 1, characterised in that the first and second MOS switching transistor (Tl, T2) are of the n-channel type and the bipolar transistors (T4, T5) are of the pnp-type.

3. Circuit arrangement aooording according to claim 1 or 2, characterised in that to each base terminal of the bipolar transistors (T4, T5) is connected a further bipolar transistor (T6, T7) , serving as current mirror, both with its base terminal as well as with its collector terminal, and that the emitter terminals of the bipolar transistors serving as the current mirrors are connected to one of the two constant supply voltages (VCC,VEE).

4. Circuit arrangement according to claim 1 or 2, charcaterised in that parallel with the drain-source-path of the MOS switching transistor (Tl) serving as the gate input is connected the drain-source-line of at least one further MOS switching transistor (Tl) also serving as a gate input.

5. Circuit arrangement according to claim 1 or 2, characterised in that at the connecting point of at least one of the MOS switching transistors (Tl, T2) leading to the bipolar transistors (T4, T5) two further MOS switching transistors (T8, T9) are interconnected in such a way that the source terminals of this third and fourth MOS Switching transistor (T8, T9) are connected to the drain terminal of the first or second MOS switching transistor (Tl, T2) and the drain terminal of the third MOS switching transistor (T8) is led to the collector terminal of one of the bipolar transistors IE 91536 (T4, T5) and the drain terminal of the fourth MOS switching transistor (T9) is led to the collector terminal of the other bipolar transistor (T4, T5) , and that the gate terminal of the third or fourth MOS switching transistor (T8, T9) serves as a further gate input, while to the still remaining gate terminal of the fourth or third MOS switching transistor (T9, T8) is connected a third reference voltage for determining the switching threshold of the interconnected gate.

6. Circuit according to claim 5, characterised in that the second reference voltage (VB1) for determining the gate switching threshold is additionally used as third reference voltage without shifting the level.

7. A circuit arrangement according to any preceding claim substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.