IE76474B1 - Control arrangements for a bus connection - Google Patents

Abstract

Bus link control in a program-controlled communication system (K) with a program-controlled HDLC control structure under the requirements of a communication system equipped with only one processor. A link processing program module (PMSA) of the HDLC control structure of the bus link discriminates between necessary and time-uncritical system tasks (NS, NSZS, ZUS) during the processing. After conclusion of the system tasks necessary in every case (NS, NSZS), a clock pulse counter (T) is interrogated, the counting pattern (Z) of which is short compared with the processing cycle (BZY). If the time value of the count (Z) of the clock pulse counter (T) is, for example, shorter than half the processing cycle (BZY), processing of time-uncritical system tasks (ZUS) is begun. <IMAGE>

Description

Siemens Aktiengesellschaft Control arrangement for a bus connection The invention relates to a control arrangement for a bus connection, particularly of a High Level Data Link Control (HDLC) transmission method, on a data bus between a central processor of a program-controlled conraunications installation or switching equipment and access modules of the communications installation, for example an analogue/digital access module and/or an access module for exchange lines, in which arrangement the access modules connected to a common data bus are connected via a module control to a bus structure of a central processor used for controlling the communications installation.

Program-controlled communications installations in communications systems are used for connecting communications terminals with one another and for connecting these communications terminals fo communications networks , particularly coupling networks.

Independently of the degree of complexity of the basic communications system, a communications installation, in principle, consists of a multiplicity of switching function units and a programmable digital processor system which monitors these function units by means of a multi-tasking operating system and initiates and controls all switching sequences.

For monitoring and controlling function units, particularly access modules such as, for example, analogue subscriber access modules (SLMA), conference switching modules (CONF) or an access module for exchange lines (TML) in a communications installation, it cannot be avoided that the central processor continuously monitors, for example, the operational status of the access modules or detects signalling information present and then immediately forwards appropriate control information to the correspondingly addressed access modules. Ρ 1294Ε It has hitherto been usual for signalling information of the access modules connected via a data bus to be processed by a central processor of the computer system in accordance with a master/slave method. The central processor here handles the role of the master and the access module that of the slave. The interrogation and processing of the access modules is in this case initiated and controlled by the central processor of the communications installation by means of interrogation procedures. The signalling changes present at the access modules are in this case detected, interrogated and evaluated by the central processor.

The method for interrogating the signalling and allocating control data to the access modules connected via the data bus is predetermined by a protocol for the message traffic produced; a) Interrogating for signalling informations — Polling by the central processor — Information string from the access module — Acknowledgement by the central processor b) Transmission of control data; — Send control by central processor — Acknowledgement from the access module The protocol. for the message traffic is designed in such a manner that an action (signalling interrogation/control data allocation), which was initiated by a polling of the central processor, must first be completely finished before an item of signalling information of another access module or of a higher priority process can be processed. This leads to considerable time-critical problems, especially in communications installations and particularly in key telephone installations since, on the one hand, the central processor continuously carries out system tasks of the communications system, operated in the multi-tasking operating system, of the communications installation which must be continuously processed and, on the other hand, detects and processes the signalling information of the access modules within a P 1294E particular period of time. When high loads occur, e.g. maximum switching capacity, this leads to considerable restrictions in the facilities of the communications installation, for example high waiting times of the telephone subscriber. ? In addition, a process of interrogating the access module or of the transmission to the access module * must not be disturbed by a higher priority process in a multi-tasking operating system since, otherwise, data from the central processor are conducted to function units for which they are not intended.

The consequence of data forwarded wrongly or incompletely would be a failure of facilities. An exclusive allocation of the central processor for processing access modules, in addition, leads to unacceptable high waiting times for the telephone subscriber or to blockages for other system tasks to be carried out in the communications installation.

To eliminate the listed restrictions of facilities of the communications installation, it is known (SP 0 347 S44 Al) to combine the access modules connected to a bus system via preprocessors. The entire protocol of the message traffic produced from and to the access modules of the communications installation is handled by the preprocessors. In this arrangement, the preprocessors convert the signalling information of the access modules into switching events.

The object forming the basis of the invention consists in specifying another bit-oriented transmission control method under the requirements of a system equipped with only one processor, particularly a programcontrolled communications installation, which enables a bus system to be processed.

A solution to this problem can be found in Claim 1. Apart from the economic advantage of saving one or more preprocessors, the invention also has the further advantage that, in spite of maximum utilisation of the switching function units of the communications Ρ 1294Ε installation such as, for example, with maximum possible switching load and simultaneous presence of signalling information at all access modules, all facilities of the communications installation, remain available.

Due to the calling-up of a memory process program module which converts the switching-module-specific signalling information, temporarily stored in the system memory, into time-critical system events and timedistributed system events, in which process it allocates a lower or higher priority to the system events within the operating system and processes these, the timedistributed system events being ordered into a memory area of a time management system, the invention entails the advantage that the processing of the access-modulespecific signalling information saved in the system memory is carried out in a time interval pattern dependent on the type of access module. The time-critical and the time-distributed system events are in each case inserted time-optixnally between the procedures to be processed by the operating system of the communications installation.

If is a further development of the invention that the counting interval of the clock counter carried in the background is small compared with a processing cycle. The counting interval is preferably < 1/4 of the period of the processing cycle. This has the advantage that, on the basis of the count ox the clock counter, a qualified statement can be mad® whether and which time-uncritical system task(s) can still be processed.

A further advantageous development of the invention is that a first output program module converts control information to the access modules into an accessmodule—specific format and enters this in a first output memory. Apart from the advantage of better utilisation of the central processor, this entails the advantage that it is not necessary to arrange separate access-modulespeeific converters in each access module. Ρ 1294Ε 'it is a further development of the invention that the memory processing is carried out in accordance with the FIFO mode (First In, First Out) . This entails the advantage that the access-moduls-specific control data are again read out of the memory in accordance with the time sequence in which they have been read in to the first output memory and during this process the logic sequence of a connection set-up or connection clear-down, for example of a call connection or of a conference circuit, is retained in accordance with the operation system of the communications installation.

According fo the logical sequence of a connection set-up/clear~down, the time sequence of the requests of the relevant access modules is saved under the aspect of time-distributed or time-critical system tasks.

It is a further development of the invention that a second output program module enters time-uncritical access-module-specific control information, particularly maintenance information, operating software for access modules or record data for the operational software, in a second output memory and transfers this information to the access modules in a second time slice of the operating system in accordance with the time interval pattern. Apart from the advantage of an optimal time utilisation of the processing cycle with system tasks to be executed, this also entails the further advantage that the communications system can interrupt the transmission of the time-uncritical control information at any time in order to handle, for example, higher priority system processes such as switching functions.

Further features of the invention will now become apparent from subsequent more detailed explanations of a bit-oriented transmission method, for example of a High Level Data Link Control -HDLC- control structure on an HDLC bus in accordance with the invention, by referring to the drawings, in which: Ρ 1294Ε β Figure 1 shows a block diagram of an HDLC bus integrated in a communications installation, Figure 2 shows a diagrammatic view for illustrating the allocation of program modules via a process list, Figure 3 shows how an HDLC control structure is integrated into an operating system.

Figure 4 shows an interaction of program modules.

Figure 5 shows a flowchart of a link processing program module.

Figure 1 diagrammatically shows an HDLC bus integrated into a communications installation K to the extent required for understanding the invention.

A multiplicity of lines ΚΑΝΙ,..., XANn or exchange lines AL1, ..., ALn can be connected via the access modules ABG, such as, for example, analogue subscriber access modules (SLMA), conference circuit modules (CONF) or access modules for exchange lines (TML).

An item of signalling information I can be present at individual or at all access modules ABG at the access modules ABG (SLMA, CONF, TML) of the communications installation X. An HDLC bus connects the access modules ABG to a module control PBC. The module control P3C is connected to the bus system (address bus, data bus, signal bus) of the central processor CP. The transmission of data on the HDLC bus, controlled by the central processor CP, can be carried out, for example, in half duplex mode, that is to say that the HDLC bus is always released in only one direction of transmission for each data transmission. The signalling information I to be transmitted from the access module ABG to the module control PBC or the control information ST to be transmitted from the module control PBC to the access modules ABG is transmitted in an HDLC transmission procedure.

P 1294E The H'DLC transmission procedure corresponds to the procedures of a first and second layer (physical layer, data link layer) of the Open System Interconnection (OSI) model. This OSI reference model has been standardised by the International Standardisation Organisation (ISO) in collaboration with the CCITT.

The transmission frame necessary for the transmission procedure, essentially consisting of a bit sequence for frame delimiting, address field, control field for instructions or messages, field for the data to be transmitted and a frame check sequence, is used for data transmission and for data protection during an HDLC transmission procedure. In this arrangement, the module control PBC has the task of taking the transmitted data (signalling information I) from the transmission frame and to carry out a serial/parallel conversion of the signalling information I transmitted from the access modules ABG and, on the other hand, to carry out a parallel/serial conversion of the control information ST to be converted. In addition, the serially transmitted signalling information I is checked for transmission errors and corrected by the access modules ABG.

A further module, a system memory SSP, is connected to th® address, signal and data bus of the bus system of the central processor CP as shown in Figure 1. The system memory SSP consists of semiconductor memory chips of different memory type? an EPROM memory in which the entire system program is unmodifiably stored? a RAM memory which is used as read/write memory? an EEPROM memory in which operator data such as abbreviated dialling numbers are stored. Since th® data of the RAM memory are lost in the event of a voltage failure, a mains-independent voltage source such as a battery ensures that the stored data are preserved.

The system memory SSP and the module control PBC are connected to the central processor CP via the data bus. Ρ 1294Ε Figure 2 shows by means of diagrammatically shown function blocks how a system processor SYPR arranged in a central processor CP interacts with an operating system BS, a process list PL and stored program modules PMx.

In principle, the system processor SYPR is exclusively used for processing the program designated as operating system BS. This operating system program is designed In such a manner that it selects, dependent on incoming system tasks such as, for example, necessary system tasks NS, NSZS, time-uncritical system tasks ZUS or incoming system events such as, for example, timedistributed system events ZVSA, time-critical system events ZSA, successively in each case an available program module PMx. such as, for example, a link processing program module PMSA, a memory processing program module PMAB or a task module PMAG and allocates these for a certain period of time to the system processor SYPR for execution. Each program module PMx is stored as a program code sequence in the system memory SSP and has a name NA, for example a letter combination SA, AB, AG and a priority value PR. The operating system BS, particularly the multi-tasking operating system BS has available the process list PL in which it notes the ready-to-ru.n program modules PMx by entering the name NA, the priority value PR and the address AD of the program module PMx in the system memory SSP, and from which it then determines the in each case highest priority program module PMx for assignment to the system processor SYPR.

If a program module PMx is allocated to the system processor SYPR, the relevant program module PMx can retain the system processor SYPR until either a higher priority program module applies for allocation of the .system processor SYPR or until it leaves the system processor SYPR of Its own accord. The latter also applies primarily when a program module PMx needs certain information to be produced by other program modules for processing its system tasks/system events and must wait for the arrival of this information. Ρ 1294Ε Figure 3 shows the processes to be controlled by the operating system BS of a communications system K. Priority values PR are allocated to the individual processes in accordance with their urgency for the operating system BS. The processes to be coordinated by the operating system 3S receive the following priority values PRs Priority value 1 (highest priority value): Administration of the individual processes, for example operating-system-ovn timers, switching-over of priorities.

Priority value 2: User processes, the tasks of which are executed time-critically per user, for example time control of signalling tones in exchange traffic.

Priority value 3: Event saving, event output and time-critical tasks, for example dialling protection and forwarding. Priority value 4: User processes, the tasks of which can be executed time-distributably per user, for example path switching, switching of the speech paths.

Priority value 5s Time management, which carries out a uniform forwarding of the saved events, distributed to the active users.

Priority value 5s Administration and test tasks, for example cyclic memory tests, customer data records .

The signalling information items I transmitted via the HDLC bus from the access modules ABG and the resultant system task/system events or the control information items ST to be transmitted to the access modules ABG via the HDLC bus are detected by the operating system BS of the communications installation K and appropriate processes are initiated.

The system tasks for HDLC link processing are processed by the operating system BS of the central 0» P 1294E processor CP of the communications installation K by means of a link processing program module PMSA.

In this arrangement, the program module PMSA is noted with the highest priority value PR (Priority value 1) in the process list PL. One of the reasons why the highest priority value PR (1) is assigned to the link processing program module PMSA is that it must be ensured that each item of signalling information I can be detected and saved by the access modules ABG.

An output program module PMAG for outputtingcontrol information ST is assigned the priority value 2 in the process list PL.

A memory processing program module PMAB for the access-module-specific signalling information I stored in a particular memory area of a RAM memory IABG1, IABG2,..., lABGn of the system memory SSP (see FIG. 4) is assigned the priority value 3.

Figure 4 shows the interaction of the program modules for HDLC link processing: link processing program module PMSA, memory processing program module PMAB, first output program module PMAG, second output program module PMBG.

The link processing program module PMSA has the task of initiating and executing the scanning process of the access modules ABG in the correct time during a processing cycle BST and to store the signalling information I of the access modules ABG within a memory area IABG1, IABG2,..., lABGn (e.g. RAM memory), allocated to th© respective access modules ABG, of the system memory SSP of the communications installation K.

The link processing program module PMSA distinguishes between necessary system tasks NS and timeuncritical system outputs £U3 during a processing cycle BS¥.

A necessary system task NS is the saving of the signalling information I in the memory area IABG1, IABG2,..., lABGn of the system memory SSP, provided for this purpose.

P 1294E After the necessary system tasks NS to be executed immediately have been processed, further system tasks NSZS, stored as necessary in a first time slice SSI in a time interval pattern SR, are processed by the link processing program module PMSA. Furthermore, the link processing program module PMSA, taking into consideration the duration of the processing cycle BSY, has the task of transferring the control information ST, stored in a first and second output memory ASP1, ASP2, to the access modules A3G.

The control information items ST, stored in the second memory ASP2 by using a time interval pattern SR in a second time slice ZS2, are only read out by the link processing program module PMSA when the control information ST stored in the first memory ASP1 has been completely read out. The reading and writing out of and into the first memory ASP1 occurs in accordance with the FIFO - First In, First Out - mode in this arrangement.

A program module PMAB provided for memory processing has the task of reading out from the system memory SSP the access-module-specific signalling information I, temporarily stored in a certain memory area IABG1, IABG2,..., lABGn of the system memory SSP, to convert it into system events and to forward it to receiver modules. During the distribution of the system events to the respective receiver module(s), a distinction is in each case made between time-distributed system events ZVSA. and time-critical system events ZSA. The processing of the time-distributed critical system events ZVSA can occur time-distributed within an acceptance time. Time-critical events SSA are forwarded by a message traffic within the operating system BS to a higher priority process where they are immediately processed.

A first output program module PMAG and a second output program module PMBG have the task of in each case converting the control information ST of the communications system K into an access-module-specific format P 1294E corresponding to the access module ABG and to store this in each case in the associated output memories ASP1, ASP2.

Figure 5 shows a flow chart by means of which the essential programming steps of the link processing program module PMSA within a processing cycle BZY can be traced.

As indicated in Figure 3, the highest priority value is assigned to the link processing program module PMSA.

Within the processing cycle BZY of an HDLC link processing process, a distinction is made between necessary system tasks KS to be processed immediately and necessary system tasks NSZS to be processed, which are distributed to a first time slice ZS1 with the aid of a time interval pattern ZR. As a first program step, the processing of the necessary system tasks NS such as, for example, the scanning of the access modules ABG is first carried out by the link processing program module PMSA.

Following this, the necessary system tasks NSZS (system task 1 to system task N), which are distributed in the first time slice ZS1 in the time interval pattern ZR, are handled. A necessary system task NSZS contained in the first time slice ZS1 is the interrogation of a failure detection of an access module ABG after a time interval of 50 ms. After all necessary system tasks NS, NSZS have been processed, a clock counter T of a timer ZUS is interrogated for its count 2.

The time interval of the counting pattern ZR of the clock counter T in the timer ZUE is preferably 2 ms. The duration of the processing cycle BZY is preferably 10 ms.

If the time value of the count Z of the clock counter T, after completion of all ths necessary system tasks NS, NSZS, corresponds to the period of the processing cycle BZY, the link processing program module PMSA starts again with the necessary system tasks NS, Ρ 1294Ε NS 2 3 to be executed within & processing cycle 32 Y.

If the time value of the count 2 of ths clock counter T is still within the period of the processing cycle 32Y, the processing of time-uncritical system tasks 2US can be begun. A time-uncritical system task is, for example, the transmission of control information (items) ST via the HDLC bus to the access modules ABG. The count 2 of the clock counter T is again interrogated in each case after conclusion of a time-uncritical system task ST. If the count 2 has not yet reached a predetermined value of 2 in a time interval of the time interval pattern 2R of 2 ms, the further processing of a further time-uncritical system task 2US can be begun. After each processing of a time-uncritical system task 2US, the count 2 of the clock counter T of the timer 2UE is again interrogated. The time value of the count 2 then decides whether a new processing is carried out or whether the time-uncritical system processing is terminated.

Claims (7)

1. Patent claims

1. Control of a bus connection in a program-controlled communications installation (K) or switching equipment between a central processor (CP) and at least one access module (ABG), the access modules (ABG) connected to a common bus (HDLC) being connected via a module control (PBC) to a bus structure (signal bus, data bus, address bus) of a central processor (CP) used for controlling the communications installation (K), characterised in that the processing of an item of accessmodule-specific signalling information (I) present at the access modules (ABG) via a link processing program module (PMSA) equipped with high priority (PR) is noted as ready to run in a process list (PL) of the central processor (CP), in which arrangement the link processing program module (PMSA), distinguishing between necessary system tasks (NS) and time-uncritical system tasks (ZUS) detects within a processing cycle (BZY) an access-module-specific signalling information item (I) which is present as a necessary system task, and stores the signalling information temporarily in a system memory (SSP), allocated to the access modules (ABG), of the central processor (CP), then processes the necessary system tasks (NSZS) ordered in a first time slice (SSI) in a time interval pattern (ZR) and then initiates cyclic time-uncritical system tasks (ZUS) in accordance with a count (Z) of a clock counter (T) controlled by interrupt control in the background.

2. Control of a bus connection according to Claim 1, characterised in that a memory processing program module (PMAB) converts the access-module-specific signalling information (I), temporarily stored in a system memory (SSP), into time-distributed system events (ZVSA) and time-critical system events (ZSA) and, assigning a lower or higher priority (PR) to the system events (ZVSA, ZSA) within the operating system (BS), processes the corresponding program modules (PMx), the time-distributed 91 Ρ 1294Ε system events (ZVSA) being ordered in a memory area (S) of a time management system (ZM).

3. Control of a bus connection in accordance with Claim 1, characterised in that the time interval pattern 5 (2) of the clock counter (T) controlled in the background is small compared with one processing cycle (32Y).

4. Control of a bus connection according to Claim 4, characterised in that a first output program module (PMAG) converts control information (ST) to the access 10 modules (A3G) into an aceess-module-speeific format and stores this in a first output memory (ASP1)..

5. Control of a bus connection according to Claim 4, characterised in that the memory processing of the first output memory (ASP1) is carried out in accordance with 15 the FIFO mode.

6. Control of a bus connection according to Claim 1, characterised in that a second output program module (PMBG) enters time-uncritical access-module-specific control information (ST), particularly maintenance 20 information, into a second output memory (ASP2) and transfers this information as time-uncritical control information (ST) into a second time slice (2S2) in accordance with a time interval pattern (2R).

7. A control of a bus connection according to any preceding claim substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.