IE60874B1 - Data transmission method for a digital switching system and arrangement for carrying out the method - Google Patents

Abstract

The invention describes a system architecture for a digital switching system in which signalling and packet data are exchanged collision-free and without data loss between terminal stations (E) and a higher-level unit (PAD). In a subordinate unit (LCi), data flowing in the direction of the higher-level unit (PAD) are separated and signalling data are preprocessed. Signalling and packet data flowing in the direction of the terminal station are switched to the same data channel and, using a monitoring device, a control signal identifying the state of the data channel is conducted to the higher-level unit (PAD). The architecture is modular and thus variably adaptable to different packet data loads.

Description

The invention relates to a data transmission method for a digital switching system according to the preamble of Patent Claim 1 as well as to an arrangement for carrying out the method according to the preamble of Patent Claim 8.

Modern digital switching systems are hierarchically organised computer-controlled systems with a great variety of incoming subscriber lines. The units of the switching system perform the tasks of receiving and forwarding income data. On the hierarchical level of a switching system, superordinate units may be, for example, a local exchange, a long-distance exchange or a packet data exchange. On the next lower hierarchical level there are subordinate units, for example line cards, which switch between the upper hierarchical level and the terminal stations of the lowest hierarchical level. Such line cards have, for example, connections to PCM highways.

When required, the subordinate units generate signalling information, that is to say control information between the terminal station and the digital network, which is required for establishing connections for, for example, speech or communication data signals. One distinguishes, on the one hand, circuit-switched data, where switching is from one terminal station to another terminal station for a certain time. This possibility is selected for high-priority speech transmission, but is often unprofitable for data transmission, since there is poor utilisation of the available connection lines. One distinguishes, on the other hand, the packet-switched data typical of data switching, where a network node is used for temporarily storing the data in order to find a most favourable transmission path through the network from one terminal station to another terminal station. The network lines are required here only for transmission.

The ISDN system (Integrated Services Digital Network) offers one possibility of combining circuitswitched and packet-switched data. This system can connect terminal stations to exchanges, in order to access communication services. The ISDN basic access offers two speech channels each with 64 kbit/s and one data channel with 16 kbit/s transmission capacity. In the ISDN system, communication services are accessed on the basis of the use of certain protocols which are defined in the CCITT recommendations. These protocols are exchanged via the data channel, the D-channel, via which it is also possible to transmit signalling data for establishing connections for the circuit-switched Bchannels for the user data or speech transmission.

The multiple use of the D-channel may result in the traffic volume in the D-channel being variable by several orders of magnitude. In the prior published publication Randy Kun: A VLSI APPROACH TO SUPPORTING LAPD IN AN ISDN EXCHANGE TERMINATION, BNR, IEEE, pages 760-765, it is stated in this respect that the fluctuations in the traffic volume of the D-channel result from the fact that there is a different number of terminal stations, each of which supports a different number of applications, which in turn have their own traffic characteristics. It is further stated that, in an ISDN system, the data processing of the D-channel is expensive in an exchange using commercially available arrangements, since the latter do not all conform to ISDN requirements. The arrangements are designed to support a small number of high-speed channels, whereas packet switching must cost-effectively support a large number of channels with a low signalling rate. The acceptancy of packet switching in the ISDN has therefore hitherto been doubtful.

Pig. 1 shows a typical architecture of a switching system for the handling of packet data. Terminal stations Eii are connected via terminal station lines DC to subordinate units LCi, which in turn are connected via packet data lines PD to a packet exchange PAD and to a central processing unit CPU as well as via control lines KL to the central processing unit.

In the ISDN, the subordinate units are formed, for example, by line cards, a schematic representation of which is shown in Fig. 2. The terminal station lines DC are connected on the line card to transmitting/receiving components S/E, of which only one is illustrated, for better clarity. Connected downstream of this component is a communications control component ICC and a peripherals control component PBC. The communications control component ICC has inter alia the task of processing the D-channel information and through-connecting the B-channels transparently in both directions. For this purpose, the communications control component ICC is connected to a local processor LCP of the subordinate unit, which may also perform a preprocessing of the signalling data. The interface IOM between the transmitting/receiving component S/E and the communications control component ICC is designed in the ISDN as a modular interface. The peripherals control component PBC connects the terminal station lines to the superordinate units. Besides speech, data and signal line control, it serves as a multiplexer or demultiplexer for the PCM highways PCMH.

Components for switching technology are known, for example, from B. MU Her: Kommunikationsbausteine fur die digitale Ubertragungstechnik (Communication components for digital transmission technology), Siemens Components 25 (1987), Issue 2, pages 65-69.

The subordinate unit, for example the line card, has the task of separating the B-channels and D-channels as early as possible. While the B-channels are connected in the PCM highways, the data packets of the D-channel are first unpacked on the subordinate unit, in order to check whether signalling information or a data packet is present and are then further processed or packed again as appropriate. In a packet data architecture according to Fig. 1, two categories have been distinguished hitherto in the prior art: 1. Systems with decentralised handling of signalling and packet data on the subordinate unit.

These architectures are suitable if relatively small traffic flows, that is to say signalling data with little packet data, occur. As the traffic flow for packet data increases, the system discovers its limits. Typically, a powerful processor of the subordinate unit can serve up to 16 terminal stations if only signalling data are present, but only 4 terminal stations if packet data are added. A representative of this architecture is the Digital Electronic Switching System of Siemens AG. The signalling and packet data must initially be temporarily stored on the subordinate unit before they are forwarded to the central processing unit and, in addition, separate control components are required for signalling and packet data in order to send and receive the data packets in programmable time slots. Preliminary work with respect to designing the subordinate unit to handle the maximum traffic volume is economically unjustifiable owing to the great outlay for the necessary memory capacity and management. 2. Systems with central packet handling.

In these systems, the packet data are switched via separate lines or PCM highways to powerful superordinate units PAD, for example to a central packet data exchange. The paket data are then no longer unpacked on the subordinate unit. The advantage of these systems lies in the possibility that a powerful subordinate unit is only necessary at one place in the system. The disadvantage is that permanent or semipermanent connections to this superordinate unit must be available for signalling and packet data. A separation of the very different types of data is only possible in the superordinate unit. Since temporary storage is necessary on the superordinate unit due to the signalling data, in this system the storage problem is merely transferred to the superordinate unit. Accordingly, separate control components for the signalling and packet data are required on the superordinate unit. An architecture of this kind is described in the Randy Kun publication cited and is used by several companies.

A system architecture is desirable where the advantages of both described systems can be utilised and the disadvantages eliminated.

In accordance with the subordinate unit described in Fig. 2, this means that the packet data must be separated at the IOM interface even before the communications control component ICC and that a second communications control component is necessary which must be arranged in the region of the superordinate unit, since the packet data are to be available centrally in the system. For this, however, innumerable lines are required and the synchronised pulse frame usually used for the transmission is poorly utilised. Moreover, a concentration of the packet data between the IOM interface and the second communications control component ICC is not possible without problems. Although the direction from the terminal station to the superordinate unit does not present any major problems, the reverse direction does. In the subordinate unit, it must be possible to separate the signalling and packet data in the direction of the superordinate unit from one another and to switch them in the direction of the terminal station on the same data channel. A collision occurring in the direction of the terminal station between the two data types must be resolved without loss of data.

A method for resolving collisions is described in European Patent Application 0,175,095. It is based on the fact that, by listening in on the data line, the senders of data detect a collision even during the transmitting operation, and, when the transmitted data are corrupted, perform exactly synchronised termination of the transmitting operation. Consequently, however, no time stage and no concentration or switching function can be introduced between the senders and receivers of data. Besides the internal wiring outlay comparable to a central architecture, this method thus leads to a poor utilisation of the internal system connecting lines.

The object of the invention is, with a method and an arrangement of the type mentioned in the introduction, to state a possibility of decentralised handling and preprocessing of signalling data on the subordinate unit and a possibility for handling the packet data in a superordinate unit. The further object of the invention is to design the method and the arrangement to be modular, so. that they can be introduced, where required, into the switching system and, depending on the traffic flow, be adjusted for packet data.

This object is achieved in a method of the type mentioned in the introduction according to the invention by the features of the characterising part of Patent Claim 1. The object is further achieved in an arrangement of the type mentioned in the introduction according to the invention by the features of the characterising part of Patent Claim 8.

The invention confers the advantage that expensive preliminary work on the subordinate unit is not necessary. It also has the advantage that the signalling and packet data can be processed completely differently in accordance with their character since, due to the early separation of the two data types, the signalling data with high priority can be processed very quickly, while the packet data with a lower priority can wait longer until an optimum transmission path is found. Owing to its modularity, the switching system can always be adjusted to the traffic flow of packet data. By implementation in integrated components, the invention can be assisted in such a manner that a user of these integrated components notices nothing of collisions occurring and how they are resolved. The invention also resolves a collision if the sources of the data to be switched are not sending simultaneously or in exact synchronisation.

Further refinements of the inventive idea are characterised in the subclaims.

The invention will be decribed below in greater detail with reference to the exemplary embodiments illustrated in the figures of the drawing. The same elements are denoted by the same reference symbols in the drawing, in which: Fig. 1 shows the already described structure in principle of a digital switching system and Fig. 2 shows a likewise already described known exemplary embodiment of a subordinate unit for ISDN, Fig. 3 shows a schematic diagram of an arrangement according to the invention for carrying out the method according to the invention, Fig. 4 to Fig. 7 show exemplary embodiments of arrangements according to the invention for carrying out the method according to the invention which differ with respect to the transmission paths for packet data between the subordinate and the superordinate unit, and Fig. 8 shows an exemplary embodiment of an implementation of the arrangement according to the invention in an integrated component.

In accordance with Fig. 3, a data control component DEC acting as an intelligent switch is provided on the subordinate unit LC for each terminal station. This control component DEC can separate signalling and packet data in the direction of the superordinate unit PAD on the subordinate unit LC and can operate the data flowing in the other direction to the terminal station on the same data channel of a terminal station line DC. In doing so, the packet data are transmitted via a data line DL to the superordinate unit, which likewise contains a data control component DEC which is connected to a central processing unit CPU. For preprocessing the signalling data on the subordinate unit LC, the data control component DEC of this unit is connected to a local processor LCP. The local processor LCP is connected via a control line KL to a group control facility GC, to which various subordinate units LCi are connected. For better clarity, only one subordinate unit LC is drawn in Fig. 3. In the arrangement for carrying out the method according to the invention described in Fig. 3, one data control component is required for each subordinate and superordinate unit.

With the aid of the intelligent switch, the data control components DEC on the subordinate unit separate the signalling and packet data. Signalling or packet data transmitted from a terminal station E are identified according to the invention by means of a packet address and are subsequently separated. The signalling data are passed on to the local processor LCP and can be preprocessed there. Packet data are passed on to the superordinate unit PAD and can be multiplexed, for example, in 16 kbit/s time slots on PCM highways.

In the reverse direction, the method according to the invention provides that a monitoring facility arranged on the data control component DEC monitors the data channel of a terminal station line DC for packet data. Packet data transmitted from a superordinate unit PAD and arriving at the subordinate unit LC are initially temporarily stored, if appropriate after demultiplexing. A register which can be maintained with a minimum bit width of 2 bits is provided as a temporary store. Following the temporary storage, the packet data are switched to the data channel of the terminal station line DC. With the aid of the monitoring facility, the local processor LCP serving as the source for the signalling data, the signalling processor, can monitor the data channel for the packet data and detect the free or seized state. As long as a state of the data channel free of packet data is determined, signalling data can be transmitted as required to the terminal station in the data channel with the aid of the signalling processor. Simultaneously, in this case, a control signal is transmitted to the superordinate unit PAD indicating to this unit that the data channel is seized. The same path as for transmitting the packet data can be used for transmitting this control information. The superordinate unit is then informed of the seizure of the data channel.

♦ A collision of signalling and packet data occurs in the case when the data channel is seized with signalling data, but the control signal for indicating the siezed state arrives at the source for packet data, that is to say at the superordinate unit PAD, when this unit has already begun transmitting the packet data. This temporal delay can, for example, arise as a result of a time-division multiplexing function for packet data. In this case, the superordinate unit PAD halts the transmitting operation after arrival of the control signal and begins the transmitting operation from the beginning when the control signal signals a free data channel again. The already transmitted part of the packet data is scrapped on this subordinate unit LC. A collision of this kind is resolved, therefore, in that the signalling processor can transmit the signalling data with a higher priority to the terminal station. According to the invention, the collision problem is also solved with the described method when the sources for the data channel, that is to say the superordinate unit PAD and the local signalling processor LCP do not transmit simultaneously or in exact synchronisation. A concentration of the packet data on PCM highways or special lines is possible. Preferably, therefore, the packet data are transmitted in multiplex/demultiplex mode.

The control component DEC, which performs the protocol handling for the signalling data on the subordinate unit, must in addition contain the following function blocks for carrying out the method according to the invention: j An output and an input for the packet data, an output for the control signal (data channel seized/ free), a programming facility for the programming of time slots for these inputs and outputs, a register for temporarily storing the packet data, a monitoring facility which monitors the state (free or seized) of the data channel for the packet data and a logic facility which allocates the data channel. The outputs are preferably bus-capable and are thus provided with opendrain stages and/or tristate outputs with associated control signals. Fig. 8 shows two exemplary embodiments of data control components DEC having the corresponding additional inputs and outputs and having the control outputs for tristate amplifiers TS. The open-drain stages have the effect that a logical zero level from the bus is achieved. The additional function blocks may be preferably implemented in an integrated component.

A data control component DEC of this kind is in a position to switch either the packet data or the signalling data on the data channel to the terminal station and to issue a control signal regarding the state of the data channel to the superordinate unit.

In accordance with Figs. 4 to 7, exemplary embodiments are illustrated which differ according to the transmission paths for packet data between the subordinate and superordinate units.

The architecture illustrated in Fig. 4 is characterised in that the packet data are transferred with the aid of a peripherals control component PBC via existing PCM highways PCMH to the superordinate unit. The information exchanged internally on the subordinate unit between the transmitting/receiving components S/Ei and the peripherals control component PBC are monitored by corresponding data control components DECi. In the exemplary embodiment, the internal system connection is established and cleared for packet data as with circuitswitched channels. This leads to the optimum utilisation of the internal channel wiring of the switching system and the superordinate unit PAD. A concentration of the packet data is possible. The data control components DECi handle the signalling data in both directions and switch through the packet data in the direction of the superordinate unit without temporary storage. In the direction of the terminal station, the collision between signalling data and packet data is monitored and resolved according to the invention. In this case, a minimum temporary store with a bit width of less than 2 bits is necessary for packet data.

Since the packet data are transferred via the existing internal wiring, when this architecture in accordance with Fig. 4 is used it is a simple matter to introduce packet switching functions into existing switching systems without having to change the backplane wiring. When the capacity on the internal system PCM highways PCMH becomes a bottleneck as a result of the additional transmission of packet data, an alternative architecture with a separate line for transmitting packet data can be selected in accordance with the exemplary embodiments below. In the exemplary embodiments below, the packet data are also switched, for example, in timedivision multiplexing to these separate lines.

In accordance with the exemplary embodiment of Fig. 5, no switching function for packet data is employed between the subordinate and the superordinate unit. The user data are forwarded and received via a peripherals control component PBC via PCM highways PCMH. From the subordinate unit LCi, the packet data reach the super25 ordinate unit PAD via data control components DECi and packet data lines PDH and vice versa. The variant according to Fig. 5 is suitable if no concentration of data is provided, that is to say when a data control component is available for each subscriber in the super30 ordinate unit.

If one considers the statistical traffic flows of packet data, it can be established that in the case of an integration over a large number of terminal stations, a concentration of packet data and hence a cost improvement is possible. Depending on the degree of concentration, two to four terminal stations can be connected to one data control component. In accordance with Fig. 6, in each case four terminal stations are associated with one data control component DEC. Known time coupling stages permit the switching of 64 kbit/s channels. Not all available data control components DECi can be switched here to each terminal station. Such a possibility is, however, provided by the exemplary embodiment according to Fig. 7.

In accordance with Fig. 7, peripherals control components PBCi are employed as a time stage, permitting an optimum utilisation of the available data control components DECi. Since a peripherals control component PBC can also switch 16 kbit/s channels in ISDN, in the exemplary embodiment according to Fig. 7 unrestricted switching functions between packet data channels and data control components DECi are possible.

In all three exemplary embodiments according to Figs. 5 to 7, the same subordinate units LC are employed. In contrast to the subordinate unit employed in Fig. 4, according to Figs. 5 to 7 the packet data are switched directly by the data control component DEC to the lines of the backplane.

Claims (15)

1. Patent Claims

1. Data transmission method for a digital switching system, which is organised hierarchically on at least three levels which comprise terminal stations, subor5 dinate and superordinate units, and in which signalling data and packet data can be switched bidirectionally via data channels, characterised in that the subordinate units (LCi) separate signalling data and packet data and in that a collision of data is prevented by the following 10 method steps: a) a monitoring unit of a subordinate unit monitors the data channel of a terminal station line (DC); b) packet data transmitted from a superordinate unit (PAD) and arriving at the subordinate unit (LCi) are 15 temporarily stored and subsequently switched on the data channel of the terminal station line (DC); c) when a state of the data channel free of packet data is established, if appropriate, signalling data are transmitted to the terminal station (E) via the data 20 channel and d) simultaneously a control signal indicating seizure of the data channel is transmitted to the superordinate unit (PAD); e) if the control signal arrives at the superordinate 25 unit (PAD) after transmission of packet data has begun, then the transmitting operation is halted and f) the already transmitted packet data are scrapped on the subordinate unit (LCi); g) when a free state of the data channel is established 30 again, the transmitting operation of the superordinate unit (PAD) starts again from the beginning.

2. Method according to Claim 1, characterised in that signalling data or packet data transmitted from a terminal station (E) are identified by means of an 35 address and are subsequently separated, and in that these signalling data are passed on to a local processor (LCP) and the packet data are passed on to the superordinate unit (PAD).

3. Method according to Claim 1 or 2, characterised in that the control signal is transmitted on the same line path as packet data to the superordinate unit (PAD) .

4. Method according to any one of Claims 1 to 3, characterised in that the subordinate unit (LCi) transmits packet data in multiplexing mode to the superordinate unit (PAD) and works in demultiplexing mode in the reverse transmission direction.

5. Method according to any one of Claims 1 to 4, characterised in that the packet data are concentrated in the transmitting mode between the subordinate (LCi) and superordinate units (PAD).

6. Method according to any one of Claims 1 to 5, characterised in that the packet data transmitted from the superordinate (PAD) to the subordinate unit (LCi) are temporarily stored for 2 bit/s time slots.

7. Method according to any one of Claims 1 to 6, characterised in that the bidirectional data transmission between subordinate and superordinate units (LCi, PAD) is carried out in pulse code modulation (PCM).

8. Arrangement for carrying out a data transmission method for a digital switching system, which is organised hierarchically on at least three levels which comprise terminal stations as well as subordinate and superordinate units, and in which signalling data and packet data can be switched bidirectionally via data channels, characterised in that the subordinate unit contains a data control facility (DEC) with a monitoring facility for monitoring the data channel for packet data, a logic facility for allocating a data channel, a register for temporary storage, an input (DATA IN) and an output (DATA OUT) for packet data, an output (C-DATA) for the control signal and with a programming facility for the programming of time slots for these inputs and outputs.

9. Arrangement according to Claim 8, characterised in that the outputs (DATA OUT, C-DATA) contain open-drain stages and/or form tristate outputs with additional control outputs (control).

10. Arrangement according to Claim 8 or 9, characterised in that the register is 2 bits wide and the programming facility is provided for the programming of • 2 bit/s time slots. \ 5

11. Arrangement according to any one of Claims 8 to γ 10, characterised in that the data control facility (DEC) is also correspondingly present in the superordinate unit (PAD).

12. Arrangement according to any one of Claims 8 to 10 11, characterised in that the data control facility (DEC) can be inserted in a modular fashion.

13. A data transmission method according to claim 1, substantially as hereinbefore described.

14. An arrangement according to claim 8, substantially as

15. Hereinbefore described with reference to Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7 and Fig. 8 of the accompanying drawings.