IE60529B1 - A method of fabricating Schottky diodes - Google Patents

A method of fabricating Schottky diodes

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Publication number
IE60529B1
IE60529B1 IE241987A IE241987A IE60529B1 IE 60529 B1 IE60529 B1 IE 60529B1 IE 241987 A IE241987 A IE 241987A IE 241987 A IE241987 A IE 241987A IE 60529 B1 IE60529 B1 IE 60529B1
Authority
IE
Ireland
Prior art keywords
wafer
approximately
etching
layer
baking
Prior art date
Application number
IE241987A
Other versions
IE872419L (en
Original Assignee
Millimetre Wave Technology Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Millimetre Wave Technology Ltd filed Critical Millimetre Wave Technology Ltd
Priority to IE241987A priority Critical patent/IE60529B1/en
Priority to GB8722287A priority patent/GB2209868B/en
Priority to BE8701126A priority patent/BE1000030A6/en
Publication of IE872419L publication Critical patent/IE872419L/en
Publication of IE60529B1 publication Critical patent/IE60529B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • H01L29/66204—Diodes
    • H01L29/66212—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A process for fabricating a Schottky diode 1 comprises the steps of first cleaning a wafer comprising a semiconductor substrate such as a GaAs substrate 2 having an epitaxal layer 3 on one side. Silicon dioxide is then coated over the epitaxal layer 3 by a sputtering technique. The wafers are then scribed to a desired size, which is typically 5 x 5 mm. The surfaces of the wafer are then ground to approximately 90 mm. The other side of the wafer is then cleaned and an ohmic contact surface 4 is electroplated on. The contact surface is then alloyed. To apply the metal the anode surface is first cleaned and positive resist is applied. The anode surface is then masked and windows are etched out of the silicon dioxide layer. The windows are then continued into the water by etching out the GaAs layer. The resist is then removed and the anode surface is anodized before electroplating on the metal which is typically platinum followed by gold.

Description

The invention relates to Schottky diodes and in particular to a method of fabricating such diodes, diodes when made by the method and equipment such as waveguide mixers and multipliers incorporating such diodes.
S A Schottky diode is a rectifying diode formed from a junction between a metal and a semi-conductor. The energy gap and doping level of th® semi-conductor are such that minority carriers in the semi-conductor do not contribute significantly to the current flowing in the diode. Thus, such diodes have fast switching speeds and there is practically no reverse current swing when the diode is reversed biased.
According to the invention there is provided a method of fabricating a Schottky diode from a wafer comprising a semi-conductor substrate having an epi-taxial layer on one side, the method, comprising th® steps ofscoating the epi-taxial layer with silicon dioxide; scribing the wafer into a desired size; forming an ohmic contact surface on the other side of -2the substrate; applying a positive resist to the anode surface of the wafer; masking the anode surface, the mask having an array of 5 openings; etching the silicon dioxide layer through the openings to form windows; etching the epi-taxial layer through the windows; removing the positive resist, and electroplating the anode windows with metal.
In one embodiment of the invention the process includes the step, prior to electroplating of anodizing the anode surface. Preferably the anode surface is anodized with an anodizing solution comprising tartaric acid mixed with propylene glycol and using a platinum electrode.
In a particular preferred embodiment of the invention the masking comprises the steps ofscleaning and baking the wafer; priming the oxide surface by dropping a primer such as -3hexamethyldisilasane onto the surface and spinning the wafer; applying a photo resist to the wafer and iaanediately spinning the wafer; conditioning the wafer by baking; exposing the front, side edges and corner of the wafer to light; exposing the back surface of the wafer to light; developing the wafer to counteract edge and back surface unevenness; exposing the wafer to a positive resist mask, and hardening the resist mask.
Preferably the primer is allowed to rest on the surface for a minimum of 10 seconds following which the wafer is spun for approximately 30 seconds at approximately 5000 r -p.mPreferably the wafer is spun after applying the photo resist at a speed of approximately 5000 r.p.m. for approximately 30 seconds. -4ϊη one embodiment of the invention the wafer is conditioned by hardening with UV light for 30 minutes followed by baking at approximately Ι50θθ for approximately 20 minutes, baking at approximately 180®C for 20 minutes, followed by baking at approximately 210®c for approximately 20 minutes.
Preferably etching steps are carried out in an etching chamber which is previously passivated to etching conditions .
In one case a radio frequency plasma formed of Argan and CKF3 gases is set up to achieve a desired etch depth based on an etching rate of 474 +/- 15 A/min for silicon dioxide.
In another case a plasma is set up to achieve a desired etch depth based on an etching rate of 22.4 +/- 2.0 A/min for GaAs.
Preferably the epitaxal layer is of GaAs.
Usually the metal electroplated on is platinum followed by gold.
The invention also provides a Schottky diode whenever made by the method of the invention as well as equipment such as a waveguide mixer» a multiplier, a high frequency -5receiver and a corner reflector mixer incorporating a diode according to the invention.
The invention will be more clearly understood from the following description thereof given by way of example only with reference to the accompanying drawings in whichsFig. 1 is a diagrammatic representation of the steps for fabricating a Schottky diode in a method according to the invention.
Fig. 2 is a cross-sectional view of a typical Schottky diode.
Fig. 3 is a block diagram of the front end of a high frequency receiver.
Fig. 4 is a cross-sectional view of a multiplier; Fig. 5 is an exploded view of a waveguide mixer, Fig. 6 is a perspective view of a corner reflector mixer, and Fig. 7 is a cross-sectional view through the corner reflector mixer of Fig. 7.
Referring to the drawings and initially to Fig. 1 there is -6illustrated a process fox' fabricating a Schottky diode according to the invention. The process includes several steps which are identified in Fig. 1 by reference numerals from 1 to 15. Briefly, a wafer comprising a semi5 conductor substrate such as a GaAs substrate having an epi-taxial layer on one side is first cleaned. Silicon dioxide is then coated over the epi-taxial layer by a sputtering technique. The wafers are then scribed to a desired size, which is typically 5x5 mm. The surfaces of the wafer are then ground to approximately 90 mm. The other side of the wafer is then cleaned and an ohmic contact surface is electroplated on. The contact surface is then alloyed. To apply the metal the anode surface is first cleaned and positive resist is applied. The anod© surface is then masked and windows are etched out of the silicon dioxide layer. The windows are then continued into the wafer by etching out the GaAs layer. The resist is then removed and the anode surface is anodised before electroplating on th© metal which is typically platinum followed by gold. The wafers are then tested, scribed, soldered and tested again.
Each of these process steps will now be described in mors detail.
Step I Cleaening The wafer is first rinsed and scrubbed in de-ionized water -7and then dried in an oven. The wafers are then boiled and scrubbed in trichloroethylene and methyl alcohol - The surface of the epi-taxial layer is then etched using hydrochloric acid which is rinsed with de-ionized water and then dried in an oven.
Step 2 Silicon dioxide coating The epi-taxial layer is coated with silicon dioxide using a sputtering technique.
Step 3 Scribing The substrate is scribed into 5mm x 5ran wafers.
Step 4 Grinding The wafers are first waxed with, paraffin wax and then ground to a surface roughness of 90 micro meters in a number of steps using grit 600. Th® wafers ar® then rinsed in de-ionized water, boiled in trichloroethylene and dried.
Step 5 Cleaning qhaic contact surface The wafers are first rinsed in de-ionized water and then dried and subsequently boiled in trichloroethylene and methyl alcohol. They are then etched with hydrochloric -8acid for 60 secs and rinsed quickly with de-ionised water, dried in an oven and transferred to the plating bath as quickly as possible.
S-fcep 6 Qbwic contact, surface electroplating Electroplating is carried out by first filling an electroplating container with a fresh solution of Autronex (SEL-REX Corporation) and adjusting the pH 3,2 to 3,8. A D.C, supply and ammeter is then hooked up and the ohmic contact surface is plated in a solution of Puragold (Sel10 Rex Corporation) for 2 mins at 3 mA per 25 mm2 wafer. The container is then filled with fresh SnSii solution and the pH checked to lie between 0.2 and 0.5. The wafers are then rinsed in de-ionized water and dried and plated in SnSfi for 80 seconds at the same current. Plating is then carried out in Autronex for 2 mins, again using the same current after which the wafers are rinsed in de-ionized water» boiled and dried.
Step 7 Ofeaic contact, surface alloying The ohmic contact surface is alloyed by pre-heating a furnace to 400θΰ at a hydrogen to nitrogen ratio of 2080 and at a rate of 50 cc per min. The wafers are left in the furnace for 4 mins» to alloy. -9Step _3 Cleaning anode surface The anode surface is cleaned by boiling successively in de-ionized water, trichloroethylene, isopropyl alcohol, acetone and xylene and then baked at 200θ€ for 60 mins.
Step 9_Applying positive resist Positive resist such as Kodak 747 (Kodak is a registered Trade Mark) is applied to the wafer which is then spun at 6000 r.p.m. for 30 secs. The resist is then exposed for 4 secs followed by a further 3 secs and developed for 60 secs, rinsed for 30 secs and baked for 30 mins at 120°C.
Step 10-, Masking anode surface aad etching opt silicon dioxide layer A. Masklag A suitable resist mask with high selectivity is Shipley 2400 but this must be u*V hardened for 30 minutes. The lithography used is to boil and swab the wafers in trichloroethylene, de-ionised water and isopropylene. The sample is then outgased for 30 mins, at 200θ0. The oxide surface is then primed by dropping a primer such as hexamethyldisilasane onto the anode surface and allowing the primer to rest on the surface for a minimum of 10 secs following which the wafer is spun for approximately 30 -10secs at approximately 5000 r.p.m. The wafer is then baked for 25 mins at 95®c and the front, side edges and corners are exposed for 60 secs while covering the centre of the wafer with a UV opaque material such as that available under the name Rubylith. The back of the wafer is then exposed for 60 secs.
The mask is then developed for 50 secs using Shipley 2401 developer at a ratio of developer to de-ionised water of ls4 to avoid edge and back unevenness causing poor mask contact.
The mask is then exposed for 50 secs and developed for 10 secs in Shipley 2401 diluted 1-4 with de-ionised water.
The mask is then hardened using UV light fox- 30 mins followed by baking for 20 mins at 150θ0„ baking for 20 mins at 180®C and baking for a further 20 mins at 210°c to harden the resist mask.
B- Etching Etching is carried out in an etching chamber which is first passivated by coating the walls and other surfaces of the etching chamber with etch products and absorbed gas so that a steady state is attainable quickly.
The etching chamber is passivated with only a silicon wafer inside by first setting up a pre-mixed -11Trifluoromethane/Argon 50:50 by volume gas line to the chamber, introducing the gas into the chamber while cooling to achieve a chamber pressure of 81/m/Torr, a base electrode temperature of 11®C and a gas mass flow of 40sccm.
This coats the etching chamber with etch products and absorbed gas so that a steady state is attained quickly. The etching chamber is then opened and a GaAs wafer is loaded onto the Silicon chip in the centre of the base electrode. The etch chamber is then closed. The radio frequency plasma of Trifluoromethane and Argon gases set up from the passivation step is used and the operating parameters from the etch are the same as for passivation except that the time is set to achieve a desired etch depth. For silicon dioxide etching the desired etch depth is set up bearing in mind the average etch rate of 474 +/l5A/min for SiOp etching. Wen etching is complete the nitrogen regulator pressure is reduced to zero to reduce vent inflow and prevent the wafer from flying off the electrode on venting of the chamber. The chamber is then opened and the wafer is removed.
Using this step perfect anisotrophy is achieved. Further, no mask undercutting is observed and excellent mask selectivity is achieved. The anode surface has excellent smooth etch surface morphology. -12Step 11 .Mask anode swrface and etch out GaAs layer This step follows exactly Step 10 except that the etching time is set to achieve a desired etch step bearing in mind the average etching rate of 22.4 + /- 2»0A/min characterised for GaAs etching.
Again perfect anisotrophy, no mask undercutting, excellent mask selectivity and smooth etch surface morphology are just some of the advantages obtained by using this method.
Step 12 Resist removal The photo resist is removed by placing the wafer in the evacuation chamber, evacuating the chamber by bleeding oxygen at approximately 2T,12 - 15 mm flow and plasma etching at 75 watts for 20 mins. The process is continued until all of th© photo resist is removed.
Step 13_&jR<»aigincr the anode starface The anode surface is anodised by an anodising solution comprising 3 grms of tartaric acid in 100 mis of deionised water to which ammonia is added to adjust the pH to approximately 6.0 followed by mixing in propylene glycol to a ratio of Is2. The solution is placed in a pyrex beaker with a magnetic stirrer and using a platinum electrode, the surface is anodised at 1 V per 1.5A Ga/As -13to be removed or 22 A oxide produced for 10 mins. The surface is then rinsed in cold de-ionized water.
Step 14_Electroplating Using conventional electroplating techniques, the windows formed in the wafers are first applied with platinum and then with gold until the anode holes are filled. The diodes are then rinsed in de-ionized water and boiled for mins in de-ionized water.
Step 15 Testiisq Scribing, soldering and testing techniques are then used to provide tested Schottky diodes chips of desired size and configuration.
A typical cross-sectional view of a contacted Schottky harrier diode made by the method described above is illustrated in Fig, 2. The diode comprises a GaAs substrate 2 having an active GaAs epitaxal layer 3 on one side and an ohmic contact layer 4 on the other face. The epitaxal layer 3 is coated with a layer 5 of fine silicon dioxide in which a plurality of windows δ are formed and into which windows is introduced the gold/platinum anode metal. The diode is usually contacted by a contacting whisker 10. -14Referring to Fig. 3 there is illustrated a typical front end configuration of a high frequency receiver including a waveguide mixer 20 and a multiplier 22 both of which incorporate Schottky diodes made by the method of the invention. The waveguide mixer 20 receives radio frequency (RF) signals of 400 G Hz through a diplexer 23, and is connected at its output to a matching network and bias transformer 24 which feeds data processing circuits 26 and an automatic noise temperature meter 27 via an intermediate frequency (IF) matching circuit 25. A power supply 28 feeds the bias transformer 24.
The multiplier 22 is illustrated in more detail in Fig. 4 from which the position of the Schottky diodes and whiskers will be readily apparent. The multiplier 22 comprises an output guide 30 with a Schottky diode, having a whisker contact 29, and a low-pass filter 31. A contacting back short 32 and a short for series stub 33 are also provided. An SMA bias connector 34 is connected to a quartz capacitor 35, which is, in turn, connected to the low-pass filter 31.
Fig. 5 is an exploded view of the waveguide mixer 20 in which a Schottky diode 39 is connected to a radio frequency filter 40. The waveguide mixer 20 further comprises a suspended substrate channel 41 for the filter 40, a diode post 42 and a reduced height waveguide hole 43 for the diode post 42. An intermediate frequency output -15connector 44 and a DC bias input connector 45 are also provided.
Figs. 6 and 7 illustrate a corner reflector mixer 50 having a Schottky diode chip 51 and Whisker antenna 52.
The whisker antenna 52 is connected to an intermediate frequency output connector 53 and the diode 51 is mounted in a ground plane 54 above a protection cap 55» Α 90θ corner reflector 56 is mounted intermediate the ground plane 54 and the connector 53.
Schottky diodes made by the method of the invention may ba used in many similar items.

Claims (18)

1. GL&ZMS
1. Ά method of fabricating a Schottky diode from a wafer comprising a semi-conductor substrate having an epi-taxial layer on one side, the method comprising the steps of:5 coating the epi-taxial layer with silicon dioxide: scribing the wafer into a desired size: forming an ohmic contact surface on the other side of the substrate; applying a positive resist to the anode surface of the 10 wafer; masking the anode surface, the mask having an array of openings; etching the silicon dioxide layer through the openings to form windows; 15 etching the epi-taxial layer thx'ough the windows; removing the positive resist, and electroplating the anode windows with metal. A method as claimed in Claim 1 wherein the process =17includes the step, prior to electroplating, of anodizing the anode surface.
2. 3. A method as claimed in Claim 2 wherein the anode surface is anodized with an anodising solution comprising 5 tartaric acid mixed with propylene glycol and using a platinum electrode.
3. 4. A method as claimed in any preceding claim in Which the masking comprises the steps of;cleaning and baking the wafer; 10 priming the oxide surface by dropping a primer such as hexamethyldisilazane onto the surface and spinning th® wafer; applying a photo resist to the wafer and ixamediately spinning the wafer; 15 conditioning the wafer by baking; exposing the front, side edges and corner of the wafer to light; exposing the back surface of the wafer to light; developing the wafer to counteract edge and back -18surface unevenness; exposing the wafer to a positive resist mask, and hardening the resist mask.
4. 5. A method as claimed in Claim 4 in which after the primer is applied the primer is allowed to rest on the surface for a minimum of 10 seconds following which the wafer is spun for approximately 30 seconds at approximately 5000 r.p.m.
5. 6- A method as claimed in Claim 4 or 5 in which the wafer is spun after the photo resist is applied at a speed of approximately 5000 r.p.m. for approximately 30 seconds»
6. 7» A method as claimed in any of Claims 4 to 6 in which the wafer is conditioned by hardening with UV light for 30 minutes followed by baking at approximately 150°C for approximately 20 minutes, baking at approximately 180θΰ for 20 minutes followed by baking at approximately 210®C for approximately 20 minutes»
7. 8. A method as claimed in any of Claims 1 to 7 in which the etching steps are carried out in an etching chamber which is previously passivated to etching conditions,
8. 9» A method as claimed in Claim 8 wherein a plasma is set up to achieve a desired etch depth based on an etching -19rate of 474 +/- 15 A/min for silicon dioxide.
9. 10. A method as claimed in Claim 9 in which the plasma is set up to achieve a desired etch depth based on an etching rate of 22.4 +/- 2.0 A/min for GaAs. 5
10. 11. A method as claimed in any preceding claim wherein the epitaxal layer is of GaAs.
11. 12. A method as claimed in any preceding claim wherein the metal which is electroplated is platinum followed by gold.
12. 13. A method substantially as hereinbefore described. 10
13. 14. A Schottky diode whenever made by the method as claimed in any of Claims 1 to 13.
14. 15. A waveguide mixer including at least one diode as claimed in Claim 14.
15.
16. A multiplier including at least one diode as claimed 15 in Claim 14.
17. A high frequency receiver including a waveguide mixer as claimed in Claim 15 and a multiplier as claimed in Claim 16.
18. A corner reflector mixer including a diode as claimed n Claim
IE241987A 1987-09-10 1987-09-10 A method of fabricating Schottky diodes IE60529B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IE241987A IE60529B1 (en) 1987-09-10 1987-09-10 A method of fabricating Schottky diodes
GB8722287A GB2209868B (en) 1987-09-10 1987-09-22 Method of fabricating schottky diodes
BE8701126A BE1000030A6 (en) 1987-09-10 1987-10-02 Diodes schottky, their production and use.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IE241987A IE60529B1 (en) 1987-09-10 1987-09-10 A method of fabricating Schottky diodes

Publications (2)

Publication Number Publication Date
IE872419L IE872419L (en) 1989-03-10
IE60529B1 true IE60529B1 (en) 1994-07-27

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IE241987A IE60529B1 (en) 1987-09-10 1987-09-10 A method of fabricating Schottky diodes

Country Status (3)

Country Link
BE (1) BE1000030A6 (en)
GB (1) GB2209868B (en)
IE (1) IE60529B1 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3360851A (en) * 1965-10-01 1968-01-02 Bell Telephone Labor Inc Small area semiconductor device

Also Published As

Publication number Publication date
BE1000030A6 (en) 1987-11-24
IE872419L (en) 1989-03-10
GB8722287D0 (en) 1987-10-28
GB2209868A (en) 1989-05-24
GB2209868B (en) 1990-08-29

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