IE44902B1 - Improvements in or relating to arrangements for restoring pulse trains of digital signals transmitted using positive-negative-stuffing - Google Patents

Abstract

At the receiving end of a time division multiplex system for plesiochronous signals, a digital signal (D12) and the associated uneven clock (T12) are restored in a pulse restoration device (1). In an elastic memory (7) connected downstream, a clock-corrected restored digital signal (D2) is formed with an associated even clock (T2). A phase comparator (14') serves as an aid which, depending on the occupancy level of the elastic memory (7), controls a gate circuit (18') via which different clocks of a central clock station (26) are selected.

Description

This invention relates to an arrangement for. restoring, at the receiving end of a transmission system, pulse trains of a plurality of digital signals which have been transmitted multiplexed in pulse frames by means of positive-negative-stuffing, the pulse frames containing, in respect of each digital signal, . an associated additional signal which consists of stuffing information and possibly information bits.

• Xt is known for such an arrangement to comprise in respect of each digital signal, a pulse restoration device which produces from the digital signal, the additional signal, and a pulse train derived from the digital signal a digital signal which has been restored following the stuffing and an associated non-uniform pulse train; a store which is supplied with the restored digital signal, the non-uniform pulse train, and. a substantially uniform pulse train and from which is read out a pulse train-corrected ' restored digital signal; a phase comparator which emits a control voltage? and a pulse generator which is controlled in frequency by the control voltage and produces the substantially uniform pulse train, which is also referred to as a read-out pulse train.

Such an arrangement is disclosed in the book Transmission Systems for Communications, revised fourth edition, December 1971, Bell Telephone Laboratories Incorporated, pages 616 to 618. In this arrangement quarts crystal oscillators serve as pulse generators.

The Technical Reports on Communications Technology, edition 42: 1972, PCM-Technik, published by the VDB-Verlag GmbH, Berlin· Charlottenburg, pages 245 to 256 further discloses an arrangement which, in place of each oscillator, employs a digital circuit to -24 4 9 Ο 3 produce the substantially uniform pulse train. The digital circuit produces a pulse train whose frequency, following a stuffing process, is ncreased or reduced. This is effected in that correcting elements, i.e. bit pulse train periods of modified duration, are provided. This known arrangement has the disadvantage that an e aborate circuit required for the production of the read-out pulse -.rain must be provided for each digital signal.

German Patent Specification No. 2 117 344 discloses a 10 device for deriving a timing pulse from a pulse sequence which possesses pulse gaps, whilst maintaining the average number of * pulses per time unit. However, this device is only suitable for a positive-stuffing process.

This invention seeks to provide an arrangement for restoring 15 pulse trains of a plurality of digital signals which have been '' transmitted multiplexed in pulse frames by means of positivenegative-stuffing, which involves a relatively low outlay.

According to this invention there is provided an arrangement for restoring, at the receiving end of a transmission system, ·> pulse trains of a plurality of digital signals which have been transmitted multiplexed in pulse frames by means of positivenegative-stuffing, the pulse frames containing, in respect of each digital signal, an associated additional signal which consists of stuffing information and possibly information bits, the arrangement comprising a pulse train generator which serves to produce a first pulse train, whose frequency corresponds to that'of a pulse train associated with each digital signal, and second, third, and fourth pulse trains which are such that in -3- each period of-the fourth.pulse train there occur n periods of the first pulse train, (n-l) periods of the second pulse train, and (n+1) periods of the third pulse train, vjhere n is an integer, and further comprising, in respect of each digital signal, a pulse restoration device which is responsive to the relevant digital : signal, the associated digital signal, and said pulse train associated with each digital signal to produce a restored digital signal and an associated non-uniform pulse train, a store which is responsive to the non-uniform pulse train to store digits of the restored digital signal and is responsive to a substantially ianiform pulse train to read out digits stored therein thereby to produce a puls.e-train-corrected restored digital signal, a phase comparator which is responsive to the degree of fullness of the store falling below a predetermined value or range of values to emit a first control signal and Is responsive to the degree of fullness of the store exceeding said predetermined value or range of values to emit a second control signal, and a gate circuit which is responsive to the pulse trains produced by the pulse train generator and the first and second control signals to emit the substantially uniform pulse train in such manner that in each complete period of the fourth pulse train the substantially uniform pulse train is constituted by the first pulse train in the absence of both the first and second control signals, by the second pulse train in response to the occurrence of the first control signal, and by the third pulse train in response to the Occurrence of the second control signal.

* The degree of fullness of a store is understood as the number of storage cells of the store which are occupied by stored -4449 0^ digits divided by the total number of storage cells of the store which can be occupied by stored digits.

’It is advantageous if n is an integral power of 2.

Preferably in respect of each digital signal the phase comparator is responsive to the degree of fullness of the store . falling below or exceeding the predetermined value by a given quantity to emit the first or second control signal respectively. When the digital signals are binary signals the given quantity is expediently % bit.

Preferably each store has eight one-bit storage cells and the period of the fourth pulse train is between l/6Af and l/3Af, where Af is the maximum deviation of the frequency of the original digital signal from the frequency of the digital signal in the main channel.

Advantageously in respect of each digital signal the phase ' comparator comprises a comparator and first and second stores and is arranged in each cycle of the read out of digits from the store to compare a number of a storage cell of the store into which storage is effected with a number of a storage cell of the store from which read-out is effected and in response to the results of this comparison to set the first store or the second store or neither of the first and second stores to a predetermined state. -.5The invention will be further understood from the following description by way o£ example with reference to the accompanying drawings, in which :Fig. 1 schematically illustrates a known arrangement for 5 restoring the pulse· train of a digital signal which has been transmitted multiplexed in pulse frames by means of positivenegative-stuffing; Figs. 2 and 3 illustrate respectively the extraction of a Stuffing bit from and the insertion of an additional information bit into the digital signal in the arrangement illustrated in Fig. 1? Fig. 4 schematically illustrates by way of example an arrangement in accordance with an embodiment of the invention, for restoring the pulse train of a digital signal which has been transmitted multiplexed in pulse frames by means of positive' negative stuffing; Fig. 5 illustrates as a function of time t pulse trains produced in operation of the arrangement illustrated in Fig. 4; Fig. 6 illustrates the compensation of a positive-stuffing 20 process in the arrangement illustrated in Fig. 4; and Figs. 7 to 9 schematically illustrate respectively a store, a phase comparator, and a gate circuit which are provided in the arrangement illustrated in Fig. 4.

Fig. 1 shows a known arrangement for restoring, at the 25 receiving end of a t.d.m. digital transmission system, a digital signal and the pulse train thereof. This arrangement comprises a pulse restoration device 1 having inputs 2, 3, and 4 respectively for a digital signal Dll of a stuffing channel, a digital -644Q0S signal DI of a main channel, and a timing signal Tl which is assigned to the digital signal DI and outputs 5 and 6 respectively for a'restored digital signal DI2 and a non-uniform pulse train T12 which is assigned to the restored digital signal D12; a store 7 having inputs 8 and 9 connected to the outputs 5 and 6 respectively, outputs 10 and 11 for the connection of a phase comparator, an output 12 for a pulse train-corrected restored digital signal D2, and an input 13 for a substantially uniform pulse train T2 which is assigned to the digital signal E2? a phase comparator 14 having inputs 15 and 16 connected to the store outputs 10 and 11 respectively and an output 17 for a control voltage U; a pulse train generator 18 having a control input 19 to which the control voltage U is supplied and an output 20 at whioh the pulse train T2 is produced; and an output 13' to which the pulse train T2 is supplied.

' The pulse restoration device 1 analyses the digital signal Dll, in the event of an item of positive-stuffing information removes one bit from the digital signal DI, and in the event of an item of negative-stuffing information inserts the information bit, transmitted' in the stuffing channel, into the digital signal DI. The pulse restoration device 1 feeds the store 7 with the restored digital signal D12 and the associated timing signal T12.

Fig. 2 illustrates as a function of time t the extraction of one stuffing bit S from the digital signal DI (positive25 stuffing). The associated timing pulse of the pulse train Tl is suppressed to form the timing signal T12, so that the stuffing bit is not entered into the store 7. Fig. 3 similarly illustrates the insertion of an information bit J into the digital . -7signal DI (negative-stuffing). In this case an additional timing pulse TJ is included.in the timing signal T12.

•The pulse restoration device 1 emits the restored digital signal D12, and the associated non-uniform pulse train T12, to the store 7 into which the signal DI2 is entered under the control of the pulse train T12. From the store the signal DI2 is readout as the signal D2 under the control of the substantially uniform pulse train T2. The phase comparator 14 emits the control voltage ϋ to the generator, this voltage being proportional to the degree of fullness of the store 7. The frequency of the pulse train T2 generated by the generator 18 is regulated by the control voltage U so that the degree of fullness of the store 7 is maintained substantially at a predetermined value of e.g. %. When, for example, one bit is entered into the store 7 the degree of fullness of the store 7 rises above this value, and as a result ' the frequency of the pulse train T2 is increased so that the degree of fullness of the store 7 returns to its predetermined value.

The digital signal D2 read out from the store 7 -thus 20 corresponds to the original data signal which in transmission has been multiplexed with other digital signals to form a digitalmultiplex signal.

Averaged over a long period of time, the pulse train T2 possesses the same frequency as the pulse train of the original digital signal. However, it exhibits a.jitter as a result of the compensation processes described above, the maximum value of the jitter being one bit.

Fig. 4 illustrates an arrangement, in accordance with an -84 4 9 0 2 embodiment of the invention which differs from the arrangement illustrated in Fig. 1 in that it includes a different phase comparator 14', a gate circuit 18' in place of the pulse train generator 18, and a pulse train generator 26. The phase comparator 14' has, in place of the output 17 of the phase comparator 14, outputs 17’ and 17 for control signals SI and S2 respectively. The pulse train device 18' is a gate circuit having an output 20' for the pulse train T2, inputs 19' and 21' for the control signals SI and S2, and inputs 22 to 25 respectively for pulse trains T20, T21, T22, and TU, which pulse trains are emitted, commonly for all the gate circuits 18' provided in respect of all the digital signals which are to be restored, by the pulse train generator 26 respectively at outputs 27 to 30 thereof. The phase comparator 14' can operate in analogue fashion, its outputs 17' and 17 being preceded by threshold value circuits, the control , signal SI or S2 being emitted whenever the degree of fullness of the store 7 respectively falls below or exceeds a predetermined value. However, the phase comparator 14' can alternatively operate in digital fashion.

The frequencies and phase states of the pulse trains produced by the pulse train generator 26 are selected to be such that in each period T of the pulse train TU, which is referred to as a switch-over pulse train, there occur n periods of the pulse train T20, (n-l) periods of the pulse train T21, and (n+1) periods of the pulse train T22, where n is a whole number. This is illu' strated in Fig. 5. The frequency f20 of the pulse train T20 is selected to be equal to the frequency fl of the pulse train Tl.

Fig. 6 illustrates the compensation of a positive-stuffing -9process. Xf no stuffing is being effected, the gate circuit 18' switches through the pulse train 120 to form the pulse train T2. Information is thus entered into and read out from the store 7 at the frequency fl, so that the degree of fullness of the store 7 does not change from the predetermined value. After a positivestuffing process, the degree of fullness falls below the predetermined value by 1 bit, so that the phase comparator 14' emits the digital control signal Sl=l to the gate circuit 18'. On the occurrence of the next pulse of the switch-over pulse train TO the gate circuit 18' switches through the pulse train T21 With the frequency f2l, in place of the pulse train T20, for one period 1 of the switch-over pulse train, lu. During this period, n bits are entered into the store 7 and (n-1) bits are read-out from the store 7, so that the degree of fullness returns to precisely the predetermined value.' The signal SI assumes the value zero as { soon as the degree of fullness of the store 7 differs from the predetermined value by less than a value ΔΧ. Xn a similar manner, following a negative-stuffing process, the control signal S2=l is produced and causes the pulse train T22 to be switched through in place of the pulse train 120 for one period of T of the switchover pulse train TU, so that again the predetermined degree of fullness of the store 7 is maintained.

The storage cell requirement of the store 7 is a minimum if a compensating process is initiated following each stuffing process; i.e. the phase comparator 14' must be designed to be such that the quantity ΔΧ by which the predetermined degree of fullness can be undershot exceeded before the signal Sl=l or S2=l is produced amounts to % bit. -1044902 The average frequency of the stuffing processes. is equal to the difference 0f between the pulse train frequencies of the origihal digital signal and the main channel. If, for example, the pulse train frequency of the original digital signal exceeds the pulse train frequency of the main channel by Af=X Hz, on average, stuffing must be effected every second. Since a period T of the switch-over pulse train TU is required to compensate a stuffing process, it is necessary that TK-l/if. In communications networks a plurality of transmission sections with digical-multiplexlO devices are often connected in series, so that a single digital signal can pass through a plurality of grouping and clearing processes and the intervals between two consecutive stuffing processes can fluctuate considerably, substantially exceeding or falling below the average spacing of 1/A.f. In order that the pulse train restoration facilities may operate satisfactorily even under these conditions, it is necessary for the period T of the switch-over pulse train TU to be selected to be less than l/&f and for the store 7 to contain an adequate reserve of storage positions. Advantageously T is from l/6Af to l/3A>f,Af being the maximum frequency difference, and the store 7 has eight storage cells.

In practice, a digital-multiplex-device for example groups 64 kbit/s signals to form one 2048 kbit/s signal. The bit rate of the main channel has a nominal value of 64 kbit/s, which can deviate by a factor of - 0.5 . 10 , and the bit rates of the 64 kbit/s signals can deviate from the nominal value by a factor of 4· «> —4 - 1 , 10 . The maximum difference between the pulse train frequencies is thus £>£ = 9.6 Hz. This means that in the most 11unfavourable situation a stuffing process.is required approximately every 100 ms.

'The frequency of the .pulse train Tl is fl = 64 kHz. If a value of 211 '= 2048 is selected for n, the switch-over pulse train TD has a frequency of 31.25 Hz and a period of T = 32 ms, and the maximum product T . Af is 0.31. During the compensation carried out in a stuffing process, the frequency of the, read-out pulse train increases or reduces by a factor of approximately 5 . 10-4.

If the store 7 has eight storage cells it is ensured that during th the compensation, which lasts for 32 ms, of a stuffing process it is possible to accommodate further stuffing processes.

Fig. 7 illustrates the form of a known store which can be used as the store 7 in the Arrangement illustrated in Fig. 4.

This store is constituted by CMOS modules and comprises two 4-bit counters 31 and 32 (module CD 14520), an addressable eight-bit t store 33 (module CD 4099), and a data selector 34 (module MC 14512).

The non-uniform pulse train T12 is conducted via the input 9 to the pulse train input CK of the counter 31, outputs QA, QB, and QCof the first three stages of which serve to address the addressable store 33 via its address inputs A0, Al, and A2 respectively. The bits of the digital signal DI2 are therefore cyclically entered into the storage cells Q0 to Q7 of the store via the input 8 and the data input D of the store 33. The read-out pulse train T2 present at the input 13 controls the counter 32, whose outputs QA, QB, and QC address the data selector via its address inputs A, B, and C respectively. With each pulse of the pulse train T2 one bit is read-out from the -124 4 9 0 2 addressable store 33 via one of the inputs XO to X7 and via the output X of the data selector 34, to the output 12. Xn the normal state, the store 7 is half full, and each bit which is entered into a storage cell is read-out after four pulses. If, for example, the addressable store 33 enters a bit into the storage cell QO, simultaneously the data selector 34 reads out one bit from the storage cell Q4. The store 7 is connected to the phase comparator 14' via outputs 35 to 40 and an input 41.

Fig. 8 illustrates one possible form of the phase comparator 10 14', in which once in each storage cycle of eight pulses of the pulse train T2 the write-in and read-out addresses are compared with one another and the result of the comparison is stored in two stores.

The phase comparator 14' illustrated in Fig. 8 consists of 15 an inverter 42, a NOR gate 43, a NAND gate 44, an address decoder (module CD 4028), a first store comprising NOR gates 48 and 49, and a second store comprising NOR gates 46 and 47.

A comparison is carried out when the counter 32 of the store 7 has the state QA = 0, QB = 0, and QC = 1, i.e. when the storage cell Q4 of the addressable store 33 is read-out. With this state of the counter 32, which is maintained for one period of the pulse train T2 the output of the gate 43 has the value one. In the middle of this period a narrow pulse of a pulse train T-Tor enables the gate 44, so that the input D of the address decoder 45 is supplied with the value zero. The pulse train T-Tor has the same pulse train frequency as the pulse traifl T2, i.e. 64 kHz, and a pulse width of 1 /s.

The address decoder 45 establishes the state of the -13counter. 31 at the instant of comparison, i.e. ΐ/hen the input D of the address decoder 45 has the value zero”. In consequence one of the outputs Q0 to Q7 of the address decoder 45 assumes the value one”.

When the store 7 is half full (i.e. degree of fullness = %), at the instant of the comparison, the output Q0 of the address decoder 45 assumes the value one11, and the stores which consist of the gates 46 to 49 are set so that SI = 0 and S2 = 0.

If the degree of fullness of the store falls below the predetermined value of k by more than % bit, one of the outputs Q5, Q6, and Q7 assumes the value one, and the stores are set so that SI = 1 arid S2 = 0. If the degree of fullness exceeds the predetermined value by more than % bit, one of the outputs Ql, Q2, and Q3 assumes the value one, and the stores are set so that SI = 0 and S2 = 1, If the output Q4 of the addressable store 45 assumes the value one, this indicates that the store 7 is in an overflow state, which can occur when the device is initially switched on or in the event of disturbances. In this situation the counter 31 is'set to zero via the'termlnal 41 and its input R. .

Fig. 9 illustrates one possible form of the gate circuit 18’s which consists of two JK flip-flops (bistable trigger stages) 54 and 55, which are constructed from CMOS modules CD 4027, NOR gates 56 to 59, and inverters 60 to 64 whioh can be dispensed with if the pulse trains TU, T20, T21, and T22 are available*in inverted form and if the pulse train T2 can be employed in inverted form The flip-flops 54 and 55 are supplied with the signals -1444-9 0 3 SI and S2 via the inputs 19' and 21' and with inverted signals SI and Si via-inputs 19 and 21, which inputs are connected to outputs 50 to 53 of the phase comparator 14' illustrated in Fig. 8. The flip-flops 54 and 55 are able to change their states only with the falling flanks of the switch-over pulse train TU. If the signals SI and S2 both have the value 0, the two flip-flops have states in which their values Q = 0. In this case the gates 57 and 58 are blocked and the gate 56 is enabled to switch through the pulse train T20 to form the pulse train T2. If the signal SI or S2 assumes the value one, with the next falling flank of the pulse train TU the flip-flop 54 or 55 respectively is switched to the state in which its value Q = l, so that the gate 56 is blocked and the gate 57 or 58 respectively is enabled to switch through the pulse train T21 or T22 respectively to form the pulse train T2.

Claims (7)

1. CLAIMS :•/1« An arrangement for restoring, at the receiving end of a transmission system, pulse trains of a plurality of digital signals which have been transmitted multiplexed in pulse frames . 5 by means of positive-negative-stuffing, the pulse frames containing, in respect of each digital signal, an associated additional signal which consists of stuffing information and possibly information bits, the arrangement comprising a pulse train generator which serves to produoe a first pulse train, whose frequency •10 /ccorresponds to that of a pulse train associated with each digital . signal, and second, third, and fourth pulse trains which are such that in each period Of the fourth pulse train there occurs n periods of the first pulse train, (h-l) periods of the second pulse train, and (n+1) periods of the third pulse train, where n 15 is an integer, and further comprising, in respect of each digital signal, a pulse restoration device which is responsive to the relevant digital signal, the associated digital signal, and said pulse train associated with each digital signal to produce a restored digital’ signal and an associated non-uniform pulse train, 20 a store which is responsive to the non-uniform pulse train to store digits of the restored digital signal and is responsive to a substantially uniform pulse train to read out digits stored therein thereby to produce a pulse-train-corrected restored ' -digital signal, a phase comparator which is responsive to the 25 degree of fullness of the store falling below a predetermined value or range of values to emit a first control signal and is responsive to the degree of fullness of the store exceeding said -164 4903 predetermined value or range of values to emit a second control signal, and a gate circuit which is responsive to the pulse trains produced by the pulse train generator and the first and second control signals to emit the substantially uniform pulse train in 5' such manner that in each complete period of the fourth pulse train the substantially uniform pulse train is constituted by the first pulse train in the absence of both the first and second control signals, by the second pulse train in response to the occurrence of the first control signal, and by the third pulse train in 10 response to the occurrence of the second control signal.

2. An arrangement as claimed in Claim 1 wherein n is an integral power of 2.

3. An arrangement as claimed in Claim 1 or Claim 2 wherein in respect of each digital signal the phase comparator is 15 responsive to the degree of fullness of the store falling below or exceeding the predetermined value by a given quantity to emit the first or second control signal respectively,

4. An arrangement as claimed in Claim 3 wherein the digital signals are binary signals and the given quantity is % bit. 20 5. An arrangement as claimed in Claim 4 wherein each store has eight one-bit storage cells and the period of the fourth pulse train is between l/tof and l/3Af, whereAf is the maximum deviation of the frequency of the original digital signal from the frequency of the digital signal in the main channel. . -17- 6. An arrangement as claimed in any of. Claims 1 to 5 wherein· in’respect of each digital signal the phase comparator comprises a comparator and .first and second stores and is arranged in each cycle.-of the read out of digits from the store to compare

5. A'number of a storage cell of the store into which storage is ·. effected with a number of a storage cell of the store from which read-out is effected and in response to the results of this ’comparison to set the first store or the second store or neither of the first and second stores to a predetermined state.

6. 10

7. An arrangement for restoring pulse trains of a plurality of digital signals substantially as herein described with referend to Figs. 4 to 9 of the accompanying drawings.