HUE047108T2 - Több attribútum mezõ készlet egyetlen laptáblázat bejegyzésben - Google Patents
Több attribútum mezõ készlet egyetlen laptáblázat bejegyzésbenInfo
- Publication number
- HUE047108T2 HUE047108T2 HUE13745243A HUE13745243A HUE047108T2 HU E047108 T2 HUE047108 T2 HU E047108T2 HU E13745243 A HUE13745243 A HU E13745243A HU E13745243 A HUE13745243 A HU E13745243A HU E047108 T2 HUE047108 T2 HU E047108T2
- Authority
- HU
- Hungary
- Prior art keywords
- table entry
- page table
- multiple sets
- single page
- attribute fields
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
- G06F12/145—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/656—Address space sharing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Memory System (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/565,434 US8938602B2 (en) | 2012-08-02 | 2012-08-02 | Multiple sets of attribute fields within a single page table entry |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| HUE047108T2 true HUE047108T2 (hu) | 2020-04-28 |
Family
ID=48916200
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| HUE13745243A HUE047108T2 (hu) | 2012-08-02 | 2013-07-18 | Több attribútum mezõ készlet egyetlen laptáblázat bejegyzésben |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US8938602B2 (enExample) |
| EP (1) | EP2880540B1 (enExample) |
| JP (3) | JP2015527661A (enExample) |
| KR (1) | KR102051698B1 (enExample) |
| BR (1) | BR112015001988B1 (enExample) |
| ES (1) | ES2763545T3 (enExample) |
| HU (1) | HUE047108T2 (enExample) |
| WO (1) | WO2014022110A1 (enExample) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9141559B2 (en) * | 2012-01-04 | 2015-09-22 | Intel Corporation | Increasing virtual-memory efficiencies |
| US9378572B2 (en) | 2012-08-17 | 2016-06-28 | Intel Corporation | Shared virtual memory |
| US9373182B2 (en) | 2012-08-17 | 2016-06-21 | Intel Corporation | Memory sharing via a unified memory architecture |
| US9436616B2 (en) | 2013-05-06 | 2016-09-06 | Qualcomm Incorporated | Multi-core page table sets of attribute fields |
| US20140331019A1 (en) * | 2013-05-06 | 2014-11-06 | Microsoft Corporation | Instruction set specific execution isolation |
| US9530000B2 (en) | 2013-06-14 | 2016-12-27 | Microsoft Technology Licensing, Llc | Secure privilege level execution and access protection |
| US9507726B2 (en) | 2014-04-25 | 2016-11-29 | Apple Inc. | GPU shared virtual memory working set management |
| US9563571B2 (en) | 2014-04-25 | 2017-02-07 | Apple Inc. | Intelligent GPU memory pre-fetching and GPU translation lookaside buffer management |
| US9921897B2 (en) | 2016-01-06 | 2018-03-20 | International Business Machines Corporation | Testing a non-core MMU |
| GB2547242B (en) | 2016-02-11 | 2018-05-23 | Advanced Risc Mach Ltd | Graphics processing |
| US10019377B2 (en) * | 2016-05-23 | 2018-07-10 | Advanced Micro Devices, Inc. | Managing cache coherence using information in a page table |
| US9864700B1 (en) * | 2016-08-17 | 2018-01-09 | Advanced Micro Devices, Inc. | Method and apparatus for power reduction in a multi-threaded mode |
| KR101942663B1 (ko) * | 2017-09-28 | 2019-01-25 | 한국과학기술원 | 가상 메모리 주소 변환 효율화를 위한 연속성 활용 주소 변환 방법 및 시스템 |
| US10747679B1 (en) * | 2017-12-11 | 2020-08-18 | Amazon Technologies, Inc. | Indexing a memory region |
| CN110198331B (zh) * | 2018-03-28 | 2022-11-25 | 腾讯科技（上海）有限公司 | 一种同步数据的方法及系统 |
| CN112115521B (zh) * | 2019-06-19 | 2023-02-07 | 华为技术有限公司 | 数据访问方法及装置 |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3454854B2 (ja) * | 1992-01-16 | 2003-10-06 | 株式会社東芝 | メモリ管理装置及び方法 |
| US6446034B1 (en) | 1998-12-16 | 2002-09-03 | Bull Hn Information Systems Inc. | Processor emulation virtual memory address translation |
| US6286092B1 (en) | 1999-05-12 | 2001-09-04 | Ati International Srl | Paged based memory address translation table update method and apparatus |
| US7444636B2 (en) | 2002-07-15 | 2008-10-28 | Hewlett-Packard Development Company, L.P. | Method and system of determining attributes of a functional unit in a multiple processor computer system |
| US7111145B1 (en) | 2003-03-25 | 2006-09-19 | Vmware, Inc. | TLB miss fault handler and method for accessing multiple page tables |
| US7673116B2 (en) | 2006-01-17 | 2010-03-02 | Advanced Micro Devices, Inc. | Input/output memory management unit that implements memory attributes based on translation data |
| US7539842B2 (en) | 2006-08-15 | 2009-05-26 | International Business Machines Corporation | Computer memory system for selecting memory buses according to physical memory organization information stored in virtual address translation tables |
| US7865675B2 (en) | 2007-12-06 | 2011-01-04 | Arm Limited | Controlling cleaning of data values within a hardware accelerator |
| US8015361B2 (en) | 2007-12-14 | 2011-09-06 | International Business Machines Corporation | Memory-centric page table walker |
| US8352670B2 (en) * | 2008-01-22 | 2013-01-08 | Globalfoundries Inc. | Execute-only memory and mechanism enabling execution from execute-only memory for minivisor |
| US8397049B2 (en) * | 2009-07-13 | 2013-03-12 | Apple Inc. | TLB prefetching |
| US20110016290A1 (en) | 2009-07-14 | 2011-01-20 | Arie Chobotaro | Method and Apparatus for Supporting Address Translation in a Multiprocessor Virtual Machine Environment |
| US8386745B2 (en) * | 2009-07-24 | 2013-02-26 | Advanced Micro Devices, Inc. | I/O memory management unit including multilevel address translation for I/O and computation offload |
| US20110161620A1 (en) | 2009-12-29 | 2011-06-30 | Advanced Micro Devices, Inc. | Systems and methods implementing shared page tables for sharing memory resources managed by a main operating system with accelerator devices |
| US8669990B2 (en) * | 2009-12-31 | 2014-03-11 | Intel Corporation | Sharing resources between a CPU and GPU |
| US20120233439A1 (en) | 2011-03-11 | 2012-09-13 | Boris Ginzburg | Implementing TLB Synchronization for Systems with Shared Virtual Memory Between Processing Devices |
-
2012
- 2012-08-02 US US13/565,434 patent/US8938602B2/en active Active
-
2013
- 2013-07-18 HU HUE13745243A patent/HUE047108T2/hu unknown
- 2013-07-18 BR BR112015001988-9A patent/BR112015001988B1/pt active IP Right Grant
- 2013-07-18 WO PCT/US2013/051069 patent/WO2014022110A1/en not_active Ceased
- 2013-07-18 JP JP2015525447A patent/JP2015527661A/ja not_active Withdrawn
- 2013-07-18 KR KR1020157005315A patent/KR102051698B1/ko active Active
- 2013-07-18 ES ES13745243T patent/ES2763545T3/es active Active
- 2013-07-18 EP EP13745243.9A patent/EP2880540B1/en active Active
-
2017
- 2017-10-19 JP JP2017202603A patent/JP2018041485A/ja not_active Withdrawn
-
2019
- 2019-02-01 JP JP2019016836A patent/JP6728419B2/ja active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US20140040593A1 (en) | 2014-02-06 |
| ES2763545T3 (es) | 2020-05-29 |
| KR20150038513A (ko) | 2015-04-08 |
| BR112015001988B1 (pt) | 2022-03-15 |
| WO2014022110A1 (en) | 2014-02-06 |
| EP2880540B1 (en) | 2019-09-25 |
| BR112015001988A2 (pt) | 2017-07-04 |
| EP2880540A1 (en) | 2015-06-10 |
| JP2019109906A (ja) | 2019-07-04 |
| CN104508641A (zh) | 2015-04-08 |
| KR102051698B1 (ko) | 2019-12-03 |
| JP2018041485A (ja) | 2018-03-15 |
| US8938602B2 (en) | 2015-01-20 |
| JP2015527661A (ja) | 2015-09-17 |
| JP6728419B2 (ja) | 2020-07-22 |
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