HU201622B - Circuit arrangement for controlling picture elements of display boards displaying alfanumeric and/or graphic information mixed according to the colour and brightness - Google Patents

Abstract

The present invention relates to a circuit arrangement that performs pixel control of modern light information equipment that may otherwise be implemented in conventional conditions under favorable conditions. The switching arrangement has pixel control circuits coupled to the actuator input (s) of the switching means (106) of the pixel light source (s), having a counter means and a storage device (101) adapted for receiving and transmitting pixel information. The reader outputs of the storage device (101) are coupled with the inputs (102a, b, c, d) of the counter chain (102) serving as a counting device. The switching arrangement is configured to connect a pulse source (107) controlled from a programmable container to a clock input (102h) of the chain (102h) providing a non-linear, non-linear, orbital (or downlink) pulse beam. The overflow outlet (102f) of the counting chain (102) is preferably coupled to a control input of a device for switching the light sources (106) through an inverter (103), preferably a semiconductor storage switch (105). (Figure 1, EN 201622 B Scope of the description: 8 pages, 4 drawings, Figure 4 -1-

Description

BACKGROUND OF THE INVENTION The present invention relates to a circuit arrangement which provides pixel control under state-of-the-art pixel control conditions which are otherwise conventional.

The switching arrangement is capable of providing gradation rendering according to brightness levels and displaying both black and white and color. The information content of the pixel is preferably incandescent, semiconductor, etc. display.

The purpose of similar devices of this type is that their application requires a high number of wires, high capacity storage, and their specific size determines both the specific cost requirement, reliability (P-factor) and operating speed limits. Therefore, various known, state-of-the-art solutions seek to vary the circuitry for retrieving and identifying the required information while maintaining the same scope and quality of service, and in particular the wiring and wiring of the circuit arrangement. optimize it.

The Hungarian patent application HU 187 540, which describes a state of the art, gives a good overview of the state of the art. In this solution, a digital comparator compares the required pixel information stored in the storage with the output state of a monotone variable (ascending or descending) number generator.

In the prior art, coded information (e.g., BCD code) represents the degree of luminosity to be applied to the pixel, and this coded information is transformed

non-linearly, known solutions to provide charge integral with linearity instead of nonlinearity of the focal angle influencing the visualization, since in this case there will be a step-by-step spacing between the ignition (or extinction) signals and the sinusoidal current so that all levels of luminosity are different from the neighbor in the same luminance increment. Reference is made to this in, inter alia, the Hungarian Patent Application No. VI-1212. In this known solution, this transformation is accomplished by comparing hue information with a nonlinear comparative signal. It may be necessary to control the level of brightness described above to ensure the shade of the image

- to fulfill other purposes, namely to modify the global brightness level of the whole (or a specific part of) the pixel array.

Further, it is known in the Hungarian patent application HU 189 864, which instead of comparing, incrementally determine a preset signal with a nonlinear function pulse set which is nonlinear according to the transform of the step signal and the charge integral. The purpose of the known solution is to utilize the system idle and the 20 ms period for color mixing, which is divided into three third periods in a time multiplex mode to process the information to be mixed according to the three basic colors. The solution itself controls the global brightness level of the entire pixel array with width modulated enable signals. Linear step signals are applied to the clock input, which are enabled or disabled by non-linear width modulated enable signals, depending on how the average brightness of the table, regardless of the pixel, is to be adjusted over a period of time. Thus, the known solution employs control signals that are not non-linear per pixel according to the desired pixel luminance, but uses known specific degrees of luminance that are one-pixel, representative of the colors stored in the temporary storage for the entire sequence, up for control.

In the prior art, brightness signals are used to influence the pulse width of a pulse generator signal and to apply a width modulated single-aperture signal to the control input allowing the switching of the pixel-by-pixel switch.

The invention is based on the discovery that the complexity can be further reduced by comparing the stored pixel information with the output state of a number generator, not an external, monotone and uniformized signal (p. 187,540), but nonlinear between the storage device and the pixel light source switch. switches a chain of accounts with a function clock clock. According to the invention, the read outputs of the storage device are coupled to the inputs of an account press.

According to our solution, the clock input of this chain is connected to a programmable storage source controlled by a nonlinear function-driven, non-solitary ascent (or decay) pulse set. The overcurrent output of the counter circuit is connected, preferably via an inverter, to a control input of a device for switching the light source (s), preferably a semiconductor switch.

The above definitions used by us are functionally understood. A variety of products from different manufacturers of semiconductor circuits can be used in the circuit layout of the present invention, and the data sheets developed by the companies for each circuit may refer to each terminal at different functional names. The circuit used at all times

EN 201622 Β such terminal point (s) as the readout output (s) of the storage medium, which, in the presence of an appropriate (e.g., readout) instruction, provides a serial and / or parallel state combination representing the information currently stored; clamp inputs are called input points, through which the initial state of the cycle per cycle is adjusted according to the information content of the incoming signals; changing said initial state step by step in the same sequence (ascending or descending) of the clock signals associated with the corresponding serial input ("clock input") of the account as a stepping stone during the cycle;

a terminal point that is called an overflow output that gives an output signal when a step signal that causes the saturation of the account to arrive at the clock input; a switch is referred to as a switch having an input of a pulse signal at its output which switches on a circuit other than a control current, such as a thyristor, a flip-flop with amplifier, from the pulse signal to another output signal.

BACKGROUND OF THE INVENTION The present invention relates to a circuit arrangement for controlling pixels of display panels displaying alphanumeric and / or graphical information according to degrees of brightness and optionally color tones, switching means for operating the light source (s) per pixel, and receiving pixels for controlling pixels and have a suitably designed storage device. The read outputs of the storage device are coupled to the inputs of the press of the counter serving as a counting device. The switching arrangement is configured to connect a clock pulse input to the clock signal of the account with a non-linear function-driven, programmable storage pulse source providing a non-linear rising (or falling) pulse set. The overcurrent output of the numerical chain is, preferably via an inverter, coupled to a light switching device, preferably via a semiconductor storage switch control.

In accordance with the present invention, the programmable storage is configured as a non-linear (e.g., sinusoidal) voltage of a circuit controlled by the storage switch, which is a linear, i.e., linear, luminous intensity storage for controlling the pulse source.

1 is a generalized and simplified block diagram of a pixel control circuit according to the present invention, FIG. 2 illustrates a portion of a matrix-structured light information board and data receiving information to be displayed. Figure 3 illustrates variations of the source of information to be displayed to the data input, Figure 4 illustrates the structure of a 6x10 elementary pixel circuit.

Figure 1 shows that the display device 106 is a light source 106 in a conventional manner

- in series with the main circuit branch of the semiconductor storage switch 105, such as a triac - switched between the Ut and 0 terminals of a power source. In the figure, the storage device 101 is, according to our example, a D storage device, a type 4076 integrated circuit. The data inputs 101a, b, c, d thereof are coupled to a 4-bit data combination representing the pixel to be displayed in BCD code. A clock function with linear function is applied to the 10le clock input. The current state of the storage device 101 is displayed on the read outputs 10h, i, k, 1. These reader outputs 10lh, i, k, 1 are coupled to the inputs 102a, b, c, d of the numerical circuit 102, exemplified by the integrated circuit 40,193. The superconducting output 102f of the numerical circuit 102 is formed by the so-called carry terminal of the integrated circuit 40,193. E2 is the output 102f

- via an inverter 103 and a resistor 104 implemented with a semiconductor device of type 14 049 - connected to the control input of the storage switch 105. The clock input 102h of the numerical circuit 102 is coupled to a pulse source output 107 controlled by a programmable storage that provides a nonlinear, non-linear, rising (or falling) pulse array.

Thus, the nonlinearity of the function sequence consists in the fact that the successive pulse signals do not follow one another in the form of phase shifts, and the interval between successive pulse signals varies. The input of the pulse source controller 107 is controlled from a programmable memory not shown separately in FIG. The storage device 101 is coupled to the horizontal select signal input 10Lf and the vertical select signal input 10Lg to the respective HS or VS signal. The l0lp, o, n, m, and 102g, i, e terminals are wired in the usual way out of the IC datasheets, while the lOlk terminals are not wired.

Figure 2 shows part of a 203 character field. Each 202 characters consists of 6x10 pixels. The board control circuit 201 provides the different timing signals derived from the CLT clock signal provided to the third input 201c, which in this example is a 4 MHz clock. Vertical selector switches VST signal to first input 201b, horizontal selector HST signal to second input 201a

HU 201622 uk after all. In the three-phase time division, the first output 201d, which is the output of the programmable storage, provides a per-column nonlinear function r, s, t, and the second 201 e output provides a per-line (linear function) CL1, .....

Cin Clocks. The third output 201f provides 3-bit column control BMO signals and the fourth output 201g provides 4-bit row control BMS signals. The fifth output 201h provides the receiving circuit 204 with CLA clock signals. 4-bit ADAT data signals representing the pixel information to be displayed per cycle are sequentially written to the input of the receiving circuit 204, and are connected in step by step to the respective row of column wires.

Figure 3 shows that the table controller HST and VST signals, the CLT clock signals and the 4-bit ADAT data signals can be provided to the video controller circuit 303 by a computer data source 301, preferably a personal computer 301. and the central and interface units 3011 and 3012), including a video generator 302, the symbols of which indicate that, in our example, there is a recorder 3021, an antenna 3027, a magnetic tape recorder 3022, and a monitor 3023, but of course may have other devices.

Figure 4 shows that the columns 401 of the character circuit 401 formed by pixels 11-16, 21-26, ..., 001-006 provide vertical selector VS signals for the column control BMO signals and the row control BMS signals for the lines of the character circuit 401 decoding circuit 403 provides horizontal selection HS signals. Each of the character circuits 401 in a column is simultaneously connected to the sequence step of the nonlinear ascending pulse set of nonlinear function paths, and to each of the character circuits 401 in a row is simultaneously connected to the corresponding clock signals CL1, ..., CLn.

The operation of the circuit arrangement according to the invention will now be described. For the sake of simplicity, we will not discuss the general features of the operation of such circuits, which are assumed to be known, and which are otherwise discussed in detail in the aforementioned Hungarian Patent Publication No. HU 187,540. It can be seen from the above that a storage device 101 and a number chain 102 are connected in a circuit directly controlling the switching of the light source 106, the so-called pixel control circuit. The superconducting output 102f of the numerical circuit 102 is coupled to the light source 106 via a semiconductor storage switch 105 via an inverter 103, which is common to multiple pixel switches. A 4-bit ADAT data signal representing the desired luminous intensity in BCD code is coupled to the data inputs 101a, b, c, d of the storage medium 101. This symbol thus distinguishes 2 ⁴ = 16 brightness levels. The respective incoming BCD encoded signal is stored in the storage medium 101 having both the selectable VS and HS signals and the CL clock signal being active.

The CL clock is a synchronous signal assigned to the row assigned to the particular cycle in the CL1, ..., CLn line by line timer which activates the character set 401 selected by the line separator HS signal and the column separator VS signal according to the time division defined for the matrix control. The row separator HS signal or column separator VS signal is generated by the decoding circuits 403 and 402, respectively, from the 4-bit row control BMS signal and the 3-bit column control BMO signal, with a value set of 10 and 6 pixels in the 6x10 character range. It will be appreciated that for other row and column widths, as for other gradation extensions, the achieved simplification applies mutatis mutandis, while the numerical ratio of savings and simplifications may be less than or greater than the ratio shown herein. .) The storage device 101 of the cycle 401 character cycle outputs a 4-bit ADAT data signal representing the luminous intensity predicted by the time division to the read outputs 10lh, i, k, 1, from which the count chain 102 is written. a, setting its initial (press) state. The incrementing of the numerical chain 102 thus starts from the initial state representing the required gradient in each cycle. In this case, the incremental rate of the control according to the invention is not linear according to the number of increments but the degree of luminosity which results in a nonlinear change in the flow angle. The increment can start at the specified luminous intensity from 0 to 16 from any intermediate value and is derived from the number of steps (non-linearly timed) that the numerical circuit 102 will overflow due to the ground state of the semiconductor switch 105 at output 102f. whereas the overcurrent signal, via inverter 103, extinguishes the semiconductor storage switch 105. For example, if the start state is 5, then step 16 from the start of the cycle will not trigger the semiconductor storage switch 105 to quench, but 16-5 = 11. a stepper signal which, according to the present invention, linearly decreases the flow angle of a given semiconductor storage switch 105 in a nonlinear fashion according to the step of the invention. If the initial state is 9, the extinction is triggered by step 7 and the flow angle:

HU 201622 Β η

ff = y af n where aí n = f n-f n-i and

1 -fn

In is the phase angle of the nth step within the phase range [0 - n / 2]. Of course, the phase angle of the first stepping signal is fo = 0, since the first of the 16 brightness levels is black, in which case the quenching stepping signal must appear in the beginning phase of the half-period, giving preset saturation; igniting a semiconductor 105 storage switch. Alternatively, if the start state is 0, the light source 106 will receive power throughout the semiconductor, the semiconductor storage switch 105 will be active for the duration, and the pixel intensity will be maximum. The control according to the invention thus requires the four-bit HS signal, the three-bit VS signal and the one-bit step signal to be transmitted to the pixel control circuit, i.e., 4 + 3 + 1 = 8 control wires are provided for each pixel, (2log16 = 4). The prior art HU 187 540 has a four-bit luminance signal for a 16-bit system, but with digital comparisons, the control signal requires 4 + 3 + 4 = 11, which is a significant extra. The prior art patent application HU 189 864 is capable of providing the same light point hue or hue at 6 bit wires, but the selection of the desired light spot switch requires at least 6 wires. Our solution saves more than 27% and 33% on wiring the control wires, not only greatly reduces material requirements, but also significantly simplifies assembly and yeasting (such as ringing) and reduces the amount of work required. Accordingly, the reliability of the system increases, operation and maintenance are simplified.

Thus, on the one hand, the invention improves the economy of the system, reduces the need for skilled labor, the need for management and maintenance, and, on the other hand, improves the reliability by reducing the complexity of the system.

Let us now look at Figure 2. For each of the 202 characters, a pixel control circuit, as shown in FIG. 1, is applied which receives said control signals from the corresponding output 201d, ..., h through the board control circuit 201 through eight wires. The board control circuit 201 receives from the video control circuit 303 of FIG. 3 the corresponding control HST and VST signals and the CLT clock signals, respectively. They may be provided by either a computer data source 301 or a video generator 302. Since the subject matter of the invention is not directly affected by the generation of video signals, it is not discussed here. The non-linear step signal is received by each of the character circuits 401 and within each of the pixel control circuits (FIG. 1). The time division serial synchronization signals are applied to the current queue as the clock clock CL1, ..., CLn. The four bit ADAT data signal representing the luminosity information is applied to a data receiving circuit 204 which in turn exits the step register and its parallel outputs sequentially to the next column conductor of the data combination in the sequence of character fields 203 and to each In this way, vertical coordinate control is implemented within the display panel. The column separator and row separator VS and HS signals derived from the column control BMO and row control BMS signals, respectively, define a vertical or horizontal coordinate within character field 401. The control within the character field 401 is illustrated separately in Figure 4. The board control circuit 201 (FIG. 2) receives the HST and VST signals and the CLT clock from the video control source (data source 301 or 302); Thus, the horizontal and vertical positions of the entire display board are selected, and a reference signal for generating timing signals (4 MHz in our example) is provided. The table control circuitry 201 breaks the selection into 401 character fields and generates a non-apertured leading edge or trailing edges), it derives the clock signals CL1, ..., CLn from the reference signal for the sequence selection and also provides clock signals to the receiving circuit 204. In this example, the operation is three-phase and network phases are assigned r, s , t is used to divide the font field into three phases, illustrated in Figure 2. Alternatively, three phase decomposition can be used to produce three basic color sync signals (color-guides).

The embodiment described above is exemplary; By using known sub-circuits and / or designing new circuits, a variety of variants may be provided to satisfy different services, the common feature of which is to link a number chain 102 and a storage device 101 in pixel control circuits, preset the number chain 102 with step data The non-linear, luminous intensity controlled by the programmable storage is executed by stepping signals 102, which are preferably proportional (linear, cosine, logarithmic, etc.).

EN 201622 Β An overflow signal triggers the shutdown of the storage switch 105 activated at the beginning of the semester, thereby adjusting the flow angle required for a given pixel intensity in a given cycle. 5

1-4. The various units, stages, circuits illustrated in Figures 1 to 5 are technologically interchangeable (hybrid circuitry, chip, circuit board combinations, etc.), any state-of-the-art implementation of any particular embodiment, and can be combined within the scope defined by these common features. This principle is also illustrated by the fact that in this exemplary embodiment, the pulse source 107 providing the nonlinear step signals denoted in FIG. 1, which is controlled by a programmable storage 15, is provided with an appropriate degree of board control circuit 201 so that output 201d output of a circuit called a pulse source.

It follows from the foregoing that the control may extend to hues of color, in which case what is said for multiple light sources per pixel applies mutatis mutandis to the light source 106, and the switching means is adapted accordingly.

The bit number of the row control, column control signals is the logarithm of the number of rows, columns.

Given the above, a person skilled in the art will be able to determine the pace of the pulse signals (step marks) in accordance with the particular operating characteristics, and for the sake of completeness, you have illustrated When preset to 15, the first step signal at 26 °, and when pressed at 0, the sixteenth step signal at 154 ° causes overflow in one case, and in the other case maximum power to the light source 106. The step marks follow each other at intervals such that after each additional phase interval the charge integral grows uniformly. Based on the data in the exemplary Table, the programmable storage implementing the exemplary function relationship of no problem to the expert, as well as the implementation of a possible connection with other functions.

SPREADSHEET

bright- ness degree 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 presets 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x (degrees, 26 44 55 62 69 75 81 87 93 99 104 111 118 126 136 154

Claims (7)

1. Circuit arrangement for controlling pixels of display panels displaying alphanumeric and / or graphical information according to luminance levels and, where appropriate, hues, by means of switching means (s), actuator input (s) and pixel control circuits, having a storage device adapted to receive and transmit pixel information, the read outputs of the storage device being coupled to the press inputs of a counter which serves as a counter, characterized in that the counter (102, clock input (102h) has a nonlinear a pulse source (107) is connected and the pulley output (102f) of the account chain (102) is provided - preferably on an inverter (103, and a light source case) (106) device, preferably a semiconductor storage switch (105) coupled to the control input. Circuit arrangement according to Claim 1, characterized in that the programmable storage, nonlinear, preferably sinusoidal voltage of the light source (s) (106) is linearly incrementally integrated, linearly incrementally integrated, preferably step-dependent, in accordance with the table function. trained as a container. The circuit arrangement according to claim 1 or 2, characterized in that the storage means (101) has a horizontal or vertical selection signal input (10lf, g), a clock input (10lle) and data inputs (101a, b, c, d). ) and the clock input (102h) of the counter (102) directly or indirectly via the corresponding output (201d) of the board control circuit (201), 5 e, f, g, h) are attached. The circuit arrangement according to claim 3, characterized in that the storage means (101, with a select signal input (10f, g)) are coupled to corresponding outputs of a decoding circuit (403, 402) and to the decoding circuits (403, 402). , - having a number of bits corresponding to the logarithm of the number of rows or columns - inputs with corresponding outputs of the board control circuit (201) 5 (201g, f) attached. 5. A circuit arrangement according to any one of claims 1 to 5, characterized in that the data inputs (101a, b, c, d, data receiving circuits (204) of the character circuits (401) belonging to each column of the display board) are connected to the same parallel data output. A circuit arrangement according to claim 5, characterized in that the data acquisition circuit (204) is a shift register with a number of parallel outputs corresponding to the number of columns. 7. A circuit arrangement according to any one of claims 1 to 5, characterized in That the first, second and third inputs (201a, b, c) of the board control circuit (201) and the data input of the receiving circuit (204) are coupled to one of the outputs of the video control circuit (303) and the video controller. It is coupled to the respective outputs of 5 circuits (303, a computer data source (301) and / or a video generator data source (302).