HU197648B - Circuit arrangement for time and frequency division multiplex separation of information appearing in time and field at the same time - Google Patents

Abstract

The present invention relates to a switching arrangement for separating time and frequency multiplexes of digital information simultaneously in space and time, and preferably for generating a code-dependent response code comprising responsive devices having a different register of contents (8). You have a polling device, the polling device and the answering devices are connected to a common data channel (1). The switching arrangement is configured such that each answering device is connected to the data channel (1) via a decoder (2). The outputs of the decoder (2) are connected to a start signal generator (4) and to a data register (5), the outputs of the start signal generator (4) are connected to a time signal generator (3). The output of the timer (3) is output to the clock input of the data register (5), the additional output of the start signal generator (4) is connected to the erase input of the data register (5). There is a code recognition comparator (6) which is connected to the outputs of the data register (5) and the code register (8) of the answering device. The control circuit (9) and the programming controller (7) are included, the output of the programming controller (7) is connected to the output of the time signaling (3) and its output is connected to the control circuit (9). The additional output of the programming controller (7) is

Description

The present invention relates to a circuit arrangement for separating time and frequency multiplexes of digital information occurring simultaneously in space and time. The present invention is applicable to any place where the content of the information is predetermined, relevant, its occurrence within the scope of the invention is not to be limited, nor is it intended to limit its co-occurrence. The solution can be used, for example, to identify objects, creatures, to determine the loading state or presence of moving vehicles. It can also be used in methods where interrogation signals transmitted by an interrogator are transmitted in block form and the beginning of the blocks is identified by an identification signal, and should be recognized depending on the presence or condition of the medium (person or object) carrying the arrangement of the invention. a response must be provided.

The nature of the data path is irrelevant to the scope of the invention, and the information is fed into the data channel by a known encoder and retrieved from there using a decoder. The structure of these circuits may vary according to the nature of the data channel and any known method may be used.

In the description of the invention, the interrogator code is the sequence of codes by which each answering device is called to respond. A response code is a sequence of signals generated by each response code device, such a circuit arrangement described in the present invention, which consists of its own identification code and / or code dependent upon the response device or its carrier state, e.g., physical or biological parameters. As used herein, a signal generator is a portion of a responding device that generates a response signal.

Prior art coders recognize a trigger signal to their own responder, which then emits a sequence of contents defined by ^the signal generators. However, the number of signal generators is increasing, and the frequently occurring simultaneous responses become invaluable to the resulting interferences. In one known way, to prevent this, the signal generators do not start the response signal immediately after receiving the guide code, but instead start a pseudorandom generator which transmits the transmitter at the times it determines, within the predetermined frequencies. Such a solution is known from DE 3 305 685.

By using the known solution, it is possible to isolate more than one signal data content of a signal generator to be identified at a time, or to identify them with a limited number of pieces. A disadvantage of the known solution is that it is expected to be statistically recognized, which means multiple allocations on the channel used, and thus the channel capacity limits the number of identifiers that can be identified on one channel at a time.

Alternatively, the number of so-called query sites is increased by limiting the number of identifiers that can be identified simultaneously in a given area to mathematically changing the number of tokens and query locations, time frequencies or multiplex channels. Such a solution is described, for example, in the Austrian ECOPLAN CONSULT GMBH P; REM; Description of the system called ID. The disadvantage of the known solution is that the number of multiplex channels is increased to a greater extent than would be required by the speed of the obtained information using other known solutions. A further disadvantage is the high cost of applying the procedure due to the increase in polling sites.

The object of the present invention is to provide a solution which eliminates the disadvantages of the known solutions and allows the detection of a large number of channels on a channel, in which the signal generators can be retrieved with high security without significant spatial limitation.

It has now been found that it is expedient to request all response markers operating in the system in a multiplex form on the same query channel. The presence or absence of a response code between two queries can represent the presence of a person or object in the space under investigation, while different physical interpretation of the content of the response code is possible depending on the content of the code (e.g. weight, volume, etc.)

Each answering device operating in a given system is provided with a code specific to it, and therefore the circuit arrangement according to the invention has a code register in which this code is stored. In accordance with the present invention, the known interrogator produces sequentially the interrogator codes in such a way that it provides a start signal before each interrogator code to indicate the start of a new interrogator. Between generating two different codes, it takes time for the answering device to respond so that the self-recognizing device can respond.

According to the present invention, the query code arriving to the responder is entered into the data register by the start signal. A control circuit compares the contents of the code register with the comparator with the contents of the data register at the rate of arrival. In the case of identity, a response signal is generated which is fed into the data channel. If the contents of the data register and the code register are not the same, the circuit layout is prepared for

-3197648 to receive another query code without sending any response to the data feed.

BACKGROUND OF THE INVENTION The present invention relates to a circuit arrangement for separating time and frequency multiplexes of digital information occurring simultaneously in space and time, and preferably for generating a code content dependent response code comprising transmitting devices having a code register per transmitting device. It has an interrogator having a coding and control circuit which sequentially generates codes of different contents from each code register. The interrogator and the interrogator are connected to a common data channel. The switching arrangement is configured such that each responding device is connected to the data channel via a decoder, the outputs of the decoder being connected to a time signal generator and a start signal generator, which are connected to a data register. It has a code recognition comparator, which is connected to a data register and a code register of the answering device for comparator input. It has a control circuit and a programming controller, the timing controller is connected to the input of the programming controller, and the output of the programming controller is connected to the control circuit. The code recognition comparator is connected to the programming controller and the control circuit, and the output of the control circuit is connected to the data channel via an encoder.

In a preferred embodiment of the circuit arrangement, the data register comprises an instruction register connected to an identification register, the instruction register being linked to a response register, the output of which is bound to an instruction decoder.

A possible exemplary embodiment of the circuit arrangement of the present invention will be described in detail with reference to the accompanying drawings, in which: - Figure 1 is a block diagram of the invention where only a simple response signal is transmitted after the codes are compared; a preferred block diagram in the case where an additional information block is present in the response code in addition to the response signal, FIG. 3 is a preferred embodiment of the block diagram of FIG. 1, and FIG. 4 is a further embodiment of the block diagram of FIG. represents a possible solution.

Fig. 1 is a block diagram of a switching arrangement according to the invention connected to a data channel 1 by its answering device. An interrogator, not shown in Figure 1, is connected to the same data channel 1. The

Figure 1 shows that a decoder 2 is connected to the data channel 1. The outputs of decoder 2 are connected to start signal generator 4 and data register 5. The time signal generator 3 is connected to the start signal generator 4, and the output of the start signal generator 4 and the time signal generator 3 are connected to the clock input of the data register 5.

The circuit arrangement according to Fig. 1 has a code recognition comparator 6 with input of data register 5 and a further input with code register 8. The circuit arrangement has 9 control circuits and 7 programming controllers. The timer 3 is connected to the input of the programming controller 7 and the code recognition comparator 6 is connected to its further input. The output of the programming controller 7 is connected to the control circuit 9, its other output is connected to the code register 8, and its control output is connected to the code recognition comparator 6, the timer 3 and the encoder 10. The output of the control circuit 9 is also connected to the encoder 10, which is also connected to the decoder 2, the time signal generator 3 and the start signal generator 4. The output of the encoder 10 is connected to the data channel 1.

The interrogator signal on the data channel 1, which is generated by the interrogator, not known in itself, is converted by the decoder 2 into a digital form for processing. The query signal to the input of the decoder 2, therefore, appears in its output in decoded form and accordingly supplies the logical levels corresponding to Data "1", Data "0", Start.

The time signal generator 3 is used to generate and verify the sequence of the digital signal and thus of the data coming from the data channel 1. The start signal generator 4 recognizes the start of the data block and initiates processing, and provides for the deletion of previous data at the end of the data block if no response signal is triggered.

The start signal generator 4, which is a monostable multivibrator for example in the embodiment of FIG. 3, generates a signal Ra which resets the data register 5 to allow data entry from the start signal to the end of continuous data reception by the VE signal from the control circuit 9. Otherwise, there is a continuous gap in the data register 5. The timing time of the start signal generator 4, preferably a monostable multivibrator, should be chosen to be longer than, but not more than one and a half times the time between, two continuously received data. This ensures that, due to data continuity shortcomings, the Ra signal can be used to erase data received so far. The loss of decoder 2 input signal will reset the circuit. The start signal generator 4 generates the CL.l character and the enable symbol E.

The time stamp generator 3 generates the CL shift signal for the data register 5 from the input CL.l and CL.2 input letters and the HE signal appearing on its input, and

-4197648

From this enable signal and the AV signal that will be described.

The outputs of the data register 5 display signals HK1 ... HKn which are output to the comparator input 6. The data register 5 also generates the AV signal. The code recognition comparator 6 receives further input from the code register 8 with the SK1-.SKn signals and the PE signal. The PV signal at the output of the comparator 6 triggers the programming controller 7 as described in FIG. The programming controller 7, by examining the appropriate code combination, decides whether it is only necessary to answer or at the same time accepts the question code appearing in the data register 5 as the new code of the respondent. To the start signal of the code recognizer 6 (in the case of a data match), the control circuit 9 transmits a response signal - the contents of the data register 5 - via the encoder 10 to the data channel 1. The programming controller 7 generates, as shown in FIG. 1, a step sequence CL3 which is fed to the control input of the code register 8 and a signal Rp, which also enters the code register 8 and the control circuit 9.

Figure 2 illustrates a preferred embodiment of the circuit arrangement wherein the data register 5 comprises an identification register 51 and an instruction register 52 associated therewith. The instruction register 52 is coupled to a response register 11 whose output is connected to an instruction decoder 12. The circuit arrangement of FIG. 2 describes a solution for transmitting commands addressed on data channel 1 and reprogramming code code 8 (i.e., changing the contents of code register 8) and obtaining additional information at the same time as the response code (e.g. physical or chemical data).

The structure of Figure 2 until the code content of the data block is recognized is the same as that of Figure 1. However, within the data register 5, the identification code and the instruction code are functionally separated and placed in the identity register 51 and the instruction register 52 respectively. The detailed operation of the code recognizer will be described in detail with reference to FIG.

From the data channel 1, the interrogation signal is transmitted to the input of the decoder 2 and is output in its decoded form as Data "1", Data "0" and Start signals, which are formed after proper signal formation using e.g. The Start signal is generated from the Data "1" and Data "0" signals by means of an edge circuit which performs a logical AND function. Data "1", Data "0", Start signals control the 4 Start signal generator, preferably comprising 41 monostable multivibrators. Data signals "1", Data signals "0" are connected to a logic OR function V1, the output of which is connected to the input TR of the monostable multivibrator 41 and to the input signal CL.l of the timer 3.

The start signal generator 4 has a further logic OR function V2 having one input connected to the logical AND output edge output (Start signal) and the other input to the Q output of the monostable multivibrator 41. The output of the V2 circuit which performs the logic OR function is connected to the Clear input of the monostable multivibrator 41.

The start signal generator 4 also has a logic NOR function NI circuit having one input connected to the Q output of the monostable multivibrator 41 and the other input to the Q output (VE signal) of the R-S storage 93 arranged in the control circuit 9.

At the output of the NI circuit implementing the logical NOR function, a signal Ra resetting the data register 5 is displayed, which also allows data to enter from the start of the Start signal until the end of continuous data reception. Otherwise, there is a continuous gap in the data register 5. The loss of the decoder 2 input signal will reset the circuit. The start signal generator 4 also generates the enable signal E, which is generated at the Q output of the monostable multivibrator 41, in addition to the reset signal Ra and the input CL.l.

The time stamp generator 3 generates a CL stepper for the data register 5 at the inputs of its input CL.l, CL.2, based on the corresponding logic relationship between the enable signal E and the ÁV and HE signals according to the following logical relationship:

CL = [(E + AV) * CL.l * HE] + CL.2 The above logical relation with the N2 circuit which performs the logical NOR function as shown in Figure 3, the logic AND function circuits N2, N3 and the logical

Preferably, the OR function is provided by circuit V3 by switching the enable signal E and the GV signal to the input of the N2 circuit which performs the logical NOR function. The output of the N2 circuit implementing the logical NOR function is connected to one of the inputs of the circuit E2 implementing the logical AND function and to the other input the input CL.l. The output of the logic AND function É2 is connected to one of the inputs of the logic AND function É3, the other input of which is the output Q of the R-S memory 93, i.e. the HE signal. The output of the logic AND function É3 is one of the inputs of the logic OR function V3, while the other input is the CL.2 input. The input CL.2 is formed from the output Q of the R-S storage 93 and from the output of the control oscillator 91 in the control circuit 9 via a logic AND function circuit E4. The output of the É4 circuit which implements the logic AND function is also connected to a 92 splitter circuit 92

The output of the -5197648 circuit is connected to the S input of the R-S storage 93.

3, the data register 5 and the code register 8 are preferably shift registers, the contents of which are compared by the code recognition comparator 6. The comparator 6 is, for example, an n + 1 bit digital comparator.

If the code recognition comparator 6 to view the data register 5 Q ,, Q _2, ... Q "outputs HR1, HK2, ... HKN signals of the eight code register Q ,, Q _2, ... Q" outputs SK1, SK2 identical ... with SKn signals, it outputs a call identifier I at its output, by means of which the RS storage 93 of the control circuit 9 initiates the CL.2 input signals, which, via the timer 3, starts the CL logic signals at its output to the contents of the data register 5 and thereby transferring it to the gravel 10. The encoder 10 performs the conversion of the data according to the nature of the data channel 1 and encodes it to the data channel 1.

For a n-bit call signal, the data register 5 is N + 2 bits long. The first bit takes the value of "l" as a result of the start signal and moves to the output Q _{n + 1 in} the data register 5 as a result of the CL signals. Thus, when the n + 1 data has been written, the first bit is displayed at the _{n + I} output of the data register 5, which provides the broadcast control AV signal and inter alia enables the call identifier I of the code recognition comparator 6 to be validated.

The transmit control AV signal is provided to one of the inputs of the logic AND circuitry E5 in the control circuit 9, while the other input is connected to the output of the logic OR function V4, which is input to the call identifier I and Rp. The output of the logic AND circuitry É5 is connected to the R input of the R-S memory 93.

The transmit control signal V, in addition to programming controller 7 also comes to where performing a logical AND function E6 is an input circuit, whose other input data register 5 reaches the Q _o output of the PV signal. The logical level of the PV signal corresponds to the value of the last received data. If the logical value of the PV signal is "1" then it is used to start programming, i.e. the value of the last bit of the received data determines the change of the contents of the code register 8, its programmability. Thus, if the last bit of the received data has a logical "1" value, then, irrespective of the state of the call identification signal I, the control circuit 9 initiates the CL.2 input signals by the appearance of the Rp signal through the circuit V4. The Rp signal is generated in the programming controller 7 at the output of the logic AND function É6 based on the logical equation Rp = AV + PV. This Rp signal is also fed to the Slot input of the code register 8. As a result, the contents of the code register space 8 are erased, so that the output of the code register 8, Q _n + i, becomes a PE signal which is logically zero and is input to the RS input 71 of the programming controller 7 RS. The output of the RS storage 71 is connected to one of the inputs of the logic AND function E7, the other input of which is the output of the time signal generator 3, i.e. the stepper signal CL. The output of the circuit É7, which implements the logical AND function, is coupled to the Clock input of the code register 8, on which a step sequence CL.3 is generated. As a result of the step sequence CL.3, the contents of the data register 5 are transferred to the code register 8. When programming, the response signal corresponding to the new code value entered is transmitted to data channel 1. The encoder 10 is encoded in a manner known per se, for example, by means of the appropriate logical network using the circuits fl, f2 shown in FIG.

If, in addition to the response signal, an additional block of information is provided in the response code, an identity register 51 and an instruction register 52 may be used as shown in FIG. By connecting the AV signal of the last bit of the ID register 51 to the input of the instruction register 52, which is, for example, S / P register (serial-parallel register) according to FIG. 4, the number of received bits is increased by, for example, r. Thus, in addition to the n bits of the calling code, r pieces of instruction bits are transmitted with the calling signal.

The code recognition comparator 6 provides a valid call identifier signal to the instruction register 52 and the response register 11, preferably also the S / P register (see FIG. 4), if the code is valid. As a result of the call identification signal 1, the contents of the two registers are exchanged through the parallel inputs A, ... A _r and A ', ... A' (outputs UK1, ... UKr and Ukl '... Ukr).

From the response register 11, the received instruction goes to the input of the instruction decoder 12, whereby the decoding logic activates one of the outputs P depending on the content of the instruction.

In the above case, the response signal formation is performed as described in Figure 3, the difference being only in the composition of the response signal. The response signal will contain, in addition to its own code, the contents of the response register 11, which is input to the response register 11 via a serial input SV before the calling code arrives or takes its instant value. Through the output UKr 'of the response register 11, reprogramming can also be performed as described in FIG.

The advantage of the circuit arrangement according to the invention is that, without increasing the required channel capacity, all transponder devices installed in the system are activated within a predictable time. The access time resulting from the number of respondents and the available channel capacity can be arbitrarily reduced by frequency multiplication of the channel of the response code. Further

-6197648 ⁹ megoldásunknak advantage that the exchange of information for the recipient váiaszkód radiation at the same time.

Claims (2)

PATENT CLAIMS A circuit arrangement for separating time and frequency multiplexes of digital information occurring simultaneously in space and time, and preferably generating a code dependent response code, comprising transponder devices having a code register having different contents per transponder, interrogator and transponder common data channel connected, characterized in that each responding device is connected to the data channel (1) via a decoder (2), the outputs of the decoder (2) are connected to a start signal map (4) and a data register (5), the outputs of the start signal generator (4) connected, the output of the time signal generator (3) is connected to the clock input of the data register (5), the other output of the start signal generator (4) is connected to the erase input of the data register (5); ) are connected to the inputs of the data register (5) and the code register (8) of the transponder device, comprising a control circuit (9) and a programming controller (7) connected to the input of the programming controller (7). its output is connected to the control circuit 10 (9), the further output of the program controller (7) is connected to the clock input of the code register (8), the output of the code recognition comparator (6) to the programming controller (7) and the control circuit (9) 15, each answering device comprises a code (10) whose output is connected to the data channel (1). The switching arrangement according to claim 1, characterized in that the data register (5) comprises an instruction register (52) connected to an identification register (51), the instruction register (52) being connected to a response register (11), the output of which is (12) connected.